JPH0520881A - Semiconductor output circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] The effect of inrush current can be prevented and the change timing of the output stage transistor can be adjusted with high accuracy. Even when multiple output stage transistors are configured, the change timing of each stage can be easily adjusted. A CMOS output circuit that can be used for A current mirror circuit composed of N channel MOS transistors 61 and 62 connected to the drain terminal of the input stage transistor 5 and a P channel MOS transistor 51 connected to the drain terminal of the input stage transistor 6.
A current mirror circuit composed of 52 is provided, and the gate terminals of the output stage transistors 7 and 8 are charged and discharged by the output of each current mirror circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor output circuit, and more particularly to a semiconductor output circuit constructed by using CMOS transistors.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram showing an example of a conventional CMOS output circuit. In FIG. 4, 1 is an input terminal,
2 is an output terminal, 3 is a power supply terminal, 4 is a ground terminal or a low voltage power supply terminal. Reference numerals 5 and 6 denote input-stage transistors, which drive the output-stage transistors 7 and 8.
Reference numeral 9 is a resistor connected between the drain terminals of the input stage transistors 5 and 6 and the gate terminals of the output stage transistors 7 and 8. Such a circuit is used as an output circuit of an integrated circuit having CMOS transistors, for example. .

FIG. 5 is a block diagram of an output circuit in the case where a plurality of output stage transistors in FIG. 4 are provided and a larger output current is taken out. 5, the same reference numerals as those in FIG. 4 denote the same or corresponding parts, and 71, 81, and 7
Reference numerals 2 and 82 denote drain terminals of the output stage transistors 7 and 8 and output stage transistors connected in parallel at the drain terminals. Reference numeral 91 denotes a connection point between the resistor 9 and the gate terminals of the output stage transistors 7 and 8 and the output stage transistor of the next stage. A resistor is connected between the gate terminals of 71 and 81, and a resistor 92 is similarly connected between the output stage transistors. In this way, a circuit configuration in which a plurality of circuits including the output stage transistors and the resistors are provided and a larger output current is taken out from the output terminal 2 can be obtained.

Next, the operation will be described. When a logical signal is input to the input terminal 1, the input stage transistors 5 and 6 are turned on and off, respectively, according to the signal level.
Now, assuming that a ground voltage is applied to the input terminal 1, the P-channel transistor 5 turns on and the N-channel transistor 6 turns off. As a result, current flows from the power supply terminal 3 through the drain terminal of the transistor 5 and the resistor 9 to the gate terminals of the output stage transistors 7 and 8, and the gate capacitance of the gate terminals of the output stage transistors 7 and 8 is charged.
The gate terminal voltage of the transistors 7 and 8 is the gate capacitance and the resistance 9 (the ON resistance of the transistor 5 is the resistance 9
It is sufficiently smaller than the resistance value of and can be ignored) and rises due to the time constant. When a power supply voltage is applied to the input terminal 1, the P-channel transistor 5 is turned off and the N-channel transistor 6 is turned on, so that the charges of the gate capacitors of the output stage transistors 7 and 8 are charged to the ground terminal 4 contrary to the above. And the gate terminal voltage drops.

By the above operation, the output stage transistors 7 and 8
The voltage between the gate and source terminals of changes with the above time constant. Therefore, if the change of the logic signal input to the input terminal 1 is alleviated and reduced, it is taken out from the output terminal 2 with a delay, and the output terminal when the level of the logic signal input to the input terminal 1 changes Inrush current from the power supply terminal 2 to the power supply terminal 3 and the ground terminal 4 via the output transistors 7 and 8 is reduced. This means that the potential fluctuations of the power supply terminal 3 and the ground terminal 4 due to the inrush current are reduced.

Further, as shown in FIG. 5, when the number of output stage transistors is increased in order to obtain a large current output, the inrush current also increases when each output stage changes simultaneously, which affects the power supply terminal 3 and the ground terminal 4. Also grows. However, each output stage transistor can be sequentially changed by providing resistors 91, 92 and the like between each output stage transistor and a time constant depending on the gate capacitance of each output stage transistor. That is, assuming that the ON resistances of the input stage transistors 5 and 6 are sufficiently smaller than that of the resistor 9, the change of the output stage transistors 7 and 8 is determined by the gate capacitance and the time constant of the resistor 9. Further output stage transistor 7
1, 81 changes according to the above time constant to the output stage transistor 7
The time constants of the gate capacitances 1, 81 and the resistance 91 are determined by the combined time constants. Hereinafter, similarly, the time constants up to the preceding stage are sequentially combined, and the change timing of each output stage is determined.

[0007]

Problems to be Solved by the Invention
S) Since the output circuit is configured as described above, the voltage V _GS between the gate and source terminals of the output stage transistor can be _calculated from the gate capacitance C, the resistance R, and the power supply voltages V _DD and V _{SS as} follows: V _GS = (V _DD −V _SS ) × (1−e ^{−t / RC} ), which indicates that the gate voltage of the output stage transistor changes logarithmically with time. Therefore, the gate electrode of the output transistor is charged and discharged using a time constant that changes logarithmically with the gate capacitance and the resistance, and there is a problem that it is difficult to set the time for the change of the output current.

Further, when the circuit as described above is formed on an integrated circuit, it is not necessary to form a resistor with high absolute accuracy or to form a resistor having a high resistance value in order to obtain a large time constant. This is difficult because of the restrictions on the manufacturing process and the restrictions on the pattern layout area. Therefore, there is a problem that it is difficult to accurately adjust and determine the change timing of each output stage transistor.

The present invention has been made in order to solve the above problems, and the change timing of the output stage transistor can be adjusted with high accuracy, and even when a plurality of output stage transistors are provided, the change timing of each stage is changed. It is an object of the present invention to obtain a CMOS output circuit which can be easily adjusted and which is less affected by the inrush current.

[0010]

In a semiconductor output circuit according to the present invention, first and second current mirror circuits are provided after each MOS transistor of an input stage CMOS transistor, and the gate of the output stage CMOS transistor is provided at the circuit output. The capacity is charged and discharged.

[0011]

According to the present invention, the first and second current mirror circuits are provided in the rear stage of each MOS transistor of the input-stage CMOS transistor, and the gate capacitance of the output-stage CMOS transistor is charged and discharged by the circuit output.
The change timing of the output stage transistor can be easily adjusted by adjusting the size of the transistor forming the current mirror circuit.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor output circuit according to an embodiment of the present invention will be described below. In FIG. 1, the same reference numerals as those in FIGS. 4 and 5 denote the same or corresponding portions, 51 and 52 are P-channel MOS transistors constituting the first current mirror circuit, and 61 and 62 are the second current mirror circuit. The drain terminals of the P-channel MOS transistor 52 and the N-channel MOS transistor 62 are output stage transistors 7 and 8.
Of the output stage transistors 7 and 8 are charged and discharged by a constant current by two current mirror circuits. And these 2
The drain terminals and gate terminals of the transistors 51 and 61, which form the input of one current mirror circuit, are connected to each other, and are connected to the drain terminals of the input stage transistors 6 and 5, respectively.

Next, the operation will be described. Now, assuming that the power supply voltage is applied to the input terminal 1, the P-channel transistor 5 is in the OFF state and the N-channel transistor 6 is in the ON state, so that the transistor 51 and the output stage transistor 6 forming the first current mirror are formed. A constant drain current flows through the power supply voltage and the size of these transistors. The gate terminal of the transistor 51 is connected to the gate terminal of the transistor 52,
The drain current flowing through the transistor 51 and the transistor 52 is proportional to the size of each transistor.

The drain terminal of the transistor 52 is connected to the gate terminals of the output stage transistors 7 and 8, and the gate capacitance is charged by the output current of the transistor 52 which constitutes the first current mirror circuit.
This voltage becomes the gate-source terminal voltage V _GS of the output stage transistors 7 and 8. The output stage transistor 8 is an N-channel MOS transistor, and when this voltage V _GS exceeds the threshold V _TH of the transistor 8, the transistor 8 is turned on.
As the gate voltage rises, the drain current also increases and the output current drawn from the output terminal 2 increases.

Similarly, when the input terminal 1 is at the ground voltage, the input stage transistor 5 is turned on, and the current determined by the transistor 5 and the transistors 61 and 62 forming the second current mirror circuit is changed. It flows into the transistor 61, discharges the gate capacitance of the output stage transistors 7 and 8, and the voltage thereof drops. The output-stage transistor 7 is a P-channel MOS transistor, and if the voltage V _GS exceeds its threshold value V TH, the transistor 7 is turned off.
In the N state, the drain current increases as the gate voltage decreases, and the output current flowing out from the output terminal 2 increases.

As described above, in response to the change in the logic signal at the input terminal 1, the input stage transistors 5 and 6 and the first and second transistors are provided.
Transistors 51 and 5 forming the current mirror circuit of
2, 61, 62 current and output stage transistor 7,
The change in the output current of the output terminal 2 is alleviated by the charge / discharge time due to the gate capacitance of 8. Therefore, from the output terminal 2 through the output stage transistors 7 and 8, the power supply terminal 3 and the ground terminal 4
The inrush current into is reduced.

The sizes of the transistors 51 and 52 that form the first current mirror circuit and the transistors 61 and 62 that form the second current mirror circuit are adjusted, for example, the size of the transistor 52 is reduced to reduce the gate capacitance. Output terminal 2 by delaying the charging time of
The rise time and fall time of can be adjusted separately.

In the above embodiment, the logical value of the output terminal 2 is obtained by inverting the logical value of the input terminal 1, but it is the same as the input terminal by inserting a one-stage inverter into the circuit. The logical value of may be obtained at the output terminal.

As described above, in this embodiment, the current mirror circuit composed of the N-channel MOS transistors 61 and 62 connected to the drain terminal of the input-stage transistor 5 and the P-channel MOS transistor 51 connected to the drain terminal of the input-stage transistor 6. , 52 is provided, and the gate terminals of the output stage transistors 7 and 8 are charged and discharged by the output of each current mirror circuit. Therefore, the gate-source voltage V _{GS of the} output stage transistors 7 and 8 is And the relationship between time and gate capacitance is C,
If the constant current of the current mirror circuit is I, V _GS =
It is expressed as (I / C) × t, and the relationship between the gate-source voltage V _GS and the charging / discharging time t changes linearly with time. Further, the resistance element can be removed from the constituent elements, and when the resistance element is formed on the integrated circuit, the pattern layout area can be reduced.

Next, a second embodiment of the present invention will be described. In this embodiment, a CMOS output circuit having a plurality of output stage transistors is combined with the above configuration, and as shown in FIG. 2, the transistors of the current mirror circuit are additionally provided in the same manner as the output stage. That is, the drain terminals of the transistors 53 and 63 of the current mirror circuit are connected to the gate terminals of the added output stage transistors 71 and 81. The drain terminals of the output stage transistors are commonly connected to the output terminal 2, and the output currents of the respective stages are combined and output to the output terminal 2.

Next, the operation will be described. Now, each P-channel MO of the output stage transistors 7, 8 and 71, 81
If the S transistor and the N channel MOS transistor have the same transistor size and the same threshold value V _TH , the gate capacitance of each output stage is also the same, and the change of each output stage changes the current mirror driving it. It is determined by the output current of the circuit. Then, due to the current ratio between the stages of the current mirror circuit, there is a time lag in the change of each output stage, and the output is made by the current by the transistors that configure each current mirror circuit and the charge / discharge time by the gate capacitance of each output stage transistor The change in the output current of the terminal 2 is alleviated, and the change timing of each stage can be easily adjusted.

Also in the above configuration, the transistors 51, 52, 53 and 6 forming each current mirror circuit are formed.
By adjusting the sizes of 1, 62, and 63, it is possible to generate a time difference in the output current change of each output stage transistor according to the current ratio.

Further, by changing the size of the input transistors 5 and 6 on the current source side of the current mirror circuit, the current value can be changed while keeping the ratio of the output currents of the respective current mirror circuits constant. . As a result, the change time of the output stage can be adjusted at the same time while maintaining the ratio of the time difference.

Further, FIG. 3 is a circuit diagram showing a third embodiment of the present invention, in which transistors 51, 52, 53 or 61, 62, 63 constituting a current mirror circuit and output stage transistors 7, 8, 71 are provided. , 81 between the gate terminals of the transistors 54, 55 and 64, which serve as a switch circuit,
65 is inserted, and the gate terminal of each transistor is connected to the drain terminals of the input stage transistors 5 and 6. Further, 11 and 12 are setting terminals for the external current source 94 or the external resistor 93, and are transistors 51, 52, 53 and 61, 62, 6 forming a current mirror circuit.
This is for allowing the current setting of No. 3 to be set from the outside.

With this structure, the rise and fall times of the current output from the output terminal 2 can be adjusted from the outside.

In the above first embodiment, similarly,
Transistors 51 and 61 forming a current mirror circuit
A current may be supplied from the outside to adjust the rise and fall times of the current output from the output terminal 2 from the outside.

[0027]

As described above, according to the semiconductor output circuit of the present invention, each MO of the input-stage CMOS transistor is
Since the first and second current mirror circuits are provided in the subsequent stage of the S transistor and the gate capacitance of the output stage CMOS transistor is charged and discharged by the circuit output, the size of the transistor forming the current mirror circuit can be adjusted. It is possible to easily adjust the change timing of the output stage transistor, and even when multiple stages of output stage transistors are provided, the change timing of each stage can be easily adjusted and the semiconductor output is less affected by the inrush current. There is an effect that a circuit can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a semiconductor output circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a semiconductor output circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a semiconductor output circuit according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing an example of a conventional semiconductor (CMOS) output circuit.

FIG. 5 is a circuit diagram showing another example of a conventional semiconductor (CMOS) output circuit.

[Explanation of symbols]

1 Input Terminal 2 Output Terminal 3 Power Supply Terminal (V _DD ) 4 Ground Terminal or Low Potential Power Supply Terminal (V _SS ) 5,6 Input Stage Transistor 7, 8 Output Stage Transistor 54, 55, 64, 65 Switch Circuits 51, 52 61 , 62 Transistors 71, 81 forming current mirror circuit Output stage transistor

[Procedure amendment]

[Submission date] December 3, 1991

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 1

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction content]

Next, the operation will be described. Assuming that a state where the power supply voltage to the input terminal 1 is applied, P-channel transistor 5 is OFF state, N = channel transistor 6 is turned ON, the transistor 51 constituting the first current mirror input stage transistor A constant drain current flows through 6 depending on the power supply voltage and the size of these transistors. The gate terminal of the transistor 51 is connected to the gate terminal of the transistor 52,
The drain current flowing through the transistor 51 and the transistor 52 is proportional to the size of each transistor.

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] 0015

[Correction method] Change

[Correction content]

Similarly, when the input terminal 1 is at the ground voltage, the input stage transistor 5 is turned on, and the current determined by the transistor 5 and the transistors 61 and 62 forming the second current mirror circuit is changed. flows through the transistor 6 2, discharges the gate capacitance of the output stage transistors 7 and 8, the voltage drops. The output-stage transistor 7 is a P-channel MOS transistor, and if the voltage V _GS exceeds its threshold V _TH , the transistor 7 will be O.
In the N state, the drain current increases as the gate voltage decreases, and the output current flowing out from the output terminal 2 increases.

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] 0024

[Correction method] Change

[Correction content]

Further, FIG. 3 is a circuit diagram showing a third embodiment of the present invention, in which transistors 51, 52, 53 or 61, 62, 63 constituting a current mirror circuit and output stage transistors 7, 8, 71 are provided. , 81 between the gate terminals of the transistors 54, 55 and 64, which serve as a switch circuit,
The gate terminals of the respective transistors forming the switch circuit are connected to the drain terminals of the input stage transistors 5 and 6. Also 11, 1
Reference numeral 2 is a setting terminal for the external current source 94 or the external resistor 93.
This is for allowing the current setting of 52, 53 and 61, 62, 63 to be set from the outside.

Claims (4)

[Claims] 1. An input-stage CMOS transistor whose gate terminal is connected to a power source, and an output-stage CMOS transistor whose drain terminal is connected to an output terminal,
Input stage CMOS transistor drain output is output stage C
A semiconductor output circuit configured to charge and discharge the gate capacitance of a MOS transistor, comprising first and second current mirror circuits provided after each MOS transistor of the input-stage CMOS transistor, the first and second current mirror circuits being provided. 2. A semiconductor output circuit characterized in that the gate capacitance of the output stage CMOS transistor is charged / discharged by the output of the current mirror circuit of 2. 2. The semiconductor output circuit according to claim 1, further comprising a plurality of output stage CMOS transistors, wherein the first and second current mirror circuits correspond to the number of the plurality of output stage CMOS transistors. A semiconductor output circuit comprising a plurality of semiconductor output circuits. 3. The semiconductor output circuit according to claim 1, wherein the first or second current mirror circuit is configured by combining transistors having different sizes. 4. The semiconductor output circuit according to claim 1, wherein an external drive current supply means for supplying a predetermined current to the first and second current mirror circuits and controlling the operation thereof, and the first and second current mirror circuits. And a switch means which is provided between the current mirror circuit of No. 2 and the gate terminal of the output-stage CMOS transistor of the subsequent stage, and supplies the output of each current mirror circuit to the gate terminal of the output-stage CMOS transistor of the subsequent stage at a predetermined timing. A semiconductor output circuit characterized by: