JPH05211307A - Nonvolatile memory cell - Google Patents

Abstract

PURPOSE:To prevent generation of distortion by a method wherein a semiconductor layer is formed on a substrate, a source and drain electrode is formed by separating the semiconductor layer, an active part and a memory storage are formed separately. CONSTITUTION:On an active part, a polycrystalline silicon semiconductor layer is formed on an insulated substrate 3. Source and drain regions 5 and 6 are separated by implanting P-ions into the surface of the polycrystalline silicon semiconductor layer, contact layers 7 and 8 are formed on the source and drain regions 5 and 6, and source and drain electrodes 9 and 10 are formed thereon. A SiNX gate insulating film 11 is formed on the surface of the part where the source and drain regions 5 and 6 are separated, and an Al gate electrode 12 is formed thereon. On a memory part 2, an electrode 13, consisting of Pt and the like, is formed on the substrate 3, a ferroelectric substance thin film 14, consisting of lead titanate, is formed thereon as a non-volatile memory part, and an Al electrode 15 is formed thereon. As the active part 1 and the memory part 2 are separated, the distortion due to the difference in thermal expansion coefficient between the semiconductor and the ferroelectric substance when heated can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a dielectric of a memory section,
The present invention relates to a structure of a non-volatile memory cell using a ferroelectric thin film.

[0002]

2. Description of the Related Art A semiconductor memory is a RAM from a storage state.
(Random Access Memory) and SAM (Sequential Acces
s Memory), and these are in principle RWM (Read Write Memory) and ROM (Rea
d Only Memory), which does not require power to maintain the stored contents and does not lose stored contents even when the power is turned off. What loses its content is called volatile memory.

Of these, the RWM RAM is generally called "RAM", and this "RAM" is further divided into static RAM (SRAM) and dynamic RAM (DRAM) from the driving means. The SRAM is composed of a flip-flop circuit, and it is difficult to increase the degree of integration due to its complicated structure. On the other hand, since the storage state can be held with a small amount of power, the power consumption is small and the writing / reading operation is performed. Has the characteristic of being fast.

On the other hand, the DRAM is composed of a capacitor which is a storage section and a transistor which is an active section which controls the storage section. In order to maintain the charge stored in the capacitor, an update operation called refresh is performed. Since it is necessary, it has a drawback of relatively high power consumption, but has a feature that the degree of integration can be increased due to the simple structure of the memory cell, and is widely used as a main memory device of a computer. ..

On the other hand, ROM, which is a non-volatile memory that does not require electric power for storage, includes a mask ROM in which information is written at the manufacturing stage and a PROM (Programmable ROM) in which a user can write information later. This P
The ROM is an EPROM (UV-Erasable PR) that is electrically written and erased by irradiating it with ultraviolet rays.
OM) and EEPROM for electrically writing / erasing
(Eletrically-Erasable PROM).

By the way, in recent years, the International Solid State Circuit Conference (ISS)
MOS in DRAM introduced in CC 88)
A RAM using a ferroelectric thin film as a dielectric of a capacitor used in a storage unit in combination with a field effect transistor (MOSFET) is an FRAM (Ferroelectric RAM).
It is called a RAM, it is non-volatile because it does not require power for memory storage, it is suitable for integration due to its simple structure, it can be driven at a low voltage in a wide temperature range, and α-rays are used. It is attracting attention due to its resistance to soft errors.

This FRAM is disclosed in JP-A-2-94571, JP-A-2-94553, and JP-A-2-290.
As disclosed in Japanese Laid-Open Patent Publication No. 079, it is configured by forming a ferroelectric thin film on a source region on a single crystal wafer or on a gate insulating film.

However, since the area of a single crystal silicon wafer is limited, it is necessary to achieve high integration in order to obtain a larger capacity FRAM using a conventional single crystal. For that purpose, High-level fine processing technology such as submicron processing technology is required. Therefore, there is a problem that a large capacity memory cannot be obtained by the conventional FRAM using the single crystal silicon wafer.

To solve this problem, the operating semiconductor layer may be composed of polycrystalline silicon or single crystal silicon. However, when amorphous silicon is heated to polycrystal or single crystal, the layer below The ferroelectric layer is also heated and changes in volume, which may cause distortion or cracks.

Further, when the semiconductor layer and the ferroelectric layer are brought into direct contact with each other, the polarization charge of the ferroelectric material is not completely canceled by the charge on the semiconductor surface, so that the electric field in the direction opposite to the spontaneous polarization is applied to the ferroelectric material. Since it occurs in the thin film, spontaneous polarization may become thermodynamically unstable.

On the other hand, Japanese Patent Laid-Open No. 3-22483 discloses a memory electrode formed on a glass substrate, a ferroelectric thin film formed so as to cover the memory electrode, and an amorphous semiconductor formed on the ferroelectric thin film. Layer, a contact layer formed separately on the surface of the amorphous semiconductor layer, and a FRAM composed of a source electrode and a drain electrode formed on each contact layer
Is listed.

Since this FRAM uses a heat-resistant glass insulating substrate which can easily obtain a large area, not a single crystal silicon wafer having a limited size as a substrate, it uses an advanced fine processing technique. Although it is possible to obtain a large-capacity memory without using it, there is a problem in that since the operating semiconductor layer is amorphous, carrier mobility is low and writing / reading operation cannot be speeded up. ing.

In order to solve this problem, the operating semiconductor layer may be made of polycrystalline silicon or single crystal silicon. However, when amorphous silicon is heated to polycrystal or single crystal, the underlying layer is formed. The ferroelectric thin film is also heated to cause a volume change, and strain or crack may occur near the interface between the ferroelectric thin film and the semiconductor layer.

Further, since the ferroelectric layer is formed on the silicon semiconductor layer, Pb atoms or O atoms in the ferroelectric film, which are harmful to the silicon semiconductor layer, may get into the silicon semiconductor. There is.

[0015]

SUMMARY OF THE INVENTION The present invention has the above-mentioned problem, namely, it has a high carrier mobility and a fast write / read operation, but cannot obtain a large-capacity memory. Writing / writing due to the problems and low carrier mobility
A problem that an FRAM using an amorphous semiconductor has, that a read operation cannot be speeded up, and a problem that spontaneous polarization in a ferroelectric thin film may not be thermodynamically stable and that a silicon semiconductor layer Harmful Pb
An object of the present invention is to obtain an FRAM having a novel structure in which atoms or O atoms do not enter the silicon semiconductor.

[0016]

In order to solve the above-mentioned problems, the present application states that "an active part and a memory part are formed adjacent to each other on an insulating substrate, and the active part is formed on the insulating substrate. A semiconductor layer, a source region and a drain region formed separately on the surface of the semiconductor layer, a contact layer formed on each of the source region and the drain region, a source electrode and a drain electrode formed on each contact layer, The memory portion is composed of a gate insulating film formed on the surface of a portion separated from the source region and the drain region on the semiconductor layer, and a gate electrode formed on the gate insulating film.
It consists of a storage electrode formed on an insulating substrate, a ferroelectric thin film formed on the storage electrode, and a connection electrode formed on the ferroelectric thin film.The source electrode of the active section and the connection electrode of the storage section are electrically connected. A non-volatile memory cell characterized in that it is connected to.

[0017]

In the present invention having the above structure, the amorphous semiconductor layer formed on the insulating substrate is heated to be polycrystallized or monocrystallized to form a transistor, and the ferroelectric substance is adjacently formed. A capacitor having a thin film as a dielectric is formed. According to this structure, the non-volatile memory operation is performed by changing the spontaneous polarization value induced in the ferroelectric substance by the voltage applied to the memory electrode.

Since the memory cell of the present invention can obtain a large-area memory unlike a conventional one using a single crystal silicon semiconductor wafer, a large-capacity memory can be obtained without using an advanced fine processing technique. Obtainable.
Further, since the formed semiconductor layer is not an amorphous silicon semiconductor layer but a polycrystalline silicon semiconductor layer or a single crystal silicon semiconductor layer, a large carrier mobility can be obtained and a sufficient writing / reading speed can be obtained. In addition, since the ferroelectric layer is sandwiched between the metal electrodes, the spontaneous polarization is stable, and the active part and the memory part are formed separately from each other. Therefore, no strain or crack is generated due to the difference in thermal expansion coefficient between the semiconductor and the ferroelectric.

Further, since the metal layer is formed between the ferroelectric thin film and the silicon semiconductor layer, Pb atoms or O in the ferroelectric film which is harmful to the silicon semiconductor layer.
Atoms and the like can be prevented from entering the silicon semiconductor.

[0020]

Embodiments of the present invention will be described with reference to the drawings.
FIG. 1 (a) shows that the invention of the present application is one transistor + 1
FIG. 3 is a schematic diagram of a configuration of an embodiment applied to a capacitor type DRAM memory cell, and its schematic diagram is shown in FIG.

This nonvolatile memory cell is formed on an insulating substrate 3 made of heat-resistant glass or the like. This insulating substrate 3 has a large area, and a large number of nonvolatile memory cells are formed on it.

In the memory cell of the present invention, the active portion 1 which is a transistor and the storage portion 2 which is a capacitor are the insulating substrate 3.
It is configured by being formed adjacent to the above.

The active portion 1 has a structure in which a polycrystalline silicon semiconductor layer 4 having a thickness of 0.15 to 0.2 μm is formed as a semiconductor layer on the insulating substrate 3. The polycrystalline silicon semiconductor layer 4 is formed by forming an amorphous silicon semiconductor layer on the substrate by low pressure chemical vapor deposition (LPCVD) at a substrate temperature of 550 ° C. using silane (SiH ₄ ) gas as a raw material. The silicon semiconductor layer is placed in a N ₂ atmosphere at 600 ° C. for 24 hours.
It is formed by solid phase growth for a time.

The source region 5 and the drain region 6 are formed separately by implanting phosphorus (P) with an ion implantation amount of 5 × 10 ¹⁵ / cm ² into the surface of the polycrystalline silicon semiconductor layer by an ion doping method. ..

A contact layer 7 is formed on the source region 5, a contact layer 8 is formed on the drain region 6, and a source electrode 9 and a drain electrode 10 made of Al are formed on the contact layers 7 and 8. ing. The contact layers 7 and 8 can be omitted.

A SiN _x gate insulating film 11 is formed on the surface of a space between the source region 5 and the drain region 6 by a sputtering method or a CVD method, and a gate electrode 12 made of Al is formed on the gate insulating film. ing.

In the memory portion 2 formed adjacent to the active portion 1, an electrode (referred to as “memory electrode”) 13 made of platinum (Pt) or the like is formed on the insulating substrate 3, and the memory electrode 2 is formed on the memory electrode 13. The film thickness of the storage unit of the non-volatile memory is 0.6
A ferroelectric thin film 14 of lead titanate (PbTiO ₃ ) having a thickness of up to 0.8 μm and an electrode (referred to as a “connecting electrode”) 15 of Al formed on the ferroelectric thin film 14 are formed.

The ferroelectric thin film 14 is made of lead oxide (PbO) and titanium oxide (TiO ₂ ) as raw materials and has a substrate temperature of 600.
It is formed by a magnetron sputtering method in an Ar / O ₂ atmosphere at a temperature of about 1 Pa and is adjusted so that the formed film composition has a stoichiometric composition ratio.

Further, the connection electrode 15 of the storage section 2 is electrically connected to the gate electrode 9 of the active section 1, and the active section 1
An insulator 16 is formed between the storage unit 2 and the storage unit 2 to electrically isolate them.

The insulator 16 is not always necessary, and can be omitted if the memory section and the active section are electrically separated.

FIG. 1B shows an equivalent circuit of the nonvolatile memory cell shown in FIG. The active portion 1 of this non-volatile memory cell is composed of a source S, a gate G and a drain D as in the case of an ordinary field effect transistor (FET) as shown in FIG. It is connected to the gate G as a capacitor using the ferroelectric thin film 14 as a body. As a result, the memory cell of the present invention has non-volatility due to the hysteresis characteristic of the ferroelectric thin film 14.

The memory cell of the present invention may be formed of a single crystal silicon semiconductor layer as a semiconductor layer instead of the polycrystalline silicon semiconductor layer. In that case, the single crystal silicon semiconductor layer is formed by heating a polycrystalline silicon semiconductor layer formed over an insulating substrate with a heating means such as an electron beam or a laser beam to recrystallize it.

The structure of the non-volatile memory of the present invention is as follows.
The present invention can be sufficiently applied even when a single crystal silicon wafer is used instead of a silicon semiconductor layer formed on an insulating substrate.

Further, although the description has been made on the assumption that the semiconductor layer is not an amorphous silicon semiconductor layer having a low carrier mobility, in the structure in which the ferroelectric thin film is covered with the semiconductor layer, the difference in thermal expansion between the two is caused during heating. Since a problem of cracking occurs with this, the configuration of the present invention can be applied to a nonvolatile memory cell using an amorphous silicon semiconductor.

In the above description, the case where a single memory cell is formed has been described. However, a commonly used memory is not composed of a single memory cell but a plurality of memory cells on a substrate. Are formed. In this normal memory, when the interaction between the electrodes and / or between the cells becomes a problem, it is necessary to electrically separate the electrodes and / or the cells. In that case, it goes without saying that it is necessary to form an interlayer insulating film and / or a passivation film or the like for electrically isolating between wirings and / or between cells in order to configure such a memory. ..

Further, like the SRAM, a polycrystalline silicon thin film is used to form a CMOS flip-flop, and a ferroelectric thin film is used as the dielectric of the capacitor to improve the write / read time and the number of rewrites. It is also possible to improve.

FIG. 3 shows a schematic diagram of the configuration of another embodiment of the present invention. The 1-transistor + 1-capacitor DRAM type memory cell shown in this embodiment is different from the embodiment in which the source region 7 and the drain region 8 are formed separately on the surface of the silicon semiconductor layer shown in FIG. The region 8 is formed over the entire thickness of the semiconductor layer. By adopting such a configuration, the electric field formed between the source region 7 and the drain region 8 becomes a uniform electric field, so that the control by the gate electrode is more effectively performed.

It is needless to say that the present invention can be applied not only to the memory cell having the simple shape described in the embodiment but also to a commonly used trench capacitor or stacked capacitor. Nor.

The dielectric of the capacitor of the memory portion in the memory cell applied to the trench capacitor is not a stack of ferroelectric thin films as in the case of FIG. 1, but a trench (groove) provided in the semiconductor layer. It is formed by forming a ferroelectric layer thin film on the peripheral wall.

[0040]

As is apparent from the above description, since the nonvolatile memory cell of the present invention can easily obtain a large area, unlike the conventional one, it is possible to use the non-volatile memory cell without using the fine processing technology. Since a large capacity memory can be obtained and a large carrier mobility can be obtained, a sufficient write / read speed can be obtained. In addition, since the ferroelectric layer is sandwiched between the metal electrodes, the spontaneous polarization is stable, and the active portion and the memory portion are formed so as to be spatially separated from each other. There is no strain or crack due to the difference in the coefficient of thermal expansion of the ferroelectric.

[Brief description of drawings]

FIG. 1 is a circuit diagram of the present invention including one transistor and one capacitor DR.
1 is a schematic configuration diagram and an equivalent circuit diagram of an embodiment applied to an AM type memory cell.

FIG. 2 is one transistor plus one capacitor D shown in FIG.
FIG. 3 is a schematic diagram of an example of a RAM type memory cell.

FIG. 3 shows the present invention in which 1 transistor and 1 capacitor DR are used.
The schematic diagram of the structure of the other Example applied to the AM type memory cell.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Active part 2 Storage part 3 Insulating substrate 4 Semiconductor layer 5 Source region 6 Drain region 7,8 Contact layer 9 Source electrode 10 Drain electrode 11 Gate insulating film 12 Gate electrode 13 Storage electrode 14 Ferroelectric thin film 15 Connection electrode 16 Insulator

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication location H01L 29/788 29/792 H01L 29/78 371 (72) Inventor Yuuji Tatemura Nihonbashi, Chuo-ku, Tokyo 1-13-1 TDC Corporation (72) Inventor Katsuto Nagano 1-13-1 Nihonbashi Chuo-ku, Tokyo Tokyo DC Corporation

Claims (2)

[Claims] 1. An active part and a memory part formed adjacent to each other on an insulating substrate, wherein the active part is formed on a semiconductor layer formed on the insulating substrate and on a surface of the semiconductor layer with a space therebetween. A source region and a drain region, a source electrode and a drain electrode formed on the source region and the drain region, respectively, and a gate formed on the surface of a separated portion between the source region and the drain region on the semiconductor layer. An insulating film and a gate electrode formed on the gate insulating film, and the memory unit includes a memory electrode formed on the insulating substrate, a ferroelectric thin film formed on the memory electrode, and the ferroelectric. A nonvolatile memory cell comprising a connection electrode formed on a thin film, wherein a gate electrode of the active portion and a connection electrode of the storage portion are electrically connected. 2. The non-volatile memory cell according to claim 1, wherein the semiconductor layer is a polycrystalline semiconductor layer.