JPH05226599A - One-time prom - Google Patents

Abstract

PURPOSE:To provide a fuse ROM-type OTP wherein an address decoding signal can be tested in an unwritten state and the data write time is short. CONSTITUTION:When an address decoding signal is tested, a latch circuit 3 is set to a continuity state so that address deconding signals from an address deconding part 2 are output to a data bus 4 through word lines and latch circuits 3. In a write operation, pieces of write data form the data bus are latched by the latch circuits 3. Pieces of data which are output by the individual latch circuits are applied to gates for individual transistors 11 through the word lines. The ON/OFF operation of the individual transistors is decided by the value of the pieces of write data which are output by the write circuits. When a voltage at a high level is applied to a bit line BL1, a fuse connected to the ON/OFF transistors out of fuse parts 12 connected to the bit line BL1 is destroyed correspondingly or it is not destroyed and set to a noncontinuity state. Thereby, a piece of '1' or '0' data can be written.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a one-time PROM.

[0002]

Fuse ROM type one-time PR
In OM (OTP), data can be written only once by applying an electric signal from the outside. Such a one-time P
One-chip microcomputers (microcomputers) with a built-in ROM are widely used as OTP microcomputers.
OTP version microcomputers are now indispensable for developing one-chip microcomputers, and are particularly useful when debugging a program. In addition, it has the advantages that it can be manufactured as a mass-produced product in a short delivery time, it can respond quickly to changes in program specifications, and it is optimal for high-mix low-volume production.

The fuse ROM type one-time PROM is widely used by being incorporated in various devices other than the microcomputer, and is also used as a single unit.

[0004]

The fuse ROM described above.
In the one-time PROM of the type, once written, the stored contents cannot be erased thereafter. Therefore, when the IC is shipped as an unwritten state, that is, when writing is performed by the user, the memory write test cannot be performed at the time of shipment, and therefore the address decode signal test cannot be performed. this is,
Whether or not the address decode signal is normal is determined by reading the data from a certain address and checking whether the write data and the read data match, so if the data is not written to the memory, the address Because the decoded signal cannot be tested. Thus, when shipped as an unwritten IC, not only the write test cannot be performed, but
Since the address decode signal cannot be tested,
The product is shipped in anticipation of a certain defect rate.

Further, by writing data, a writing IC
In the case of shipping as, the data is sequentially written to each address, so that it takes a long time to write the data, which is one of the reasons for the high cost. This is expected to become an even greater problem in situations where the storage capacity of one-time PROMs is increasing.

An object of the present invention is to solve such a problem and to provide a one-time PROM capable of testing an address decode signal in a non-written state and capable of writing data in a short time.

[0007]

To achieve the above object, a one-time PROM of the present invention including a fuse type memory section and an address decode section for outputting an address decode signal to each word line of the memory section is provided. , A read circuit which is provided between each word line and the data bus and which conducts when the first signal is applied and outputs the address decode signal to the data bus; And a latch circuit which is respectively provided between them and which fetches data from the data bus when the second signal is applied, latches the data, and outputs the latched data to the word line.

[0008]

When testing the address decode signal output from the address decode unit, the first signal is supplied to the read circuit. As a result, the read circuit outputs the address decode signal to the data bus, and it is possible to check whether or not the address decode signal is normally output.
When writing data to the memory portion, write data is input through the data bus and a second signal is supplied to the latch circuit. As a result, each latch circuit latches the data input through the data bus and outputs the latched data to the word line of the memory section. Depending on the value of the data output from each latch circuit, the on / off state of the transistor connected to the fuse forming each storage element of the memory section is turned on / off.
Off is decided. When a predetermined voltage is applied to the bit line to be written in this state, this voltage is applied to both ends of the fuse connected to the transistor which is turned on, and the fuse is destroyed and becomes conductive. On the other hand, this voltage is not applied to the fuse connected to the transistor that is off, and the fuse is kept non-conductive. This gives "1"
Alternatively, data of "0" is written in all the words at once.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows a one-time PRO according to the present invention.
The circuit diagram of M is shown. This PROM comprises a memory unit 1 capable of storing 512 bytes of data, an address decoding unit 2 for outputting an address decode signal to each word line W1 to W512 of the memory unit 1, word lines W1 to W512 and a data bus 4. And 512 latch circuits 3 connected to each other. The address decoding unit 2 is in an output enable state when the output control signal W supplied from the outside is at high level, and sets the output to high impedance when it is at low level.

As shown in FIG. 2, the latch circuit 3 is composed of inverters 31 and 32 and a switch 33. The output terminal of the inverter 31 and the input terminal of the inverter 32 are both connected to the terminal Q of the latch circuit 3, and the input terminal of the inverter 31 and the output terminal of the inverter 32 are both connected to one terminal of the switch 33. The other terminal of the switch 33 is connected to the terminal D of the latch circuit 3. The inverter 31 is supplied with the clock CK2 and its inverted clock, and the inverter 32 is supplied with the clock CK3 and its inverted clock. The switch 33 has a clock CK1 as an on / off control clock.
And its inverted clock are supplied.

The memory unit 1 includes 512 × 8 transistors 11 and a fuse unit 12 connected to each transistor.
It has and. The gates of the transistors 11 are connected to the word lines W1 to W512 every byte, that is, every eight transistors. BL1 to BL8 are bit lines.

One-time PROM configured in this way
The test procedure of the address decode signal in the above will be described. FIG. 3 shows one latch circuit 3 and one output inverter 21 of the address decoding unit 2 connected to the latch circuit via a word line. When testing the address decode signal, the address decode unit 2 is supplied with a high level control signal W, and the inverter 31 is supplied with a low level signal as the clock CK2. Further, a high level signal is supplied to the inverter 32 as the clock CK3. And the clock CK is applied to the switch 33.
A high level signal is given as 1. In this state, the address decode signal output from the inverter 21 is
As shown by the dotted line, the inverter 32 and the switch 33
Is output to the data bus 4 via. Therefore, the address decode signal can be taken out from the data bus 4,
It is possible to check whether the address decode signal is normally output.

Since the word lines W1 to W512 may be broken in the memory section 1, the terminal Q of the latch circuit 3 is detected as shown in FIG. 1 in order to detect such a break. It is preferable to connect to the word line after passing through the memory section 1 so that the address decode signal is input to the latch circuit 3 after passing through the memory section 1.

Next, writing of data will be described.
Here, among the memory elements that configure the memory unit 1 of FIG. 1, attention is paid to the memory element including the transistor 11 and the fuse unit 12 that are connected to the word line W1 and the bit line BL1. To store data "1" in this storage element,
Conventionally, as shown in FIG. 5, the gate of the transistor 11 is
That is, the high-level voltage VPP is applied to the word line W1 from the address decoding unit 2 to turn on the transistor 11, and in that state, the high-level voltage VPP is applied to the bit line BL1.
Apply PP. As a result, the transistor 11 is turned on, the high-level voltage VPP is applied to both ends of the fuse 12, the fuse 12 is destroyed and becomes conductive, and "1" is stored as data. On the other hand, transistor 1
When the bit line BL1 is set to the ground level with 1 turned on, no voltage is applied to the fuse section 12, and the fuse section 12 remains non-conductive as shown in FIG. "0" is stored as.

However, in the one-time PROM of this embodiment, the data can be collectively written as follows. First, a low-level control signal W is supplied to the address decoding unit 2 to make the output of the address decoding unit high impedance. The clock CK shown in FIG. 6 is given to the inverter 31 as the clock CK2. Inverter 3
An inverted signal of the clock CK is given to 2 as the clock CK3. Then, the switch 33 is supplied with the clock CK as the clock CK1.

As a result, as shown in FIG. 7, the data from the data bus is input to the inverter 31 via the switch 33 while the clock CK is at the high level, and the clock C
When K goes to low level, the data is
Latched in a circuit consisting of 32. The latched data is applied to the gate of each transistor 11 via the word line. By causing all the latch circuits 3 to sequentially latch the write data in this manner, the write data is output to all the word lines W1 to W512. In this state, for example, if the voltage VPP is applied to the bit line BL1 and the ground level voltage is applied to the other bit lines BL2 to BL8, all the fuse parts 12 connected to the bit line BL1 are based on the write data. Conduction or non-conduction is determined, and data is written. That is, as shown in FIG. 8, when the high level voltage VPP corresponding to, for example, "1" of data is applied from the latch circuit 3 through the word line, the transistor 11 is in the ON state, Bit line BL1
When the voltage VPP is applied to the fuse part 12,
Is applied to both ends of the fuse portion 12, the fuse portion 12 is broken, the fuse portion 12 becomes conductive, and "1" is stored. On the other hand, as shown in FIG. 9, when the voltage of the ground level corresponding to, for example, "0" of data is applied from the latch circuit 3 through the word line, the transistor 11 is in the off state, Even if the voltage VPP is applied to the line BL1,
The voltage is not applied to both ends of the fuse portion 12, and the fuse portion 12 is not destroyed, so that it remains in a non-conducting state and "0" is stored. By causing each latch circuit 3 to latch the data and sequentially changing the bit line to which the voltage VPP is applied, the data can be written in all the storage elements.

Thus, the one-time PROM of this embodiment
Then, by causing the latch circuit 3 to hold the write data and applying the voltage VPP to the bit line, it is possible to collectively write the data to the storage element corresponding to the bit line, that is, the predetermined bit of all the words. it can.

When the conventional writing is performed in the one-time PROM of FIG. 1, as shown in FIG. 10, the writing is performed in units of 8 bits (memory elements indicated by black marks). 512 x T to complete writing
Only w is needed. It should be noted that Tw is the time required for one writing and is usually about 10 ms.

On the other hand, when batch writing is performed, since writing can be performed in 512-bit units as shown in FIG. 11, the time required for writing to all storage elements is 8 × Tw.
Therefore, the writing time is reduced to 1/64 of the conventional case.

[0020]

As described above, the one-time PROM of the present invention is provided between each word line and the data bus, and conducts when the first signal is applied to the address decode signal. A read circuit that outputs data to the data bus, and each word line is provided between the word line and the data bus. When a second signal is applied, the data is fetched from the data bus and latched. It is possible to test whether or not the address decode signal is normally output, even in the unwritten state, since it is provided with the latch circuit for outputting to. Furthermore, since the bit data of all words can be written simultaneously at the same time, the writing time can be greatly shortened.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a one-time PROM of the present invention.

FIG. 2 is a circuit diagram of a latch circuit of the PROM of FIG.

FIG. 3 is an explanatory diagram of a test procedure of an address decode signal in the PROM of FIG.

FIG. 4 is an explanatory diagram of a word-wise data writing procedure in the PROM.

FIG. 5 is an explanatory diagram of a word-wise data writing procedure in the PROM.

FIG. 6 is a waveform diagram of clocks supplied to the inverters and switches of the latch circuit of FIG.

7 is an explanatory diagram of a data batch writing procedure in the PROM of FIG.

8 is an explanatory diagram of a data batch writing procedure in the PROM of FIG.

9 is an explanatory diagram of a data batch writing procedure in the PROM of FIG.

FIG. 10 is an explanatory diagram of conventional data writing in 1-byte units.

FIG. 11 is an explanatory diagram of data batch writing according to the present invention.

[Explanation of symbols]

 1 Memory Part 2 Address Decode Part 3 Latch Circuit 11 Transistor 12 Fuse Part 21, 31, 32 Inverter 33 Switch

Claims (1)

[Claims] 1. A one-time PROM including a fuse type memory section and an address decode section for outputting an address decode signal to each word line of the memory section, wherein the one-time PROM is provided between each word line and a data bus. A read circuit which is provided to conduct when a first signal is applied and output the address decode signal to the data bus; and a read circuit provided between each word line and the data bus. A one-time PROM, comprising: a latch circuit that takes in data from the data bus and latches it when a signal of 2 is given, and outputs the latched data to a word line.