JPH05227526A - Picture processor - Google Patents

Abstract

PURPOSE:To minimize the data amounts of encoded data, and the compression distortion of a picture by balancing both of them. CONSTITUTION:Differential data between a present block obtained from present picture data and the preceeding block obtained from the previous picture data are calculated in a subtracting circuit 1, and transformed into DCT data by a DCT processing in a DCT circuit 2. Then, the DCT data are quantized by a prescribed quantization scale in a quantizing circuit 3. At that time, the block criticality of the picture is calculated based on the frequency component distribution of the DCT data in a block criticality generating part 12, and the quantization scale for quantizing the DCT data is decided based on the block criticality in a quantization parameter control circuit 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus suitable for use in, for example, a video conference system or a video telephone system for compressing and transmitting an image for transmission, a material transmission system between studios and the like.

[0002]

2. Description of the Related Art For example, in a video conference system or a video telephone system, an MC-D that compresses and encodes an image
As an image processing device using the CT method, a device as shown in FIG. 9 is conventionally known.

The subtraction circuit 1 extracts the block data (block data of the current frame) clipped from the current frame data to be compression-encoded and the block data (previous frame data extracted from the previous frame data subjected to motion compensation). (The block data of the frame) and outputs the difference data to the DCT circuit 2. The DCT circuit 2 performs DCT (discrete cosine transform) processing on the difference data output from the subtraction circuit 1 and outputs the DCT data to the quantization circuit 101.

The quantizing circuit 101 quantizes the DCT data output from the DCT circuit 2 with a quantizing scale corresponding to a quantizing control parameter f in stripe units input to its control terminal (not shown). .. The variable length coding circuit 4 performs variable length coding on the quantized data output from the quantization circuit 101. The buffer memory circuit 11 temporarily stores the encoded data output from the variable length encoding circuit 4 and outputs it at a predetermined transmission rate. Further, the buffer memory circuit 11 generates a quantization control parameter f corresponding to the storage amount (accumulation amount) of the encoded data stored therein and supplies it to the quantization circuit 101 and the inverse quantization circuit 102.

The inverse quantization circuit 102 is a quantization circuit 101.
The quantized data output from the quantized circuit 101 is the quantized scale corresponding to the quantized control parameter f for each stripe input to the control terminal (not shown) of the quantized data.
Inverse quantization is performed with the same quantization scale as the quantization scale in and the DCT data is supplied to the inverse DCT circuit 6. The inverse DCT circuit 6 outputs D output from the inverse quantization circuit 102.
Inverse DCT processing is performed on the CT data, and the difference data is output to the addition circuit 7.

The adder circuit 7 adds the difference data output from the inverse DCT circuit 6 and the data output from the motion compensation circuit 10 to generate block data of the current frame. The frame memory circuit 8 temporarily stores the block data of the current frame output from the adding circuit 7.

The motion detection circuit 9 is a frame memory circuit 8
The block data of the previous frame output by the above and the block data of the current frame input to the subtraction circuit 1 are compared to detect a motion vector. The motion compensation circuit 10 performs motion compensation on the block data of the previous frame output from the frame memory circuit 8 in accordance with the motion vector detected by the motion detection circuit 9, and outputs it to the subtraction circuit 1 and the addition circuit 7.

In the image processing apparatus configured as described above, every time the block data of the current frame to be compressed is supplied to the subtraction circuit 1, the block data of the current frame and the motion compensation circuit 10 move there. Difference data from the compensated block data of the previous frame is calculated, and DCT processing is performed in the DCT circuit 2. D
The DCT data output from the CT circuit 2 is input to the quantization circuit 101, quantized therein, and variable length encoded in the variable length encoding circuit 4. Then, the variable-length coded data is temporarily stored in the buffer memory circuit 11 and output at a predetermined transmission rate.

At the same time, the block data of the current frame is
It is also input to the motion detection circuit 9, where it is compared with the block data of the previous frame stored in the frame memory circuit 8 to detect the motion vector. Then, in the motion compensation circuit 10, motion compensation corresponding to the motion vector detected by the motion detection circuit 9 is applied to the data of the previous frame stored in the frame memory circuit 8, and the prediction data of the block data of the current frame is obtained. It is output to the subtraction circuit 1 and the addition circuit 7.

On the other hand, the difference data quantized by the quantization circuit 101, that is, the quantized data is input to the inverse quantization circuit 102, inversely quantized there, and further inversely DCT processed by the inverse DCT circuit 6. .. That is, as a result, the same data (difference data) as the difference data output from the subtraction circuit 1 is reproduced.

The difference data reproduced by the inverse DCT circuit 6 is
It is input to the adder circuit 7 and is added thereto with the block data of the previous frame output from the motion compensation circuit 10. That is, as a result, the same data as the block data of the current frame input to the subtraction circuit 1 (correctly, block data of the current frame including quantization distortion) is reproduced.

The block data of the current frame reproduced by the adder circuit 7 is supplied to and stored in the frame memory circuit 8.

The above operation is repeated, and the image is compression-coded in block units.

[0014]

By the way, in this image processing apparatus, the quantization scale in the quantization circuit 101 and the inverse quantization circuit 102 is controlled based on only the amount of data stored in the buffer memory circuit 11, so to speak. Since the control is performed by the buffer storage amount method, the data amount (information amount) of the variable-length coded data varies for each block data, and there are cases where proper quantization cannot be performed.

Therefore, when the coded data is decoded, the distortion is not always uniformly distributed over the entire decoded image, but rather distortion having a high correlation (block distortion) is often generated locally. There was a problem of deterioration of the image quality and deterioration of the visual effect.

The present invention has been made in view of such a situation, and enables DCT data calculated from image data to be quantized with an appropriate quantization scale, thereby finally. The deterioration of the decoded image is reduced by balancing the information amount and compression distortion of the obtained variable-length coded data.

[0017]

According to another aspect of the present invention, there is provided an image processing apparatus for compressing image data to generate coded data, the current block obtained from the current image data, and the previous block. DC obtained by DCT transforming the difference data from the previous block obtained from the image data
It is characterized in that the quantization scale for quantizing the DCT data is controlled based on the frequency component distribution of the T data.

According to a second aspect of the present invention, in an image processing apparatus for compressing image data to generate code data, a current block obtained from current image data and a previous block obtained from previous image data. It is characterized by controlling a quantization scale for quantizing DCT data obtained by DCT transforming the difference data based on the value of the difference data with respect to the block.

An image processing apparatus according to a third aspect of the present invention is a subtraction circuit as difference calculation means for calculating difference data between a current block obtained from current image data and a previous block obtained from previous image data. 1, a DCT circuit 2 as a DCT means for performing DCT processing on the difference data calculated by the subtraction circuit 1 and converting the difference data into DCT data, and DCT data output from the DCT circuit 2,
A quantizing circuit 3 as a quantizing means for quantizing with a predetermined quantizing scale and outputting the quantized data, and a DCT circuit 2
Based on the frequency component distribution of the output DCT data, the block criticality generating unit 12 as a block criticality calculating unit for calculating the block criticality of the image, and the block criticality calculated by the block criticality generating unit 12. And a quantization parameter control circuit 15 as a control means for controlling the quantization scale of the quantization circuit 3.

An image processing apparatus according to a fourth aspect of the present invention is a subtraction circuit as difference calculation means for calculating difference data between a current block obtained from current image data and a previous block obtained from previous image data. 1, a DCT circuit 2 as a DCT means for performing DCT processing on the difference data calculated by the subtraction circuit 1 and converting the difference data into DCT data, and DCT data output from the DCT circuit 2,
A block that calculates a block criticality of an image based on the value of the difference data calculated by the subtraction circuit 1 and a quantization circuit 3 as a quantization means that quantizes with a predetermined quantization scale and outputs quantized data. Block criticality generator 2 as criticality calculation means
1 and a quantization parameter control circuit 15 as a control means for controlling the quantization scale of the quantization circuit 3 based on the block criticality calculated by the block criticality generator 21.

The image processing apparatus according to a fifth aspect further includes a buffer memory circuit 11 as a storage unit for temporarily storing the quantized data output from the quantization circuit 3, and the quantization parameter control circuit 15 includes a block. The quantization scale of the quantization circuit 3 is controlled based on the storage amount of the buffer memory circuit 11 together with the block criticality calculated by the criticality generation unit 12 or 21.

In the image processing apparatus according to the sixth aspect, the block criticality generator 12 or 21 and the quantization parameter control circuit 15 are at least one ROM.
It is characterized by being configured.

[0023]

In the image processing apparatus having the above configuration, the difference data between the current block obtained from the current image data and the previous block obtained from the previous image data is calculated, DCT-processed and converted into DCT data. To do. And
The DCT data is quantized with a predetermined quantization scale. At this time, the block criticality of the image is calculated based on the frequency component distribution of the DCT data or the value of the difference data, and the DC is calculated based on this block criticality.
Control the quantizer scale for quantizing T data. Therefore, since the DCT data can be quantized with an appropriate quantization scale, the deterioration of the decoded image can be reduced.

Further, in this image processing apparatus, the buffer memory circuit 11 temporarily stores the quantized data output from the quantizing circuit 3, and the quantizing parameter control circuit 15 causes the block criticality generating unit 12 or 2 to operate.
The quantization scale of the quantization circuit 3 is controlled based on the storage capacity of the buffer memory circuit 11 together with the block criticality calculated by 1. Therefore, the DCT data can be quantized with an appropriate quantization scale that balances the data amount of the compression-encoded data and the compression distortion, so that the deterioration of the decoded image can be reduced.

Further, in this image processing apparatus, the block criticality generator 12 or 21 and the quantization parameter control circuit 15 include at least one RO.
Since it is composed of M, the device can be made compact.

[0026]

First, the basic principle of the present invention will be described.
Recommendation 7 currently being standardized in CCIR
23 (CCIR 4: 2: 2 component TV signal 3
In the coding method based on 0 to 45 Mbit / s codec), when compressing block data forming a frame or the like by MC-DCT (motion compensation-discrete cosine transform), the frame to be compressed is as shown in FIG. Is divided into stripe units (8 line units) into line blocks, and the line blocks are divided into 8 pixel units into 8 pixel × 8 line block data, which are discrete cosine transformed in block units. Each DCT coefficient that constitutes the obtained DCT data is quantized in macroblock units consisting of two luminance signal blocks and two color difference signal blocks.

In this case, the DCT forming the DCT data
If the sum of the absolute values of the coefficients is large, the difficulty of compression in units of macroblocks corresponding to the DCT data increases, the amount of information generated increases, and the distortion due to the quantization increases, and conversely, the DCT coefficients forming the DCT data. If the sum of absolute values of is small, the degree of compression difficulty in units of macroblocks corresponding to DCT data decreases, the amount of information generated decreases, and the distortion due to quantization decreases.

Furthermore, if the precision of the quantization scale for quantizing the DCT coefficients that compose the DCT data is increased, the amount of information generated increases, but the distortion due to quantization decreases.
Further, if the precision of the quantization scale for quantizing the DCT coefficient is lowered, the amount of information generated decreases, but the distortion due to quantization increases.

Therefore, in the present invention, a rough value of the quantization scale is determined in stripe units based on the information generation amount, and the information generation amount in each stripe unit is adjusted by this, and the frequency component of the DCT data is adjusted. Based on the distribution (the size of the DCT coefficient of each order), the block criticality is calculated for each macroblock, and the quantization scale is adjusted based on the block criticality to improve the image quality. It is the basic principle.

An image processing apparatus using this basic principle will be described below in detail with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of an embodiment of the image processing apparatus of the present invention. In the figure, parts corresponding to those in FIG. 9 are designated by the same reference numerals. The quantization circuit 3 quantizes the input data with the quantization scale supplied from the quantization parameter control circuit 15. The inverse quantization circuit 5 inversely quantizes the input data with the quantization scale supplied from the quantization parameter control circuit 15.

The block criticality generator 12
It is composed of an absolute value sum circuit 13 and a BC (block criticality) control circuit 14, and calculates a block criticality m from the DCT data output from the DCT circuit 2.

That is, the block criticality generator 1
The absolute value sum circuit 13 of 2 converts the DCT data output from the DCT circuit 2 into four areas of a DC component area, a low frequency component area, an intermediate frequency component area, and a high frequency component area, as shown in FIG. The absolute value sum (absolute value sum data) of the DCT coefficients in each area when classified into areas is calculated.

The DCT coefficient in the DC component area is the DC component itself of the DCT coefficient, that is, the position (0,
0) means the DCT coefficient (the hatched portion in the figure).

B of the block criticality generator 12
The C control circuit 14 calculates the sum of the absolute values of the DCT coefficients in the DC component area (the absolute value of the DC component of the DCT coefficient) calculated by the absolute value sum circuit 13, the sum of the absolute values of the DCT coefficients in the low frequency component area, and the intermediate frequency. Sum of absolute values of DCT coefficients in the component area,
Alternatively, the block criticality m is determined based on the sum of absolute values of DCT coefficients in the high frequency component area.

The BC control circuit 14 is composed of a ROM (not shown), and the ROM stores a table in which the sum of absolute values of each area and the block criticality are associated with each other in advance. There is. That is, in the BC control circuit 14, the absolute value sum of each area supplied from the absolute value sum circuit 13 is used as the address (read address) of the built-in ROM, and the data stored therein, that is, the block criticality m is read. It is like this.

The quantization parameter control circuit 15 supplies the quantization control parameter f supplied from the buffer memory circuit 11, the block criticality m read from the BC control circuit 14 of the block criticality generator 12,
Y / C information indicating whether the DCT coefficient quantized by the quantization circuit 3 corresponds to the luminance signal Y or the color difference signal C, and the position (coordinate) of the DCT coefficient. The quantization scale S is determined from (k, l).

The quantization parameter control circuit 15 is
Like the BC control circuit 14, it is composed of a ROM (not shown), and the ROM has the quantization control parameter f, the block criticality m, the Y / C information, and the position (coordinates) of the DCT coefficient ( A table in which the k, l) and the quantization scale S are associated with each other is stored in advance. That is, in the quantization parameter control circuit 15, the quantization control parameter f, the block criticality m, Y /
C information and DCT coefficient position (coordinates) (k, l)
As the address (reading address) of the built-in ROM, the data stored therein, that is, the quantization scale S
Is read.

Therefore, in the ROM of the BC control circuit 14,
DCT coefficient absolute value sum of DC component area (DCT coefficient DC component absolute value), low frequency component area DCT coefficient absolute value sum, intermediate frequency component area DCT coefficient absolute value sum, and high frequency component area If the sum of the absolute values of the DCT coefficients of the low frequency component area is larger than the sum of the absolute values of the DCT coefficients of
The change of block data corresponding to CT data is small,
It is determined to be smooth, and the quantization scale S supplied to the quantization circuit 3 and the inverse quantization circuit 5 is finely divided, and the sum of absolute values of the DCT coefficients in the intermediate frequency component area or the DCT coefficient in the high frequency component area is determined. If the sum of the absolute values of is larger than that of the other areas, it is determined that the change in the block data is large, and the quantization scale S supplied to the quantization circuit 3 and the inverse quantization circuit 5 is roughened. To
Address data for reading the quantization scale S is stored from the ROM of the quantization parameter control circuit 15.

In the image processing apparatus configured as described above, for example, 720 pixels × 480 lines (7 pixels in the horizontal direction)
An image (image signal) composed of 20 pixels and 480 lines in the vertical direction is, for example, 8 pixels x 8 lines (8 x
When the block data divided into blocks such as 8) is input to the subtraction circuit 1 in block units, the block data of the current frame (current block data) and
The block data (previous block data) of the previous frame that has been subjected to motion compensation from the motion compensation circuit 10 is compared in pixel units, and 8 × 8 difference data is calculated. This difference data is subjected to DCT processing in the DCT circuit 2, and DCT processing is performed.
The data is output.

The DCT data output from the DCT circuit 2 is input to the block criticality generator 12,
In the absolute value sum circuit 13, four areas of the DC component area, the low frequency component area, the intermediate frequency component area, or the high frequency component area as described above (FIG. 3).
The absolute value sum (absolute value sum data) of the DCT coefficients at is calculated and supplied to the BC control circuit 14.

In the BC control circuit 14, the sum of absolute values of each area supplied from the sum of absolute values circuit 13 is built in R
As an OM address (read address), the block criticality m stored at that address is read.

The block criticality m read from the BC control circuit 14 is the quantization parameter control circuit 1
Input to 5. Then, the quantization parameter control circuit 1
5, the block criticality generator 12 (B
Block criticality m from the C control circuit 15),
Quantization control parameter f from buffer memory circuit 11, Y / C information, and position (coordinates) of DCT coefficient
When (k, l) is an address (readout address) of the built-in ROM, the quantization scale S stored at the address, that is, when the change in the block data input to the subtraction circuit 1 is small and smooth, , The fine quantizer scale S, and the coarse quantizer scale S is read when the change of the block data is large.

The quantization scale S read out from the quantization parameter control circuit 15 is supplied to the quantization circuit 3 and the inverse quantization circuit 5.

Further, the DCT output from the DCT circuit 2
The data is input to the quantization circuit 3 as well as the block criticality generator 12. In the quantization circuit 3, the DCT data from the DCT circuit 2 is quantized by the quantization scale supplied from the quantization parameter control circuit 15 and output to the variable length coding circuit 4 and the inverse quantization circuit 5.

In the variable length coding circuit 4, the quantized data output from the quantization circuit 3 is variable length coded together with the motion vector detected by the motion detection circuit 9 and supplied to the buffer memory circuit 11. In the buffer memory circuit 11, the variable-length coded data supplied from the variable-length coding circuit 4 is temporarily stored and is output to a next-stage circuit (not shown) at a preset predetermined transmission rate, and The quantization control parameter f corresponding to the data amount (accumulation amount) stored therein is generated and output to the quantization parameter control circuit 15.

On the other hand, in the dequantization circuit 5, the quantized data output from the quantization circuit 3 is dequantized by the quantization scale supplied from the quantization parameter control circuit 15 and output to the inverse DCT circuit 6. To be done. In the inverse DCT circuit 6, the data output from the inverse quantization circuit 5 (8 × 8
DCT data) is subjected to inverse DCT processing and output to the adder circuit 7.

Here, in the motion detection circuit 9, the same data as the current block data input to the subtraction circuit 1 and the previous block data stored in the frame memory circuit 8 based on the position of this data are cut out. The block data (offset block data) for each motion vector is individually compared, and the motion vector of the offset block data closest to the current block data is selected (detected) from the offset block data based on the comparison result. ) Will be done.

Then, in the motion compensation circuit 10, motion compensation corresponding to the motion vector selected (detected) by the motion detection circuit 9 is applied to the previous block data read from the frame memory circuit 8. The block data subjected to the motion compensation by the motion compensation circuit 10 is supplied to the subtraction circuit 1 and the addition circuit 7.

In the adder circuit 7, the block data supplied from the motion compensation circuit 10 and the difference data output from the inverse DCT circuit 6 are added, whereby the block data of the current frame input to the subtraction circuit 1 is added. The same data as that (more accurately, block data of the current frame including quantization distortion) is reproduced.

The block data of the current frame reproduced by the adder circuit 7 is supplied to and stored in the frame memory circuit 8.

As described above, in this image processing device, the rough value of the quantization scale is determined in stripe units based on the storage amount (accumulation amount) of data in the buffer memory circuit 11, and thus, in each stripe unit. The amount of information generated by the DCT circuit 2
Since the block criticality is calculated for each macroblock and the quantization scale is adjusted based on the frequency component distribution (power distribution) of the DCT coefficients that form the CT data, the quality of the decoded image should be improved. You can Furthermore, it is possible to balance the data amount of the variable-length coded data and the compression distortion of the image to minimize the data amount of the variable-length coded data or the compression distortion of the image.

Next, FIG. 4 is a block diagram showing the configuration of the second embodiment of the image processing apparatus of the present invention. In the figure, parts corresponding to those in FIG. 2 are designated by the same reference numerals. The block criticality generation unit 21 includes an adjacent difference extraction circuit 22, a counting circuit 23, and a BC control circuit 24, and the image (image data) input to the subtraction circuit 1 from the difference data output from the subtraction circuit 1. Calculate the block criticality of.

That is, the adjacent difference extraction circuit 22 calculates the adjacent difference between each pixel forming the difference data output from the subtraction circuit 1 (FIG. 5), and outputs 112 adjacent difference data to the counting circuit 23. To do. Counting circuit 23, adjacent 112 contiguous differential data output from the difference extracting circuit 22 to a predetermined threshold S ₁ Therefore classification, the threshold value S ₁ is greater than the number of adjacent differential data B or the threshold S ₁ is smaller than the adjacent difference, The number A of data is counted respectively. BC
The control circuit 24 calculates the block criticality based on the counting result of the counting control circuit 23, and supplies it to the quantization parameter control circuit 15.

[0055] Incidentally, BC control circuit 24 is constituted by the ROM (not shown), in its ROM, a counted by the counting circuit 23, the number of threshold S ₁ is greater than the adjacent difference data B, and the threshold value S ₁ A table in which the number A of smaller adjacent difference data is associated with the block criticality is stored in advance. That is, the BC control circuit 2
4, the numbers A and B output from the counting circuit 23
As the address (reading address) of the built-in ROM, the data stored therein, that is, the block criticality m, is read out.

In the image processing apparatus thus constructed,
When the difference data calculated by the subtraction circuit 1 is input to the block criticality generator 21, the adjacent difference extraction circuit 2
In 112, 112 pieces of adjacent difference data are calculated (FIG. 5) and output to the counting circuit 23.

[0057] In the counter circuit 23, 112 pieces of adjacent difference data output from the adjacent difference extracting circuit 22 is a predetermined threshold value S ₁ Therefore classification, the threshold value S ₁ is greater than the number of adjacent differential data B or the threshold S _1, The number A of small adjacent difference data is counted respectively. Then, the BC control circuit 24, the counting result of the counting control circuit 23, i.e., the threshold S ₁ is greater than the number of adjacent differential data B, and the threshold value S ₁ is smaller than the number A of the adjacent difference data, a built-in ROM address (read address)
As a result, the data stored therein, that is, the block criticality m is read out and output to the quantization parameter control circuit 15.

In the quantization parameter control circuit 15, as in the case of FIG. 2, the block criticality m from the block criticality generator 21 (BC control circuit 24) and the quantization control parameter f from the buffer memory circuit 11 are used. , Y / C information and the position (coordinates) (k, l) of the DCT coefficient as an address (reading address) of the built-in ROM, the quantization scale S stored at that address is read out, and the quantization circuit 3 and the inverse quantization circuit 5.

That is, as shown in the flow chart of FIG. 6, first, in step ST1, the adjacent difference data from the adjacent difference extraction circuit 22 is taken into the counting circuit 23, and the process proceeds to step ST2 where the adjacent difference data is set to the threshold value S.
It is classified into adjacent difference data that is larger than _{1 and} adjacent difference data that is smaller than ₁ and proceeds to steps ST3 and ST4 in sequence.

[0060] In step ST3 and ST4, classified threshold S ₁ is greater than the number of adjacent difference data B or the number A threshold S ₁ is smaller than the adjacent difference data, are counted respectively (count) in step ST2, the step ST5 Proceed to.

[0061] In step ST5, the number B of the threshold S ₁ is greater than the adjacent difference data, and the number A threshold S ₁ is smaller than the adjacent difference data are compared. Step ST5
In A, the number A of adjacent difference data smaller than the threshold S ₁
Is determined to be greater than the number B of adjacent difference data larger than the threshold S ₁ , that is, when the change in the block data is small and smooth, the process proceeds to step ST6 and the quantization parameter control circuit 15 causes the quantization circuit 3 Then, the fine quantization scale S is output to the inverse quantization circuit 5, and the process ends.

[0062] In step ST5, if the threshold S ₁ is smaller than the number A of the adjacent difference data is determined to not more than the number B of the threshold S ₁ is greater than the adjacent difference data,
That is, when the change in the block data is large, step ST
7, the quantization parameter control circuit 15 outputs the coarse quantization scale S to the quantization circuit 3 and the inverse quantization circuit 5, and the process is terminated.

As described above, in this image processing apparatus, the rough value of the quantization scale is determined in stripe units based on the storage amount (accumulation amount) of data in the buffer memory circuit 11, and thus, in each stripe unit. In addition to adjusting the amount of information generation, the block criticality is calculated for each macroblock based on the adjacent difference data calculated from the difference data output from the subtraction circuit 1, and the quantization scale is adjusted. The quality of the decoded image can be improved. Furthermore, it is possible to balance the data amount of the variable-length coded data and the compression distortion of the image to minimize the data amount of the variable-length coded data or the compression distortion of the image.

In the embodiment of FIG. 4, the counting circuit 23 classifies adjacent difference data by one threshold value S _1. However, as shown in the flow chart of FIG. 7 or FIG. The adjacent difference data may be classified by the threshold values S ₁ and S ₂ , or more threshold values S _{1 to} S _n .

Note that S ₁ <S ₂ <... <S _n .

That is, when the two threshold values S ₁ and S ₂ are used, first, in step ST10 of FIG. 7, the adjacent difference data from the adjacent difference extraction circuit 22 is fetched into the counting circuit 23, and the process proceeds to step ST11. The data is,
It is classified into adjacent difference data larger than the threshold value S _2, adjacent difference data larger than the threshold value S ₁ and smaller than the threshold value S ₂ , and adjacent difference data smaller than the threshold value S ₁ , and the process proceeds to steps ST 12 and ST 13.

In steps ST12 and ST13, the number C of adjacent difference data that is larger than the threshold S ₂ classified in step ST11, the number B of adjacent difference data that is larger than the threshold S ₁ and smaller than the threshold S ₂ , or the threshold S ₁ The smaller number A of adjacent difference data is counted, and the process proceeds to step ST14.

At step ST14, the numbers A, B,
Or C is compared respectively. In step ST14, the number A of adjacent difference data smaller than the threshold value S ₁ is
If it is determined that the number of adjacent difference data B is larger than the threshold value S ₁ and smaller than the threshold value S ₂ or the number of adjacent difference data C is larger than the threshold value S ₂ , that is, the change of the block data is small and smooth. If step ST
In step 15, the quantization parameter control circuit 15 outputs a fine quantization scale S to the quantization circuit 3 and the dequantization circuit 5, and the process ends.

[0069] In step ST14, greater than the threshold S _1, and the threshold value S ₂ is smaller than the number of adjacent difference data B, the threshold value S ₁ is smaller than the number of adjacent difference data A or threshold S ₂ greater than the number of adjacent difference data, If it is determined that the number is larger than C, that is, if the change in the block data is normal, the process proceeds to step ST16, where the quantization parameter control circuit 15 causes the quantization circuit 3 and the inverse quantization circuit 5 to quantize the normal value. The scale S is output, and the process ends.

In step ST14, the threshold value S
The number C of adjacent difference data larger than _{2 is} larger than the threshold value S ₁ and smaller than the threshold value S ₂ B or the number A of adjacent difference data smaller than the threshold value S _1.
If it is determined that there is more, that is, if the change in the block data is large, the process proceeds to step ST17, where the quantization parameter control circuit 15 outputs the coarse quantization scale S to the quantization circuit 3 and the inverse quantization circuit 5, The process ends.

Next, when using the _n threshold values S _{1 to} S _n , first in step ST20 of FIG. 8, the adjacent difference data from the adjacent difference extraction circuit 22 is fetched into the counting circuit 23, and the process proceeds to step ST21. The adjacent difference data is
The threshold values S _{1 to} S _n are classified into a plurality of groups A _{1 to} A _{n + 1} , and the process proceeds to step S22.

At step ST22, each group A
₁ to the number of adjacent difference data belonging to the A _{n + 1} is counted, the process proceeds to step ST23, the groups A ₁ to A _{n + 1}
Counting ratios A ₁ / (A ₁ + A ₂ + ... + A _{n + 1} ) to A _{n + 1}
/ (A ₁ + A ₂ + ... + A _{n + 1} ) is calculated.

Then, the process proceeds to step ST24, the distribution of the counting ratio calculated at step ST23 is determined, and the process proceeds to step ST25.

In step ST25, step ST
The quantization scale S is set based on the determination result of the distribution of the count ratio in 24.

That is, in step ST25, if the concentration position of the group having the larger count ratio is closer to the group A ₁ side, it is determined that the change in the block data is small and smooth, and the quantization parameter control circuit 15 The quantization scale S output to the quantizing circuit 3 and the inverse quantizing circuit 5 is finely divided, and the process ends.

[0076] Further, in step ST25, concentration location of the group count ratio becomes large, apart from the group A ₁ side, the closer to the group A _{n + 1} side, it is determined that a large change of the block data, quantizing The parameter control circuit 15 coarsens the quantization scale S output to the quantization circuit 3 and the inverse quantization circuit 5, and the processing is ended.

Even in the above case, the quantization scale can be adjusted optimally, and the data amount of the variable-length coded data and the compression distortion of the image are balanced to obtain the variable-length coded data of these variable-length coded data. The amount of data or the compression distortion of the image can be minimized.

In the embodiment of FIG. 2, the frequency component distribution (power distribution) of the DCT data is calculated based on the sum of absolute values of the DCT coefficients forming the DCT data output from the DCT circuit 2. However, for example, based on the two-value average value of the DCT coefficient that constitutes the DCT data,
The frequency component distribution (power distribution) of the DCT data can be obtained.

Further, in the present embodiment, MC between frames
Although the compression is performed by the -DCT method, the compression may be performed by the MC-DCT method between fields or another image compression method.

Further, in this embodiment, the BC control circuit 14 (or the BC control circuit 24) and the quantization parameter control circuit 15 are constituted by different ROMs, but these are constituted by a single ROM. The quantization scale S can be directly read from the ROM corresponding to the sum of absolute values of DCT coefficients (or adjacent difference data).

[0081]

As described above, according to the image processing apparatus of the present invention, the difference data between the current block obtained from the current image data and the previous block obtained from the previous image data is calculated, DCT processing is performed to convert to DCT data. Then, the DCT data is quantized with a predetermined quantization scale. At this time, the block criticality of the image is calculated based on the frequency component distribution of the DCT data or the value of the difference data, and the quantization scale for quantizing the DCT data is controlled based on this block criticality. Therefore, since the DCT data can be quantized with an appropriate quantization scale, the deterioration of the decoded image can be reduced.

Further, according to this image processing device, the quantized data output from the quantizing means is temporarily stored in the storing means, and the control means stores the quantized data together with the block criticality calculated by the block criticality calculating means. The quantization scale of the quantizing means is controlled based on the storage amount of the means. Therefore, the DCT data can be quantized with an appropriate quantization scale that balances the data amount of the compression-encoded data and the compression distortion, so that the deterioration of the decoded image can be reduced.

Further, according to this image processing apparatus, since the block criticality calculating means and the control means are composed of at least one ROM, the apparatus can be made compact.

[Brief description of drawings]

FIG. 1 is a diagram illustrating an image block dividing method.

FIG. 2 is a block diagram showing the configuration of an embodiment of the image processing apparatus of the present invention.

3 is a D output from the DCT circuit 2 of the embodiment of FIG. 2;
It is a figure which shows CT data.

FIG. 4 is a block diagram showing the configuration of a second embodiment of the image processing apparatus of the present invention.

FIG. 5 is a diagram for explaining adjacent difference data output from the adjacent difference extraction circuit 22 of the embodiment of FIG.

FIG. 6 is a flowchart for explaining the operation of the embodiment of FIG.

FIG. 7 is a flow chart for explaining the operation of the embodiment of FIG.

FIG. 8 is a flow chart for explaining the operation of the embodiment of FIG.

FIG. 9 is a block diagram showing a configuration of an example of a conventional image processing apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Subtraction circuit 2 DCT circuit 3 Quantization circuit 4 Variable length coding circuit 5 Inverse quantization circuit 6 Inverse DCT circuit 7 Addition circuit 8 Frame memory circuit 9 Motion detection circuit 10 Motion compensation circuit 11 Buffer memory circuit 12 Block criticality generator 13 Absolute value sum circuit 14 BC control circuit 15 Quantization parameter control circuit 21 Block criticality generation unit 22 Adjacent difference extraction circuit 23 Counting circuit 24 BC control circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masakazu Yoshimoto 6-735 Kitashinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation

Claims (6)

[Claims] 1. An image processing device for compressing image data to generate coded data, wherein DCT conversion is performed on difference data between a current block obtained from current image data and a previous block obtained from previous image data. An image processing apparatus, wherein a quantization scale for quantizing the DCT data is controlled based on a frequency component distribution of the DCT data obtained in this way. 2. An image processing apparatus for compressing image data to generate code data, wherein a difference data value between a current block obtained from the current image data and a previous block obtained from the previous image data is set to a value. An image processing apparatus, which controls a quantization scale for quantizing DCT data obtained by DCT-transforming the difference data based on the above. 3. Difference calculation means for calculating difference data between a current block obtained from this image data and a previous block obtained from previous image data; and difference data calculated by the difference calculation means. DC for performing DCT processing and converting the difference data into DCT data
Based on the frequency component distribution of the DCT data output from the DCT means, the T means, the quantization means that quantizes the DCT data output from the DCT means with a predetermined quantization scale, and outputs the quantized data. A block criticality calculating means for calculating the block criticality of the image, and a control means for controlling the quantization scale of the quantizing means based on the block criticality calculated by the block criticality calculating means. An image processing apparatus comprising: 4. A difference calculating means for calculating difference data between a current block obtained from the current image data and a previous block obtained from the previous image data, and the difference data calculated by the difference calculating means. DC for performing DCT processing and converting the difference data into DCT data
Based on the value of the difference data calculated by the difference calculation means; and T means, quantization means for quantizing the DCT data output from the DCT means with a predetermined quantization scale, and outputting the quantized data. A block criticality calculating means for calculating a block criticality of the image, and a control means for controlling a quantization scale of the quantizing means based on the block criticality calculated by the block criticality calculating means. An image processing device characterized by the above. 5. The storage device further comprises a storage device for temporarily storing the quantized data output from the quantization device, and the control device, together with the block criticality calculated by the block criticality calculation device, the storage device. 5. The image processing apparatus according to claim 3, wherein the quantization scale of the quantization means is controlled based on the storage amount of. 6. The image processing apparatus according to claim 3, wherein the block criticality calculation means and the control means are composed of at least one ROM.