JPH05234386A - Semiconductor memory device and its erasure and write method - Google Patents

Abstract

PURPOSE:To perform the erasure operation and the write operation of a memory under an optimum condition in a wide temperature range by a method wherein an optimum voltage value for the erasure operation and the write operation is read out from a memory circuit by means of the digital output of a temperature detection circuit, the optimum voltage value is converted into an analog value and the optimum voltage value is input to a nonvolatile memory transistor. CONSTITUTION:A piece of digital temperature information T in a digital temperature detection circuit 51 is input to a memory circuit 55; an optimum digital voltage value D for an erasure operation and a write operation is output from an address T. Its output signal 57 is input to a nonvolatile transistor via a D/A converter. Thereby, the erasure operation and the write operation can be performed under an optimum voltage condition.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device including a semiconductor nonvolatile memory and an erasing / writing method thereof.

[0002]

Nonvolatile memory is a dynamic memory,
Unlike static memory, it retains stored contents even when power supply is stopped, and is widely used in various devices.

The principle of the write and erase operations of the non-volatile memory is a sectional view showing the non-volatile memory transistor of FIG.
3 and a circuit diagram showing an equivalent circuit of the nonvolatile memory transistor of FIG. 2 and 3
The same numbers are assigned to the same portions of.

The nonvolatile memory transistor provided on the semiconductor substrate 11 is provided with a gate insulating film 13 and a gate electrode 17 in the gate portion of the channel region, and is connected to the drain electrode 15 connected to the drain region 29 and the source region 31. It has a source electrode 19 and a substrate electrode 21 connected to the substrate connection region 33.

The gate insulating film 13 has a laminated structure of an oxide film and a nitride film, or an oxide film, a nitride film and an oxide film.

The substrate electrode 21 and the source electrode 19 are the third
Are both connected to the terminal 27 of.

The drain electrode 15 is connected to the first terminal 23, and the gate electrode 17 is connected to the second terminal 25.

The non-volatile memory transistor applies a voltage higher than a normal operating voltage, that is, a voltage of 10V to 18V in general, between the second terminal 25 and the third terminal 27. As a result, depending on the polarity of the applied voltage,
Writing and erasing are performed by trapping charges in the level for trapping charges in the gate insulating film 13 or releasing charges from the levels in the gate insulating film 13 for trapping charges.

At the time of writing and erasing, the second terminal 2
The value of the voltage applied between the fifth terminal 5 and the third terminal 27 greatly affects the deterioration of the nonvolatile memory transistor and the retention characteristic of written data.

That is, the second terminal 25 and the third terminal 27
The higher the voltage applied between and is, the more the deterioration of the non-volatile memory transistor progresses, but on the other hand, the data retention characteristic is improved, which is a contradictory characteristic. For this reason, the voltages at the time of writing and erasing determine the optimum value of the voltage to be applied by balancing these characteristics.

[0011]

However, since the optimum value of the voltage at the time of writing and erasing varies depending on the temperature, there is a problem that the characteristics of the non-volatile memory cannot be sufficiently brought out in the environment where the temperature changes. is there.

An object of the present invention is to solve the above problems and provide a semiconductor memory device capable of sufficiently bringing out the characteristics of a non-volatile memory in a wider temperature range than in the past, and an erasing / writing method thereof. It is in.

[0013]

In order to achieve the above object, the present invention employs the following configurations and methods.

In the semiconductor memory device of the present invention, a plurality of source regions and drain regions of opposite conductivity type are formed on a semiconductor substrate of one conductivity type and are separated from each other, and a plurality of channel regions are provided between the source and drain regions. A non-volatile memory transistor having a gate portion in which a multi-layered gate insulating film and a gate electrode are sequentially formed and having a level for trapping charges in at least one of the multi-layered gate insulating films; and for digitally outputting temperature information. Of the digital temperature detection circuit of, and the output of this digital temperature detection circuit as the first digital output,
A memory circuit for converting the first digital output into the second digital output and a digital-analog converter for converting the second digital output, which is the output of the memory circuit, into a voltage are provided. It is characterized by

According to the method for erasing and writing a semiconductor memory device of the present invention, a source region and a drain region of opposite conductivity type are formed on a semiconductor substrate of one conductivity type so as to be separated from each other, and a channel between the source region and the drain region. A non-volatile memory transistor having a gate portion in which a plurality of layers of gate insulating films and gate electrodes are sequentially formed on a region and having a level for trapping charges in at least one of the plurality of layers of gate insulating films; A digital temperature detection circuit for digital output, a memory circuit for converting the first digital output to a second digital output by using the output of the digital temperature detection circuit as a first digital output, and the memory circuit And a digital-analog converter for converting the second digital output, which is the output of the Wherein the use of the output voltage as the erasing and the voltage at the time of writing of the nonvolatile memory transistor.

[0016]

Embodiments of the semiconductor memory device of the present invention and the erase / write method thereof will be described below with reference to the drawings. FIG. 1 is a circuit diagram for explaining a configuration of a semiconductor memory device of the present invention and an erase / write method. First, the configuration of the semiconductor memory device of the present invention will be described.

The semiconductor memory device includes a digital temperature detecting circuit 51 as means for digitally outputting temperature information, and a first
Memory circuit 55 as means for converting the digital output of the temperature information, which is the digital output of
A digital-analog converter (hereinafter referred to as an A / D converter) 59 as a means for converting the second digital output output from the memory circuit 55 into a voltage, and an N-type non-volatile memory transistor 67. It consists of.

The digital output of the digital temperature detecting circuit 51 is connected to the address line of the memory circuit 55 by the bit line 53. The data line of the memory circuit 55 is the bit line 57.
Is connected to the digital input of the A / D converter 59.

The voltage output of the A / D converter 59 is connected to the gate terminal 63 and the source terminal 61 of the nonvolatile memory transistor 67.

Further, the non-volatile memory transistor 67
The substrate terminal 65 of is connected to the source terminal 61.

Next, an erasing / writing method of the semiconductor memory device having the above-mentioned structure will be described. The optimum erase and write voltage of the nonvolatile memory transistor 67 at a certain temperature is V, the digital value of the digital output of the digital temperature detection circuit 51 is T, and the optimum erase and write voltage V is output by the A / D converter 59. Supposing that the digital value of the digital input required by the semiconductor memory device is D, the above-mentioned digital value D is written in the address T of the memory circuit 55, and data is stored in the memory circuit 55 over the entire temperature range in which the semiconductor memory device is used. Write.

In this way, at various temperatures,
When erasing and writing to the non-volatile memory transistor 67, the optimum erasing and writing voltage at that temperature is always applied to the gate terminal 63 and the source terminal 61 of the non-volatile memory transistor 67 to erase under the optimum voltage condition. And writing can be performed.

[0023]

As described above, according to the semiconductor memory device and the erasing / writing method of the present invention, erasing and writing can be performed in a wide temperature range under the optimum voltage condition for the nonvolatile memory transistor. .. Therefore, the characteristics of the non-volatile memory can be sufficiently brought out.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a semiconductor memory device of the present invention.

FIG. 2 is a cross-sectional view showing a nonvolatile memory transistor.

FIG. 3 is a circuit diagram showing an equivalent circuit of a nonvolatile memory transistor.

[Explanation of symbols]

 13 Gate Insulating Film 15 Drain Electrode 17 Gate Electrode 19 Source Electrode 21 Substrate Electrode 51 Digital Temperature Detection Circuit 55 Memory Circuit 59 A / D Converter 67 Nonvolatile Memory Transistor

Claims (2)

[Claims] 1. A plurality of layers of gates are formed on a channel region between a source region and a drain region of opposite conductivity type to a semiconductor substrate which are formed on a semiconductor substrate of one conductivity type and separated from each other. A non-volatile memory transistor including a gate portion in which an insulating film and a gate electrode are sequentially formed, having a level for trapping charges in at least one of a plurality of layers of gate insulating film, and a digital temperature for digitally outputting temperature information. A detection circuit, and a memory circuit for converting the first digital output into a second digital output, with the output of the digital temperature detection circuit as the first digital output,
A semiconductor memory device comprising: a digital-analog converter for converting a second digital output which is an output of the memory circuit into a voltage. 2. A plurality of layers of gates on a channel region between a source region and a drain region of opposite conductivity type to a semiconductor substrate formed separately from each other on a semiconductor substrate of one conductivity type. A non-volatile memory transistor including a gate portion in which an insulating film and a gate electrode are sequentially formed, having a level for trapping charges in at least one of a plurality of layers of gate insulating film, and a digital temperature for digitally outputting temperature information. A detection circuit, and a memory circuit for converting the first digital output into a second digital output, with the output of the digital temperature detection circuit as the first digital output,
A digital-analog converter for converting the second digital output, which is the output of the memory circuit, into a voltage, and using the output voltage of the digital-analog converter as the voltage when erasing and writing the nonvolatile memory transistor. An erasing / writing method for a semiconductor memory device, comprising: