JPH0523503B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an inspection apparatus for inspecting LSI wafer patterns and the like, including detecting and measuring fine patterns such as LSI patterns.

[Background of the invention]

LSI products are manufactured by forming layers of circuit patterns such as SiO ₂ on Si wafers, and during this process, inspecting the patterns of each layer for shape defects is essential to ensuring product yield.

An example of a conventional inspection device is shown in FIG. Sample 1
objective lens 2, illumination optical system 3,
It is composed of a semi-transparent mirror 4 and a detector 5. The illumination optical system 3 and the objective lens 2 constitute an epi-illumination system, and as shown in FIG. 6 occurs. Here, the specularly reflected light 7 is zero-order diffracted light (DC component), and the higher-order reflected light 6 involved in detection is 1st to Nth higher-order diffracted light (here, N is determined by the aperture of the objective lens 2). ).

The detector 5 uses a CCD or a photodiode array, and obtains a detection signal 8 from the sample shown in FIG. Signal 8 passes through a differentiating circuit (not shown) to obtain signal 9.d. Signal 9 and set threshold 10,1
Binarized signal 9a indicating the edge position by comparing
get e.

The detector 5 and the sample 1 are relatively scanned, the signal 9a is stored two-dimensionally, and the edge binarized image 12 shown in FIG. 15a is obtained. Defects 13, 14, and 15 are detected by comparing the binarized image 12 with a standard pattern 16 stored in advance in a memory circuit.

The standard pattern 16 may be a pattern created from design data or a pattern in an adjacent chip detected in advance on the same wafer.

An example of a method for comparing pattern 12 and pattern 16 is shown in FIG. Figure a and b are each pattern 1.
2 and 16 are shown, and extraction patterns 17 and 18 are obtained. Similarly, extraction patterns 19 and 20 in the horizontal direction are shown in c and d. Similarly right
Extraction pattern edges 21 and 22 at 45° and 45° to the left are shown in e and d. Extraction results a and b, c and d, e and f
If the discrepancy is detected by comparing each, defect 13,
Get 14,15. A circuit for performing the above processing is shown in Japanese Patent Laid-Open No. 133022/1983.

In addition to the above edge information, pattern defects include the first
Etched residue 23 of PolySi layer 23 shown in Figure 7
There is a flat part defect as in example a. Originally, the PolySi 23 was removed from this part, but due to a defect in the previous process, the PolySi remains, resulting in a defective cell circuit.

This defect 23a cannot be detected using the edge information described above. This defect is detected, for example, by comparing the brightness information 7 of the reflected light of the adjacent good cell circuit 23b with the cell circuit 23a.

However, this brightness information 7 is affected by stray light 27 generated on the surface of the objective lens 2 and other optical elements, and becomes a detection signal 8a shown in FIG. 18b, allowing accurate brightness detection. There is a problem that it cannot be done.

[Purpose of the invention]

SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide an inspection apparatus for LSI wafer patterns, etc., which can accurately detect brightness and edge positions and automatically inspect pattern defects in a stable manner.

[Summary of the invention]

In the present invention, separate optical systems are provided to obtain edge information and brightness information, and the former optically extracts only the high-order reflected light 6 from the edge, and the latter uses an optical isolator system to remove stray light. However, the feature is that the wafer pattern is detected by processing both pieces of information separately. This method is simpler, cheaper, and more stable than the conventional method of extracting edges and brightness using pattern recognition techniques.

[Embodiments of the invention]

FIG. 1 shows an optical system that detects only high-order reflected light 6 from pattern edges and blocks specularly reflected light 7. If a light shielding plate 27 is installed on the Fourier transform surface of the objective lens 2 to block only the specularly reflected light 7, only the higher-order reflected light will reach the detector 5a. Detector 5
By relatively scanning a and the sample 1, an inspection signal 8b shown in c is obtained. This optical system allows for a stable edge shape without being affected by specularly reflected light 7 (Figure 2a).
is obtained.

FIG. 2 shows an optical system for blocking light 27 of the objective lens 2. In FIG. This is called an optical isolator system.
It is composed of a polarizing beam splitter 4a and a quarter wavelength plate 29. When S-polarized light is used as the illumination light 3a, it is totally reflected by the polarization beam splitter 4a. Stray light 2 from the surface of objective lens 2 maintains S polarization and therefore does not reach detector 5a. The illumination light that illuminates the sample 1a passes through the quarter-wave plate 29 twice, so it becomes P-polarized light, passes through the polarization beam splitter 4a, and reaches the detector 5a. The detection signal 8c shown in b obtained thereby is not affected by the stray light 27.

In the optical systems shown in FIGS. 1 and 2 described above, when a laser beam is used as the illumination light 3a, high brightness can be easily obtained, so that a detection signal with a high S/N ratio can be obtained.

Next, a method for improving the resolution of the detection system is shown in FIGS. 3 to 5.

In FIG. 3, the semi-transmissive mirror 4 is omitted and the principle is shown expanded to the illumination system 3 and the detection system 34. The point light source 3b formed by the pinhole 33 is connected to the objective lens 2.
As a result, the light spreads over the sample to form a distribution 3c, and an infinitesimal pattern 30 on the sample is illuminated. The infinitesimal pattern 30 spreads to form a distribution 31 on the image plane of the objective lens 2. When the pinhole 28 is placed at this position, the spread distribution 31 becomes the distribution 32 after passing through the pinhole 28, resulting in improved resolution.

Here, the spread 31 is the radius M×R (=M×0.61λ/
NA), so it is effective to make the pinhole 28 smaller than this. (Here, M is the magnification of the objective lens 2, λ is the wavelength of the illumination light 3b, and NA is the aperture of the objective lens.) The improvement in resolution in FIG. 8 will be explained with reference to FIGS. 4 and 5. When the upper layer of the sample 1 is formed of a transparent layer 35 such as SiO ₂ , due to the effect of the pinhole 28,
An enlarged image i' of the upper pattern i and an enlarged image j' of the lower pattern j can be separated (FIG. 4). This improves vertical resolution.

Similarly, the enlarged image k' of point k and the enlarged image l' of point l can be separated by the pinhole 28, and the resolution in the lateral direction is also improved (FIG. 5).

FIG. 6 shows an embodiment of the present invention. This is the first
This is a combination of the optical systems shown in FIGS. 2 and 3. The detection systems in FIGS. 1 and 2 are branched by a branching mirror 36, and the former has a pinhole 28.
b, a detector 5b; in the latter, a pinhole 28c and a detector 5c were installed as necessary. Since the detector 5c detects brightness, the pinhole 28 is not necessarily detected.
c is not necessary. In this embodiment, the illumination light from the illumination optical system 3 is made into parallel light by the condenser lens 35, the objective lens 2 is made into an afocal system, and the light shielding plate 27 is installed on the Fourier transform surface of the imaging lens 37. At this time, the magnification M of the detection system 34 is
and the focal length of the imaging lens 2a (f ₁ /f). Detection signals 8b and 8c of detectors 5b and 5c
can be output simultaneously, and by creating a binarized image 12 and a brightness image using these signals 8b and 8c, and comparing them with each normal image, defects (edge defects 13, 14, 15 and brightness Defect 23
a) can be detected.

Fig. 7 shows the signal 8b of the detectors 5b and 5c in Fig. 6.
A method for creating a composite image of and 8c will be explained. Sample 1
are scanned by a scanning means, and two-dimensional images E and F of appropriate size are stored in meseri circuits 37a and 37b. The amplifier circuits 38 and 39 multiply E and F by preset constants α and β, and create an image (αE+βF) in the storage circuit 40. If α is set larger than β, an image with emphasized edges (αE+βF) can be created. If the generated image and the image G ₀ stored in advance in the memory circuit 50 are compared in the comparison circuit 51, the edge defects 13 and 1 described above are detected.
4, 15, the brightness defect 23a can be detected. image
G ₀ may be an image calculated from design data or a detected image of the same position of adjacent chips within the same sample wafer.

FIG. 8 shows a method of detecting defects by comparing each of the two-dimensional images E and F with pre-stored images E ₀ and F ₀ . The image E stored in the memory circuit 37a and the image _E0 stored in the memory circuit 52 are compared in the comparison circuit 53, and the mismatched portions (defects 13, 14, 15) are compared with the image E0 stored in the memory circuit 52.
6 is stored.

The relationship between the lower layer 26 and the upper layer 25 of sample 1 is as shown in FIG. 9, and there is an allowable overlay error (alignment error) between these two layers. For example, images E ₀ 52 and E37a are shown in FIG.
The upper layer 25 of E is located 5 pixels higher in the y direction than the upper layer 25 of E ₀ . At this time, if the unmatched portion shown in FIG. 3 is extracted, a defect will be extracted even though there is no defect. To prevent this, the comparison circuit 56 performs the following operation. That is,
Corresponding to the above-mentioned allowed overlay error (9th
Move image E one pixel at a time in the y direction within a pixel range (5 pixels in the figure) and compare it with image E ₀ ,
Only the mismatched portions in all comparisons are extracted and treated as defects. In Fig. 9, for the sake of simplicity, we have explained the overlay error only in the y direction, but there is generally an overlay error in the x and y directions.For example, if the tolerance for 5 pixels in both the x and y directions is 25 (5 x 5 ) comparisons are made. As a result, if the image E is in Fig. 15a and the image _E0 is in Fig. 9a, even if an overlay error occurs, defects 13, 14,
15 can be detected. Naturally, images E (Fig. 9b) and E ₀
In the comparison shown in FIG. 9a, no defects are detected. The circuit for detecting a mismatched portion while shifting the above image in the x and y directions is the same as in References 2 and 3.

As shown in FIG. 9, the area around the edge is affected by pattern errors, and the brightness information based on the film thickness shown in FIG. 9 cannot be clearly detected, so the brightness image F3
When comparing 7b and F ₀ 54, it is desirable to exclude the portions around the edges. FIG. 10 shows a procedure for removing comparisons around this edge.

Since the brightness image F37b and the image E37a are stored simultaneously, the edge enlargement circuit 57 obtains the image H (FIG. 10c). This is a process of expanding the edge image E by appropriate pixels in the x and y directions. Similarly, the edge enlarging circuit 61 obtains the image H ₀ from the image F ₀ 54 and the image E ₀ 52. Here, images H and H ₀ are “0” and “1” images (binarized images)
"0" indicates the area around the edge, and "1" indicates the other area. If continuous areas of "1" are extracted from images H and _H0 , closed areas '~' and ~ are obtained. Originally, for the same number of closed regions in images F and F ₀ ,
have the same brightness. The brightness in the corresponding regions of the closed regions ′ to ′ and ˜ of the multivalent images F and F ₀ is extracted by brightness extraction circuits 55 and 62 . This is the average value of the brightness within the area. For example, in the area ', the sum of brightness within m' × n' pixels is averaged by m' × n', and in the corresponding area, the sum of brightness within m × n pixels is averaged by m' × n'. The total brightness is averaged by m×n. The average brightness within the corresponding areas is compared by a comparison circuit 58, and if there is a difference in brightness, the defect 23a is stored in the memory circuit 59.

Edge defect memory 56 and brightness defect memory 59
is connected to the OR circuit 60, so the OR circuit 60 outputs all defects.

A method of removing only the area around the pattern edge from the above image F will be described. When image F is stored in the masking circuit 55 with H, only the edges around the image F are “
Similarly, F ₀ is stored in a circuit 62 that masks F 0 with H _0. In circuits 55 and 62, only the edges around the image F and the multivalued image of F ₀ are stored as “
0'' is stored. Taking into account the above-mentioned overlay tolerance, a circuit 58 calculates the difference between images 55 and 62 to create a difference image, and compares this with a set threshold. Then, the brightness defect 23a is obtained.When performing the above calculation here, if the other party is "0"
In this case (around the edge), if the comparison result is ignored, no defect will be detected.

An example of a circuit for realizing this is shown in FIG. “
The 0'' level determination circuits 65 and 66 are circuits that determine whether or not the information f ₀ and f of each pixel of F ₀ and F is “ ₀ ”.
becomes “1” when is “0”, and furthermore, the inverting circuit 68
The output "0" is obtained. The differential amplifier 58a is f
−f ₀ is calculated, and this difference signal is compared with the threshold value TH in the comparator circuit 58b. When the AND circuit 58c calculates the logical sum of the output of the circuit 58b and the output of the inversion circuit 68, the output is only the defect 23a, and information around the edges can be ignored.

The standard images E ₀ and F ₀ mentioned above may be calculated from design data, or images detected at the same position of adjacent chips in the same sample may be used.

FIG. 12 shows an embodiment of a detection optical system using a laser 63 as a light source. The laser beam from the pinhole 33 placed between the lenses 64 and 35 forms a spot with a diameter a on the sample 1 by the objective lens 2.

As the rotating polygon mirror 62 rotates, the spot scans the sample in the x direction. When the sample 1 is sent in the y direction by a stage (not shown) in synchronization with this, images E and F are respectively stored in the memory circuit 37a (and 37b). In the figure, illustration of the light shielding plate 27, the quarter wavelength plate 29, etc. is omitted for simplicity.

FIG. 13 shows an embodiment in which one-dimensional solid-state imaging devices are used for collective illumination and detectors 5c and 5b. It is important that the size of one pixel of the solid-state image sensing device be smaller than the pinhole diameter 28 (M×R) explained in FIG. In FIGS. 12 and 13, the entire surface of the sample 1 can be inspected by feeding the sample 1 in a zigzag manner in the y direction.

As described above, according to the present invention, minute pattern defects can be stably detected.

[Brief explanation of the drawing]

Figure 1 shows the external appearance of the detection device according to the present invention and sample 1.
FIG. 2 is a diagram showing a cross section and signal waveform of the detection device according to the present invention, and FIG.
The figure shows the optical path of the optical system according to the present invention, FIGS. 4 and 5 are optical path diagrams, FIG. 6 is an optical path diagram showing an embodiment of the present invention, and FIGS. The electrical processing block diagram of the embodiment, FIG. 9, is an image F ₀ (or
Figure ₁₀ shows the plane of image F and the plane of images E, H, H ₀
FIG. 11 is an electrical circuit diagram for not performing comparison processing of brightness near edges;
Figure 12 is an external view of the laser scanning detection optical system,
3 is an external view of the collective illumination detection optical system, and FIG. 14 is a diagram showing the external appearance of the conventional detection device, the cross section of the sample 1, the waveform of the signal 8, the differential waveform 9 of the signal 8, and the binarized signal waveform. FIG. 15 is a diagram showing the plane of pattern 12 and the plane of pattern 16, and FIG. 16 is a diagram showing the plane of pattern 1.
17 is a diagram showing a cross section of sample 1, and FIG. 18 is a diagram showing the appearance and signal waveform of a conventional detection device. 1, 1a...sample, 2...objective lens, 2a...
...Imaging lens, 3, 3a, 3b...Light source, 4...
Semi-transparent mirror, 5, 5a, 5b, 5c...detector, 6
...High-order reflected light, 7... Specular reflected light, 8, 8a, 8
b...Detection signal, 9...Differential signal, 10, 11...
...Threshold value, 9a... Binarized signal, 12... Pattern to be inspected, 16... Standard pattern, 13, 14,
15... Defect, 17... Vertical edge extracted image of pattern 12, 18... Vertical edge extracted image of pattern 16, 19... Horizontal edge extracted image of pattern 12, 20... Horizontal edge of pattern 16 Extracted image, 21...±45° direction edge extraction image of pattern 12, 22...± of pattern 16
45° direction edge extraction image, 23...PolySi layer, 2
3a...PolySi removed part (normal part), 23b...
PolySi etching residue, 24... ₄ layers of Si ₃ O, 2
5...SiO ₂ layer, 26...Si layer, 27...light shielding plate,
28, 28a, 28b...pinhole, 29...
1/4 wavelength plate, 30... infinitesimal pattern, 31...
Spread of infinitesimal pattern, 3c... Spread of point light source, 32... Spread of light passing through pinhole, 33...
...Pinhole, 34...Detection system, 35...Transparent layer (SiO ₂ etc.), 36...Semi-transparent mirror, 37a, 37b
...Memory circuit, 38, 39...Amplification circuit, 40
... Memory circuit, 50 ... Memory circuit, 51 ... Comparison circuit, 52, 54 ... Memory circuit, 53 ... Comparison circuit, 55, 62 ... Brightness extraction circuit (masking circuit), 57, 61 ... Edge expansion circuit, 5
6... Edge defect memory, 59... Brightness defect memory, 58... Brightness comparison circuit, 60... OR circuit, 63... Laser, 64... Lens, 62...
Rotating polygon mirror, 65, 66...Level judgment circuit, 6
7...OR circuit, 68...Inversion circuit, 58a...
Differential amplifier, 58b... Comparison circuit, 58c...
AND circuit, 69...mirror.

Claims (1)

[Claims] 1. An optical system for illumination, a first detection means for detecting high-order reflected light from the edges of the pattern, and an optical isolator system are installed to remove stray light and 1. An inspection device for LSI patterns, etc., comprising: second detection means for detecting the brightness of an area. 2 The edge information obtained by the first detection means is
Claim 1, characterized in that it has a comparison circuit that compares the brightness information obtained by the second detection means with the second brightness information. Inspection equipment for LSI patterns, etc. 3 The edge information obtained by the first detection means and the second
An inspection device for an LSI pattern or the like according to claim 1, further comprising a comparison circuit that compares information obtained by combining the brightness information obtained by the detection means with the second information. 4. Claims 2 or 3, characterized in that, when comparing brightness information, there is an extraction means for ignoring the vicinity of pattern edges and extracting only the area excluding the influence of the edges. As stated in the section
Inspection equipment for LSI patterns, etc.