JPH05232898A - Image signal processing circuit - Google Patents

Abstract

PURPOSE:To reduce the action frequency of an image signal processing circuit for a matrix type display by a small memory circuit scale. CONSTITUTION:An image signal which is serially sent is successively stored in a memory 1. Two set of memories 2 consisting of the plural memories 1 are provided. While the image signal is written in a set of memories, the image signal written in the other set of memories is read out at the same time. The image signal is read out through a selection circuit 4 and the read image signal is fetched by a data driving circuit 5 at the same time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal processing circuit of a matrix type image display device.

[0002]

2. Description of the Related Art Generally, a flat panel such as a liquid crystal display or a plasma display is used as a matrix type image display device. Compared with cathode ray tubes, these flat panel displays have the advantages of space saving and low power consumption, and are under development.

In a drive circuit for inputting a drive signal to a panel of a matrix type image display device, image signals sent in series are rearranged in the drive circuit and input in parallel to the panel. 1 of personal computer as image signal
When a bit digital signal (black and white) is used, the frequency of the image signal is about 18 MHz. On the other hand, in the data drive circuit, since the operating frequency is limited by the shift register and the data register circuit that configure the rearrangement circuit,
The data driving circuit operates at about 10 MHz. Therefore, it is necessary to store the high-speed image signal in the memory or the like once, read it at a low frequency matching the operating frequency of the data driving circuit, and send it to the data driving circuit.

FIG. 5 shows a block diagram of a conventional image signal processing circuit, and FIG. 6 shows a timing chart for explaining the operation of the block diagram of FIG. In FIG. 5, 3 is a switch,
Reference numeral 4 is a selection circuit including a switch 3, 5 is a data drive circuit, 6 is a scanning circuit, 7 is a liquid crystal panel, 8 is a control circuit, 1
Reference numeral 4 denotes a line memory having 320 memories therein, the number of pixels of the liquid crystal panel 7 is 640 × 400, and two line memories 14 store data for one line.
The liquid crystal panel 7 is an active matrix type having an amorphous thin film transistor in each pixel. The data drive circuit 5 has 320 output terminals, and two drive terminals drive 640 data lines of the liquid crystal panel 7. The image signal signal fetching frequency of this data driving circuit is 10 at maximum.
MHz.

In the timing diagram of FIG. 6, the operation of the line memory 14 is shown, and the numbers 1 to 640 indicate the order of the image signal of one line. W is a period for writing the digital image signal in the memory as data, and R is a period for reading from the memory.

The operation of this image signal processing circuit will be described.
The image signals 1 to 320 in the first half of the first line are stored in (1) of the line memory 14, and the image signals 321 to 640 in the second half of the first line are subsequently stored in (2) of the line memory 14. The writing frequency is about 18 MHz. In the period of the second line, the selection circuit 4 selects the line memory (1) and the line memory (2), and the image signals are read in parallel from these line memories (1) and (2).

Since the image signal of the first line is divided into the first half and the latter half and stored in the line memories (1) and (2), the first image signal and the 321st image signal are arranged in parallel. It is read. Similarly, the second, the 322nd, the third, and the 323th are read. The read frequency becomes 9 MHz, which is half the write frequency, and can be taken in by the data drive circuit 5. In the period of the second line, the image signals 1 to 320 in the first half are stored in (3) of the line memory 14, and the image signals 321 to 6 in the second half are continuously stored.
40 is stored in (4) of the line memory 14. The image signals 1 to 320 output from the line memory (1) are sequentially input to (3) of the data driving circuit 5, and the image signals 321 to 640 output from the line memory (2) are (4) of the data driving circuit 5. ) Are sequentially input. The input image signals are stored in the data registers in the data drive circuits (3) and (4) and arranged, and the image signals 1 to 640 are sent to the liquid crystal panel 7 all at once during the period of the third line.

The signal sent to the liquid crystal panel is converted into a signal of about ± 5 V by the level shift circuit in (3) and (4) of the data driving circuit 5a for driving the liquid crystal. By applying an ON pulse from the scanning circuit 6 to the first line of the liquid crystal panel 7 in the period of the third line, the thin film transistor whose gate is connected to the first line is turned on, and the image signals 1 to 640 of the first line are predetermined. Is displayed at the position. In the period of the third line, the image signal of the first half of the third line is written in (1) of the line memory 14 in the first half,
In the latter half, the latter half and the image signal are written in (2) of the line memory 14.

In the period of the third line, the selection circuit (4) selects the outputs of the line memories (3) and (4), and the image signal output from the line memory (3) is the data drive circuit (3). ) And the image signal output from the line memory (4) is input to the data drive circuit (4).
The input image signals are arranged in the data registers in the data driving circuits (3) and (4), and the image signals 1 to 640 are sent to the liquid crystal panel 7 all at once during the period of the fourth line, and the image signals of the liquid crystal panel 7 are displayed. An on pulse is applied to two lines. By repeating this operation and sequentially displaying the image signals of one line, one image display can be obtained.

In the prior art, two sets of two line memories 14 are prepared, an image signal for one line is divided into the first half and the second half and stored, and when the image signal is read, the two image signals of the first half and the latter half are stored. Are read in parallel and input to the two data drive circuits 5 in parallel. According to this method, the image signal fetch frequency of the data driving circuit can be halved as compared with the image signal frequency.

[0011]

However, in the prior art, four line memories 14 are required as shown in FIG. 5, and the image signal is 1 bit (black and white) instead of 1 bit.
In order to obtain 6-gradation display, it is necessary to process a 4-bit signal, and a line memory is required. Therefore, an increase in the number of parts in the signal processing circuit section increases the cost of parts, and an increase in the area of parts limits the miniaturization of the device.

Further, generally, the data driving circuit is one integrated circuit. Integrating a large number of memories into a data driving circuit is disadvantageous in terms of manufacturing cost because the chip area of the integrated circuit increases.

It is an object of the present invention to provide an image signal processing circuit by simplifying the memory circuit section without increasing the operating frequency of the data driving circuit section.

[0014]

According to the structure of the present invention, in an image signal processing circuit for rearranging serial image signals and inputting the image signals in parallel to the matrix image display device, the image signals sequentially sent are sequentially stored, Two sets of storage circuits for simultaneously sending out the plurality of stored image signals are provided, and a selection circuit for selecting the plurality of image signals output from one of the two sets of storage circuits is provided. A driving circuit for sequentially fetching the plurality of image signals sent from the two sets of memory circuits for each set of the plurality of image signals, rearranging the image signals, and sending the arranged image signals to the matrix type image display device. Is characterized by.

[0015]

1 is a block diagram of a first embodiment of an image signal processing circuit according to the present invention, and FIG. 2 is a timing chart for explaining the operation of FIG. In the figure, an image signal is an image signal of a personal computer, 1 is a memory, 2 is a set of memories including two memories, 3 is a switch, 4 is a selection circuit including a switch 3, 5 is a data drive circuit, and 6 is a scan. Circuit, 7
Is a liquid crystal panel, and 8 is a control circuit. The image signal is a 1-bit (black and white) digital signal. (1) of memory 1
From (4) to (4), one bit of the image signal is stored.
The image signal is sequentially stored in the memories (1) to (4).
Further, the reading of the memory 1 is carried out one by one, with the memories (1) and (2) and the memories (3) and (4) as one set. The two read image signals are originally continuous image signals for two pixels, and are simultaneously taken into the data drive circuit 5 through the selection circuit 4. The frequency of capturing (reading from the memory circuit) the image signal to the data drive circuit is
It is half the writing frequency of the image signal to the memory circuit.

The number of pixels of the liquid crystal panel 7 is 640 × 4.
00, which is an active matrix type having an amorphous thin film transistor in each pixel. Data drive circuit 5
Has two image signal input terminals and simultaneously receives two image signals. The data drive circuit 5 has 320 output terminals, and two drive terminals drive 640 data lines of the liquid crystal panel 7. The control circuit 8 controls each circuit.

In the operation diagram of FIG. 2, the operations (1) to (4) of the memory 1 are shown, and the numbers 1 to 640 indicate the order of the image signal of one line. W is a period for writing the digital image signal in the memory as data, and R is a period for reading from the memory.

Next, the operation of this embodiment will be described. The first image signal of the first line is written in (1) of the memory 1,
Next, the second image signal is written in (2) of the memory 1. The writing frequency is about 18 MHz. Third,
During the period in which the fourth image signal is sequentially written in the memory (3) and the memory (4), the output of the memory (1) and the memory (2) is selected by the selection circuit 4, and the first image signal and
And the second image signal are read out in parallel. The read frequency becomes 9 MHz, which is half the write frequency, and can be taken in by the data drive circuit 5.

The two image signals are stored in the data register in (1) of the data driving circuit 5. Further, the fifth and sixth image signals are stored in the memory (1) and the memory (2).
In the period in which writing is sequentially performed on the memory, the outputs of the memory (3) and the memory (4) are selected by the selection circuit, two of the third image signal and the fourth image signal are read in parallel,
Then, it is stored in (1) of the data driving circuit 4.

After repeating this operation and sequentially inputting and storing 320 image signals to the data driving circuit (1), the image signals 321 to 640 are similarly input to the data driving circuit (2) by 2 times.
Two image signals are sequentially input in parallel. The input image signals are stored in the data registers in the data driving circuits (1) and (2) and arranged, and the image signals 1 to 640 are sent to the liquid crystal panel 7 all at once during the period of the second line.

The signal sent to the liquid crystal panel 7 is converted into a signal of about ± 5 V by the level shift circuits in the data driving circuits (1) and (2) for driving the liquid crystal. Second
By applying an on-pulse from the scanning circuit 6 to the first line of the liquid crystal panel 7 during the line period, the thin film transistor whose gate is connected to the first line is turned on, and the image signals 1 to 640 of the first line are at predetermined positions. Displayed in.
Even in the period of the second line of the image signal, the image signal is sequentially written to the memories 1 to 4 as in the case of the first line, and the selection circuit 4 selects the memories (1) and (2) or the memories (3) and (4). Output is selected, and two image signals are read out in parallel.

Two image signals are supplied to the data drive circuit (1)
Sequentially stored in the internal data register. After storing 320 image signals in the data driving circuit (1), the image signals 3
Similarly, 21 to 640 sequentially input two image signals in parallel to the data driving circuit (2). The input image signals are stored in the data registers in the data driving circuits (1) and (2) and arranged, and the image signals 1 are output during the third run-in period.
To 640 are sent to the liquid crystal panel 7 all at once. By repeating this operation and sequentially displaying image signals of one line, one image display can be obtained.

FIG. 3 is a detailed block diagram of the data driving circuit 5 embodying the memory 1 of FIG. 1, and FIG.
3 is a timing diagram illustrating the operation of FIG. In the figure, the memory 1 of FIG. 1 is shown by a D-type flip-flop (D-FF) 9, and two D-FFs 9 make up a memory set 2. The image signals and the clocks (1) to (4) are input to the D-FFs (1) to (4), and the D-FFs (1) to (4) rise from the clocks (1) to (4). Sometimes captures image signals. Two switches 3 (SW1, SW2)
Constitutes a selection circuit 4, and the switch 3 selects one from two inputs.

The data driving circuit 5 includes the shift register 1
0, a data register 11, a latch circuit 12, a level shifter 13 and the like. The start pulse is a pulse for starting the operation of the shift register 10, and the image signal data (1), (2), (3), ... Are stored in the data register 11 at the rising edge of the clock.

In FIG. 4, the output of each D-FF 9 is Q.
Indicated by. Clocks, pulses, etc. for controlling the respective parts of the circuit are generated in (1) of the control circuit 8 in FIG. As shown in FIG. 4, SW is applied to the frequency at which the image signal is sent.
The output frequencies of 1 and SW2 are half, and the image signal data is stored in the data register 11 in synchronization with the clock. Image signals 1 to 320 are stored. Actually, there is another data driving circuit 5, and the image signal data 321 to 640 are stored in this data driving circuit 5. The image signal data stored in the data register 11 is simultaneously fetched by the latch circuit 12, amplified by the level shifter 13 to about ± 5 V for driving the liquid crystal, and sent to the liquid crystal panel 7.

In the conventional example, it was necessary to prepare two sets of two line memories 14, but according to the image signal processing circuit of the present embodiment, the number of memories 1 is four and the frequency of the image signal is different. In comparison, the image signal acquisition frequency of the data drive circuit can be halved.

In this embodiment, the image signal is a 1-bit (black and white) signal. However, when processing a signal of 2 bits or more for gradation display, the number of memories in one set can be increased. Since a 16-bit image signal handles a 4-bit digital signal, a memory circuit portion is configured with a total of 16 memories, the number of switches is increased, the number of data register registers is increased, and the level shifter is used to display a liquid crystal gradation display voltage. Should be generated. In this case as well, the scale of the selection circuit section and the data drive circuit is almost the same as in the conventional case, and the circuit scale can be reduced because a large number of line memories are not required in the memory circuit section. Also, in the case of a color image signal, it can be dealt with by increasing the number of memories in one set.

In this embodiment, one set of memory circuits is composed of two memories. However, one set of three memories is used to sequentially write the image signals into the three memories, and then the image signals of three pixels are written. Is sent to the data drive circuit, and the data drive circuit 5 takes in these three image signals at the same time, so that
The data driving circuit can be operated at the frequency of.
The number of outputs of the data driving circuit 5 is not limited to 320.

In the present embodiment, the image signal of the personal computer is dealt with, but the present invention can be applied to a high speed image signal such as a workstation or a high-definition television. Further, in the present embodiment, a digital signal is used. Even if the signal is analog, memory, data register,
If a sample hold circuit is used for the latch circuit or the like, the signal can be processed similarly.

Further, although the conventional data driving circuit is manufactured by one integrated circuit, since the memory circuit section requires a large-scale line memory, the memory circuit section alone is manufactured as another integrated circuit. However, according to the present embodiment, since the scale of the memory portion is small, the data driving circuit and the memory portion can be integrated into an integrated circuit. Further, although the liquid crystal panel is used in the present embodiment, it can be applied to other matrix type displays such as a plasma display.

[0031]

As described above, the image signal processing circuit of the present invention has an effect that the operating frequency of the data driving circuit can be lowered with a small memory circuit scale.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of an image signal processing circuit of the present invention.

FIG. 2 is a timing diagram illustrating the operation of FIG.

FIG. 3 is a detailed block diagram of the image signal processing circuit of FIG.

FIG. 4 is a waveform diagram illustrating the operation of FIG.

FIG. 5 is a block diagram of an example of a conventional image signal processing circuit.

FIG. 6 is a timing diagram illustrating the operation of FIG.

[Explanation of symbols]

 1 Memory 2 Memory Set 3 Switch 4 Selection Circuit 5 Data Driving Circuit 6 Scanning Circuit 7 Liquid Crystal Panel 8 Control Circuit 9 D-Type Flip-Flop 10 Shift Register 11 Data Register 12 Latch Circuit 13 Level Shifter 14 Line Memory

Claims (1)

[Claims] 1. An image signal processing circuit for rearranging serial image signals and inputting the image signals in parallel to a matrix type image display device, sequentially storing the sequentially transmitted image signals, and storing the plurality of stored image signals. There are two sets of memory circuits that send all at the same time, and one of these two sets of memory circuits
A selection circuit for selecting the plurality of image signals output from the group is provided, and the plurality of image signals transmitted from the two sets of storage circuits are sequentially taken in through the selection circuit for each group of the plurality of image signals. An image signal processing circuit comprising a driving circuit for rearranging the images in the matrix type and sending them to the matrix type image display device.