JPH05243307A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05243307A JPH05243307A JP4076390A JP7639092A JPH05243307A JP H05243307 A JPH05243307 A JP H05243307A JP 4076390 A JP4076390 A JP 4076390A JP 7639092 A JP7639092 A JP 7639092A JP H05243307 A JPH05243307 A JP H05243307A
- Authority
- JP
- Japan
- Prior art keywords
- wire
- semiconductor chip
- bonded
- bonding
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7865—Means for transporting the components to be connected
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
(57)【要約】
【目的】 ワイヤボンディングが施された半導体チップ
部を封止する樹脂注入の際、長い接続の金属細線の変形
をなくし、隣の金属細線や内部リードへの接触を防ぎ、
品質を向上する。
【構成】 半導体チップ１と内部リード４とのボンディ
ングの金属細線６のうち、長くて変形しやすい部分の接
続を、剛性の大きい金属細線１０などの導体にし、樹脂
注入の際の変形をなくし、接触事故を防ぐ。
(57) [Abstract] [Purpose] When injecting resin to seal a semiconductor chip that has been wire-bonded, eliminate the deformation of metal wires with long connections and prevent contact with adjacent metal wires or internal leads.
Improve quality. [Structure] Among the metal thin wires 6 for bonding the semiconductor chip 1 and the internal leads 4, a long and easily deformable part is connected to a conductor such as a metal thin wire 10 having high rigidity to eliminate deformation during resin injection. Prevent contact accidents.
Description
【０００１】[0001]
【産業上の利用分野】この発明は、半導体チップと内部
リードをワイヤボンディングし、樹脂封止した半導体装
置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor chip and internal leads are wire-bonded and resin-sealed.
【０００２】[0002]
【従来の技術】図９は従来の半導体装置を示すワイヤボ
ンディング部の平面図である。図において、１はリード
フレーム２のダイパッド３にダイボンディングされた半
導体チップ、４はリードフレームに形成された多数の内
部リード、６は半導体チップ１と内部リード４とをワイ
ヤボンディングした金属細線で、例えば金線からなる。
ワイヤボンディングを終えた半導体チップ部１は、後工
程で鎖線で示すように、樹脂封止体７の成形で封止され
る。2. Description of the Related Art FIG. 9 is a plan view of a wire bonding portion showing a conventional semiconductor device. In the figure, 1 is a semiconductor chip die-bonded to the die pad 3 of the lead frame 2, 4 is a large number of internal leads formed on the lead frame, 6 is a thin metal wire formed by wire bonding the semiconductor chip 1 and the internal lead 4, For example, it consists of a gold wire.
The semiconductor chip portion 1 that has completed the wire bonding is sealed by molding the resin sealing body 7 as shown by a chain line in a later step.
【０００３】図１０は半導体装置の組立て工程を示す説
明図である。ダイボンド工程で、リードフレーム２のダ
イパッド３上に半導体チップ１をろう材で接着する。つ
づいて、ワイヤボンド工程で、半導体チップ１の各電極
と対応する各内部リード４とを、金属細線６でワイヤボ
ンディングする。次に、樹脂封止工程で、半導体チップ
１部を成形金型により合成樹脂を注入し成形し、樹脂封
止体７で封止する。後工程で、内部リード４の先端側の
リード部５を残し、リードフレーム２の不要部をプレス
により切断除去し、リード部５を折曲げ整形し、樹脂封
止の半導体装置が出来上る。FIG. 10 is an explanatory view showing a process of assembling a semiconductor device. In the die bonding process, the semiconductor chip 1 is bonded onto the die pad 3 of the lead frame 2 with a brazing material. Subsequently, in a wire bonding step, the electrodes of the semiconductor chip 1 and the corresponding internal leads 4 are wire-bonded with the thin metal wires 6. Next, in the resin encapsulation step, a part of the semiconductor chip is injected and molded with a synthetic resin by a molding die, and is encapsulated with the resin encapsulant 7. In a subsequent process, the lead portion 5 on the tip side of the inner lead 4 is left, the unnecessary portion of the lead frame 2 is cut and removed by pressing, and the lead portion 5 is bent and shaped, whereby a resin-sealed semiconductor device is completed.
【０００４】[0004]
【発明が解決しようとする課題】上記のような従来の半
導体装置では、ワイヤボンディングされた半導体チップ
１部を、成形金型内で樹脂を圧入し封止する際、金属細
線６のうち、半導体チップ１の角部の電極をワイヤボン
ディングした長い金属細線６が、注入樹脂により押し曲
げられ変形し、図９に鎖線で示すように隣の金属細線６
や内部リード４に接触するという問題点があった。In the conventional semiconductor device as described above, when the wire-bonded semiconductor chip 1 part is sealed by press-fitting resin in the molding die, the semiconductor wire in the metal thin wire 6 is the semiconductor. The long metal thin wire 6 to which the electrode at the corner of the chip 1 is wire-bonded is pressed and deformed by the injected resin, and as shown by the chain line in FIG.
There is a problem in that it contacts the internal lead 4.
【０００５】この発明は、このような問題点を解決する
ためになされたもので、半導体チップと内部リードをワ
イヤボンディングした金属細線のうち、変形しやすい長
い間隔の線を変形しないようにし、隣の金属細線や内部
リードへの接触をなくし、品質を向上した半導体装置を
得ることを目的としている。The present invention has been made in order to solve such a problem, and in the thin metal wire formed by wire bonding the semiconductor chip and the inner lead, a wire which is easily deformed and has a long interval is not deformed, and the adjacent wire is prevented from being deformed. It is an object of the present invention to obtain a semiconductor device with improved quality by eliminating contact with the metal thin wires and the internal leads.
【０００６】[0006]
【課題を解決するための手段】この発明にかかる半導体
装置は、ワイヤボンディングの金属細線のうち、長くて
変形しやすい線を、剛性を大きくし変形しない接続手段
にしたものである。In the semiconductor device according to the present invention, among the metal thin wires for wire bonding, long and easily deformable wires are used as connecting means which have a high rigidity and do not deform.
【０００７】[0007]
【作用】この発明においては、ワイヤボンディングの金
属細線のうち、長くて変形しやすい線を、強度の大な材
質にするか、線径を大きくするか、曲げ強度の大な接続
手段によるかしており、樹脂注入の際の変形がなくな
り、隣の金属細線や内部リードとの接触が防止される。In the present invention, among the thin metal wires for wire bonding, the long and easily deformable wire is made of a material having a large strength, a wire diameter is made large, or a connecting means having a large bending strength is used. Therefore, there is no deformation at the time of resin injection, and contact with adjacent metal fine wires or internal leads is prevented.
【０００８】[0008]
【実施例】実施例１．図１はこの発明による半導体装置
の一実施例を示す、半導体チップとリードフレームのワ
イヤボンディング部の平面図である。図において、リー
ドフレーム２のダイパッド３にダイボンディングされた
半導体チップ１の各電極と、対応する各内部リード４と
を金属細線（金線からなる）６でワイヤボンディングし
ている。しかし、半導体チップ１の角部の電極と対応す
る内部リード４とは距離が他より大きく、線が長くな
る。このため、この部分の金属細線（金線からなる）１
０は線径を他の金属細線６より太いものを使用し、剛性
を大きくし、変形を小さくしている。EXAMPLES Example 1. 1 is a plan view of a wire bonding portion of a semiconductor chip and a lead frame, showing an embodiment of a semiconductor device according to the present invention. In the figure, each electrode of the semiconductor chip 1 die-bonded to the die pad 3 of the lead frame 2 and each corresponding internal lead 4 are wire-bonded with a thin metal wire (made of a gold wire) 6. However, the distance between the electrodes at the corners of the semiconductor chip 1 and the corresponding internal leads 4 is larger than the others, and the line becomes long. Therefore, the thin metal wire (made of gold wire) 1
For 0, a wire whose diameter is thicker than the other thin metal wires 6 is used to increase the rigidity and reduce the deformation.
【０００９】上記一実施例の装置では、ワイヤボンディ
ング工程を終えた半導体チップ１部を、成形金型内に入
れ樹脂を圧入すると、長い金属細線１０は他よりも剛性
が大きいので、変形することなく、隣の金属細線６や内
部リード４に接触することがない。７は樹脂封体を示
す。なお、長い金属細線１０の剛性を大きくするのに、
他の金属細線４より剛性の大きい材質、例えば銅線を用
いてもよい。In the apparatus of the above-mentioned embodiment, when one portion of the semiconductor chip which has undergone the wire bonding process is put into the molding die and the resin is press-fitted therein, the long thin metal wire 10 has a higher rigidity than the other, so that it is deformed. There is no contact with the adjacent metal thin wire 6 or the inner lead 4. Reference numeral 7 represents a resin envelope. In addition, in order to increase the rigidity of the long thin metal wire 10,
A material having a rigidity higher than that of the other thin metal wires 4, for example, a copper wire may be used.
【００１０】上記一実施例の装置のワイヤボンディング
方法を、現行の設備を使った場合を図２により説明す
る。まず、（Ａ）図のように、第１ワイヤボンダ１１の
ボンディングヘッド１１ａにより、架台１１ｂ上のリー
ドフレーム２の半導体チップ１と内部リード４との、短
かく線径の小さい金属細線６のワイヤボンディングをす
る。この状態のリードフレーム２を（Ｂ）図に平面図で
示す。つづいて、金属細線６でワイヤボンディングされ
たリードフレーム２を、第２ワイヤボンダ１２の架台１
２ｂ上に送り、ボンディングヘッド１２ａにより距離の
長い線径の大きい金属細線１０でワイヤボンディングす
る。この状態のリードフレーム２を（Ｃ）図に平面図で
示す。なお、先に第２ワイヤボンダ１２で長くて線径の
大きい金属細線１０のワイヤボンディングを施した後、
第１ワイヤボンディング１１で短くて線径の小さい金属
細線６のワイヤボンディングを施すようにしてもよい。The wire bonding method of the apparatus of the above-mentioned one embodiment will be described with reference to FIG. 2 when the existing equipment is used. First, as shown in FIG. 3A, the bonding head 11a of the first wire bonder 11 is used to wire-bond the semiconductor chip 1 of the lead frame 2 on the pedestal 11b and the internal lead 4 to the thin metal wire 6 having a small diameter. do. The lead frame 2 in this state is shown in a plan view in FIG. Next, the lead frame 2 wire-bonded with the fine metal wires 6 is attached to the mount 1 of the second wire bonder 12.
2b, and the wire is bonded by the bonding head 12a with the metal thin wire 10 having a long distance and a large wire diameter. The lead frame 2 in this state is shown in a plan view in FIG. In addition, after wire-bonding the long metal wire 10 having a large wire diameter with the second wire bonder 12 first,
The first wire bonding 11 may be used to wire-bond the thin metal wire 6 which is short and has a small wire diameter.
【００１１】実施例２．次に、図３は２つのボンディン
グヘッドを設けたワイヤボンダの設備を使う場合を示
す。（Ａ）図のように、ワイヤボンダ１３の架台１３ｃ
上にリードフレーム２を間欠送りする。まず、ボンディ
ングヘッド１３ａで半導体チップ１に短くて小径の金属
細線６のワイヤボンディングする。この状態を（Ｂ）図
のリードフレームの平面図で左側に示す。金属細線６で
ワイヤボンディングされた半導体チップ１部が、ボンデ
ィングヘッド１３ｂ下に至ると、長くて大径の金属細線
１０のワイヤボンディングをする。この状態を（Ｂ）図
で右側に示す。なお、ワイヤボンダのボンディングヘッ
ドの配置は、並列、対向、Ｖ字形など、いづれでも可能
である。Embodiment 2. Next, FIG. 3 shows a case where a wire bonder facility provided with two bonding heads is used. (A) As shown in the figure, the mount 13c of the wire bonder 13
The lead frame 2 is intermittently fed above. First, the bonding head 13a is used to wire-bond the short, small-diameter thin metal wire 6 to the semiconductor chip 1. This state is shown on the left side in the plan view of the lead frame in FIG. When the portion of the semiconductor chip 1 wire-bonded with the thin metal wire 6 reaches below the bonding head 13b, the long, large-diameter thin metal wire 10 is wire-bonded. This state is shown on the right side in FIG. The bonding heads of the wire bonder may be arranged in parallel, facing each other, or in a V shape.
【００１２】実施例３．図４（Ａ）は３つのボンディン
グヘッドをＶ字形配置した例を示す。ワイヤボンダ１４
の架台１４ｄ上に、マガジン１５からリードフレーム２
が間欠送りされている。第１ボンディングヘッド１４ａ
で小径で短い金属細線（例えば金線）６を、（Ｂ）図に
示すようにワイヤボンディングする。また、第２ボンデ
ィングヘッド１４ｂで大径で長い金属細線（例えば金
線）１０を、（Ｂ）図に示すようにワイヤボンディング
する。さらに、半導体チップ１の中央部電極と対応する
内部リード４ａとを、第３ボンディングヘッド１４ｃに
より金属細線６より剛性の大きい金属細線（銅線）１７
で（Ｂ）図に示すようにワイヤボンディングしている。
このように、ボンディングヘッド１４ａ、１４ｂ、１４
ｃをＶ字形配置したワイヤボンダ１４を使うことによ
り、同時に３種類のワイヤボンドができる。ワイヤボン
ドを終えたリードフレーム２は、マガジン１６に収容さ
れる。Embodiment 3. FIG. 4A shows an example in which three bonding heads are arranged in a V shape. Wire bonder 14
From the magazine 15 to the lead frame 2 on the stand 14d of
Has been intermittently fed. First bonding head 14a
Then, a thin metal wire (for example, a gold wire) 6 having a small diameter and a small diameter is wire-bonded as shown in FIG. Further, the metal wire 10 having a large diameter and a long length (for example, a gold wire) 10 is wire-bonded by the second bonding head 14b as shown in FIG. Furthermore, the central lead of the semiconductor chip 1 and the corresponding internal lead 4a are connected by the third bonding head 14c to a metal thin wire (copper wire) 17 having a rigidity higher than that of the metal thin wire 6.
Then, wire bonding is performed as shown in FIG.
In this way, the bonding heads 14a, 14b, 14
By using the wire bonder 14 in which c is arranged in a V shape, three types of wire bonds can be simultaneously made. The lead frame 2 after wire bonding is housed in the magazine 16.
【００１３】実施例４．なお、上記実施例では、リード
フレーム２のダイパッド３に１個の半導体チップ１を接
着した場合を示したが、図５に示すように、２個の半導
体チップ（例えばＩＣチップ）２１をダイパッド３に接
着した場合にも適用できる。Embodiment 4. In the above embodiment, one semiconductor chip 1 is bonded to the die pad 3 of the lead frame 2, but as shown in FIG. 5, two semiconductor chips (for example, IC chips) 21 are attached to the die pad 3. It can also be applied when adhered to.
【００１４】実施例５．図６はこの発明の実施例５によ
る半導体装置の半導体チップ部の、接続導体ボンディン
グを示す平面図である。半導体チップ１の各電極と対応
する距離の小さい内部リード４とを、短かく線径の小さ
い金属細線（金線）６でワイヤボンディングしている。
半導体チップ１の４隅の電極と対応する距離の大きい内
部リード２とを導体付着絶縁材テープ１８により、ボン
ディングしている。導体付着絶縁材テープ１８は、
（Ｂ）図に示すように、ポリイミドテープなどの絶縁テ
ープ１９の上面に導体２０が付着されており、この導体
２０からバンプ２１が絶縁テープ１９の下面に出されて
いる。この導体付着絶縁材テープ１８のバンプ２１で、
半導体チップ１と内部リードとを圧着接続している。Example 5. 6 is a plan view showing connection conductor bonding of a semiconductor chip portion of a semiconductor device according to a fifth embodiment of the present invention. Each electrode of the semiconductor chip 1 and the corresponding inner lead 4 having a small distance are wire-bonded with a fine metal wire (gold wire) 6 having a short wire diameter.
The electrodes at the four corners of the semiconductor chip 1 are bonded to the internal leads 2 corresponding to a large distance by the conductor-attached insulating material tape 18. The conductor attached insulating tape 18 is
As shown in (B), a conductor 20 is attached to the upper surface of an insulating tape 19 such as a polyimide tape, and bumps 21 are projected from the conductor 20 to the lower surface of the insulating tape 19. With the bumps 21 of the conductor-attached insulating tape 18,
The semiconductor chip 1 and the internal leads are pressure-bonded to each other.
【００１５】実施例６．図７はこの発明の実施例６によ
る半導体装置の、半導体チップのワイヤボンディング部
を示す平面図である。リードフレーム２には多数の内部
リード４が設けられ、半導体チップ１の４隅に対応し、
載置リード２５が出されている。この載置リード２５の
先端部上面にバンプ２６が設けられている。半導体チッ
プ１の４隅を載置リード２５のバンプ２６上に載せ圧着
して接合する。つづいて、半導体チップ１の各電極と対
応する内部リード４とを、短かくて線径の小さい金属細
線（例えば金線）６でワイヤボンディングする。載置リ
ード２５は剛性が大きく、樹脂封止の際変形することな
く、隣の金属細線６や内部リード４に接触することはな
い。なお、上記実施例６では、載置リード２５にバンプ
２６を設けたが、半導体チップ１の下面に、半導体ウエ
ーハの処理工程でバンプを設けたものにしてもよい。Embodiment 6. 7 is a plan view showing a wire bonding portion of a semiconductor chip of a semiconductor device according to a sixth embodiment of the present invention. The lead frame 2 is provided with a large number of internal leads 4 corresponding to the four corners of the semiconductor chip 1,
The mounting lead 25 is exposed. A bump 26 is provided on the upper surface of the tip of the mounting lead 25. The four corners of the semiconductor chip 1 are placed on the bumps 26 of the mounting lead 25 and pressure-bonded. Subsequently, each electrode of the semiconductor chip 1 and the corresponding internal lead 4 are wire-bonded with a thin metal wire (for example, a gold wire) 6 having a short wire diameter. The mounting lead 25 has a high rigidity, does not deform during resin sealing, and does not come into contact with the adjacent thin metal wire 6 or the internal lead 4. Although the mounting lead 25 is provided with the bump 26 in the sixth embodiment, the lower surface of the semiconductor chip 1 may be provided with the bump during the semiconductor wafer processing step.
【００１６】上記図７の半導体チップのワイヤボンディ
ングの、ボンダ装置を図８に示す。ボンダ装置３０の架
台３１上に、マガジン１５からリードフレーム２が間欠
送りされている。架台３１上の半導体ウエーハ４０から
分割された半導体チップ１を、吸着ヘッド３２で吸着し
ステージ３３上に置く。つづいて、ステージ３３がバン
プ圧着装置３４の方へ移動しリードフレーム２の載置リ
ード２５のバンプ２６上に位置決めして載せる。バンプ
圧着装置３４の圧着ヘッド３４ａが下降し、半導体チッ
プ１をバンプ２６に圧着し接合する。半導体チップ１が
バンプ圧着されたリードフレーム２は、ワイヤボンド部
に移送され、ボンディングヘッド３５により、半導体チ
ップ１の各電極と対応する短い距離の各内部リード４と
を、線径の小さい金属細線（例えば金線）６でワイヤボ
ンディングする。ワイヤボンディングが終了したリード
フレーム２をマガジン１６に収容する。FIG. 8 shows a bonder device for wire bonding the semiconductor chip shown in FIG. The lead frame 2 is intermittently fed from the magazine 15 onto the base 31 of the bonder device 30. The semiconductor chip 1 divided from the semiconductor wafer 40 on the pedestal 31 is sucked by the suction head 32 and placed on the stage 33. Subsequently, the stage 33 moves toward the bump crimping device 34 and positions and mounts it on the bumps 26 of the mounting leads 25 of the lead frame 2. The crimping head 34a of the bump crimping device 34 descends to crimp and bond the semiconductor chip 1 to the bumps 26. The lead frame 2 on which the semiconductor chip 1 is bump-bonded is transferred to the wire bond portion, and the bonding head 35 connects each electrode of the semiconductor chip 1 and each internal lead 4 corresponding to a short distance to a thin metal wire having a small wire diameter. (For example, a gold wire) 6 is wire bonded. The lead frame 2 for which wire bonding has been completed is housed in the magazine 16.
【００１７】[0017]
【発明の効果】以上のように、この発明によれば、半導
体チップの電極と内部リードとの接続を、距離の小さい
部分は線径の小さい金属細線でワイヤボンディングを
し、距離の大きい部分は剛性を大きくした導体を用いて
接続手段で接続したので、半導体チップ部の樹脂封止に
際し、従来のように長い金属細線が曲げられ変形するよ
うなことがなく、隣の金属細線や内部リードに接触する
ことが防がれ、品質が向上される。As described above, according to the present invention, the electrodes of the semiconductor chip and the internal leads are connected by wire bonding with a fine metal wire having a small wire diameter at a portion having a small distance and at a portion having a large distance. Since the conductors with increased rigidity are connected by the connecting means, the long metal thin wires are not bent and deformed unlike the conventional case when resin-sealing the semiconductor chip part. Contact is prevented and quality is improved.
【図１】この発明による半導体装置の一実施例を示す、
ワイヤボンディングされた半導体チップとリードフレー
ムの要部平面図である。FIG. 1 shows an embodiment of a semiconductor device according to the present invention,
It is a principal part top view of the semiconductor chip and the lead frame which were wire-bonded.
【図２】（Ａ）図は図１のワイヤボンディングを施すた
めの２台のワイヤボンダの正面図、（Ｂ）図は（Ａ）図
の第１ワイヤボンダにより施されたワイヤボンディング
部を示すリードフレームの概略平面図、（Ｃ）図は
（Ａ）図の第２ワイヤボンダにより施されたワイヤボン
ディング部を示すリードフレームの概略平面図である。2A is a front view of two wire bonders for performing the wire bonding shown in FIG. 1, and FIG. 2B is a lead frame showing a wire bonding portion made by the first wire bonder shown in FIG. 2A. And (C) is a schematic plan view of a lead frame showing a wire bonding portion applied by the second wire bonder of (A).
【図３】この発明の実施例２を示し、（Ａ）図は図１の
ワイヤボンディングを施すための２組のボンディングヘ
ッドを設けたワイヤボンダの正面図、（Ｂ）は（Ａ）の
ワイヤボンダにより施されたワイヤボンディング部を示
すリードフレームの概略平面図である。3A and 3B show a second embodiment of the present invention. FIG. 3A is a front view of a wire bonder having two sets of bonding heads for performing wire bonding of FIG. 1, and FIG. 3B is a view of the wire bonder of FIG. FIG. 6 is a schematic plan view of a lead frame showing a wire bonding portion applied.
【図４】この発明の実施例３を示し、（Ａ）図は３組の
ボンディングヘッドがＶ形配置されたワイヤボンダの斜
視図、（Ｂ）図は（Ａ）図のワイヤボンダで施されたワ
イヤボンディング部を示すリードフレームの概略平面図
である。4A and 4B show a third embodiment of the present invention, in which FIG. 4A is a perspective view of a wire bonder in which three sets of bonding heads are arranged in a V shape, and FIG. 4B is a wire bonded by the wire bonder in FIG. It is a schematic plan view of the lead frame which shows a bonding part.
【図５】この発明による半導体装置の実施例４を示す、
ワイヤボンディングされたリードフレーム部の概略平面
図である。FIG. 5 shows Embodiment 4 of the semiconductor device according to the present invention,
It is a schematic plan view of the leadframe part by which wire bonding was carried out.
【図６】（Ａ）図はこの発明による半導体装置の実施例
５を示す、ワイヤボンディングされた半導体チップとリ
ードフレームの要部平面図、（Ｂ）図は（Ａ）図の導体
付絶縁テープの斜視図である。FIG. 6A is a plan view of a wire-bonded semiconductor chip and a lead frame, showing a fifth embodiment of a semiconductor device according to the present invention; FIG. 6B is an insulating tape with a conductor shown in FIG. FIG.
【図７】この発明による半導体装置の実施例６を示す、
ワイヤボンディングされた半導体チップとリードフレー
ムの要部平面図である。FIG. 7 shows Embodiment 6 of the semiconductor device according to the present invention,
It is a principal part top view of the semiconductor chip and the lead frame which were wire-bonded.
【図８】図７のワイヤボンディング及びバンプ圧着を施
すためのボンダ装置の斜視図である。8 is a perspective view of a bonder device for performing the wire bonding and bump pressure bonding of FIG. 7. FIG.
【図９】従来の半導体装置を示すワイヤボンディングさ
れた半導体チップとリードフレームの要部平面図であ
る。FIG. 9 is a plan view of a main portion of a wire-bonded semiconductor chip and a lead frame showing a conventional semiconductor device.
【図１０】半導体装置の組立工程を示す説明図である。FIG. 10 is an explanatory diagram showing a process of assembling a semiconductor device.
１ 半導体チップ ２ リードフレーム ３ ダイパッド ４ 内部リード ６ 金属細線 10 金属細線 18 導体付着絶縁テープ 21 バンプ 25 載置リード 26 バンプ 1 Semiconductor Chip 2 Lead Frame 3 Die Pad 4 Internal Lead 6 Metal Fine Wire 10 Metal Fine Wire 18 Conductor Adhesive Insulation Tape 21 Bump 25 Mounted Lead 26 Bump
Claims (3)
プの各電極と対応する内部リードをワイヤボンディング
した半導体装置において、 上記半導体チップの電極と対応する内部リードの距離の
短い箇所は、線径の小さい金属細線でワイヤボンディン
グをし、距離の長い箇所は、上記短い箇所の金属細線よ
り剛性の大きい金属細線でワイヤボンディングをしたこ
とを特徴とする半導体装置。1. In a semiconductor device in which an internal lead corresponding to each electrode of a semiconductor chip joined to a lead frame is wire-bonded, a portion having a short distance between the internal lead corresponding to the electrode of the semiconductor chip has a small wire diameter. A semiconductor device, wherein wire bonding is performed with a thin metal wire, and a long distance portion is bonded with a thin metal wire having a rigidity higher than that of the narrow thin metal wire.
プの各電極と対応する内部リードをワイヤボンディング
した半導体装置において、 上記半導体チップの電極と対応する内部リードの距離の
短い箇所は、線径の小さい金属細線でワイヤボンディン
グをし、距離の長い箇所は、導体付着絶縁テープにより
バンプで圧着接続したことを特徴とする半導体装置。2. In a semiconductor device in which an internal lead corresponding to each electrode of a semiconductor chip bonded to a lead frame is wire-bonded, a portion having a short distance between the electrode of the semiconductor chip and the corresponding internal lead has a small wire diameter. A semiconductor device in which wire bonding is performed with a thin metal wire, and a long distance portion is pressure-bonded and connected with a bump by a conductor-adhering insulating tape.
リードフレームからそれぞれ載置リードを延長し、各載
置リードの先端部に上記半導体チップの４隅を載せ、バ
ンプで圧着接合し、上記半導体チップの電極と対応する
内部リードの距離の短い箇所は、線径の小さい金属細線
でワイヤボンディングしたことを特徴とする半導体装
置。3. A semiconductor chip is provided at a position facing four corners of the semiconductor chip,
The mounting leads are respectively extended from the lead frame, the four corners of the semiconductor chip are mounted on the tips of the mounting leads, and the bumps are pressure-bonded to each other. A semiconductor device characterized by being wire-bonded with a thin metal wire having a small wire diameter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4076390A JPH05243307A (en) | 1992-02-26 | 1992-02-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4076390A JPH05243307A (en) | 1992-02-26 | 1992-02-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05243307A true JPH05243307A (en) | 1993-09-21 |
Family
ID=13604000
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4076390A Pending JPH05243307A (en) | 1992-02-26 | 1992-02-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05243307A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08236564A (en) * | 1995-02-28 | 1996-09-13 | Nec Kyushu Ltd | Semiconductor device |
| JP2012028429A (en) * | 2010-07-21 | 2012-02-09 | Renesas Electronics Corp | Semiconductor device and method of manufacturing the same |
| KR101447055B1 (en) * | 2012-10-04 | 2014-10-08 | (주)한영이엔지 | Power line connecting structure of oled device |
-
1992
- 1992-02-26 JP JP4076390A patent/JPH05243307A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08236564A (en) * | 1995-02-28 | 1996-09-13 | Nec Kyushu Ltd | Semiconductor device |
| JP2012028429A (en) * | 2010-07-21 | 2012-02-09 | Renesas Electronics Corp | Semiconductor device and method of manufacturing the same |
| US8525306B2 (en) | 2010-07-21 | 2013-09-03 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
| US8710637B2 (en) | 2010-07-21 | 2014-04-29 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
| KR101447055B1 (en) * | 2012-10-04 | 2014-10-08 | (주)한영이엔지 | Power line connecting structure of oled device |
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