JPH05265859A - Buffer storage error processing system - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a buffer storage error processing method for performing error processing by moving out or invalidating a block when an error occurs in buffer storage. A buffer storage device 13 is a data unit 1 which is accessed by a request from the central processing unit 1 and registers data.
4b, a first tag unit 14 that manages entries and registers a block address, and a second tag unit 15 that is accessed by a request from another device and has the same contents as the first tag unit 14 There is. First tag section 14
If an error is detected in, the moveout or block invalidation is performed using the information of the second tag unit 15, and if an error is detected in the second tag unit 15,
The first information is used to move out or invalidate the block.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device in which one or a plurality of central processing units provided with a set-associative store-in type buffer storage device share one or a plurality of main storage devices. The present invention relates to a buffer storage error processing method for restarting processing when an error occurs in a buffer storage device.

[0002]

2. Description of the Related Art Conventionally, in a data processing device, a storage device is hierarchized, for example, a main storage device using a low speed / large capacity storage element and a buffer storage device using a high speed / small capacity storage element. ing. The buffer storage has a copy of the blocks that subdivide the data on the main storage,
The apparent access from the processing device to the storage device is accelerated.

Usually, a set associative method is used for mapping the buffer storage device. In this set associative method, a plurality of WAs are accessed on a line accessed by using a part of the address of the block.
Y is provided, and the block address excluding the bits used for the data and line address is registered in each WAY. The part that registers this data is called the data part, and the part that registers the block address is called the tag part.

On the other hand, control of the buffer storage device is roughly classified into two types: (1) store-through system and (2) store-in (swap) system. (1) In the store-through method, in fetch access, if the target block is not in the buffer storage device, the block is moved in from the main storage device to the buffer storage device, and in store access, it is stored in the buffer storage device. If there is such a block, the data is stored in both the buffer storage device and the main storage device, and if there is no block to be stored, the data is stored only in the main storage device. (2) On the other hand, in the store-in method, both fetch access and store access perform move-in from the main storage device when there is no target block in the buffer storage device, and during store access, the buffer storage device Store only to. Then, at the time of move-in, if the block to be replaced is a block that has been stored in the past, or another processing device that shares the main memory stores a block that has not yet been stored in the main memory. If necessary, the block is moved out from the buffer storage device to the main storage device.

When comparing these two equations,
(1) Since the store-through method does not require a move-out operation, it is easier to control than the store-in method.
Even if an error occurs in the buffer storage device, the latest data reflecting the store is in the main storage device,
Only when the block in the buffer storage device is invalidated, the processing when the error occurs can be performed.

However, each time the processor accesses the store, a store to the main memory occurs,
In particular, when the number of processors sharing the main memory increases, there has been a problem that the waiting time for accessing the main memory increases. Therefore, when there are many processing devices sharing the main storage device, the (2) store-in type buffer storage device is generally adopted.

However, when an error occurs in the buffer storage device, since the latest data is only in this buffer storage device, it is impossible to invalidate the block in the buffer storage device as a measure when the error occurs. There was a problem. Also, as the error mentioned above,
For example, in a semiconductor memory, a soft error in which a value stored in the memory is garbled may occur due to the influence of α rays or the like. As one of the measures against this soft error, ECC (Erro
r Checking and Correction) code is added to the data. The addition of ECC is widely applied to a main memory and a control memory in a processing device that stores a microprogram.

However, an extra semiconductor memory is required as another ECC code part of the data part, and
A lot of hardware is required to generate a C code or to correct an error by an ECC code. For this reason,
It is difficult to use this ECC code when the buffer storage device has a physical quantity limitation.

[0009]

Further, (2) in the store-in type storage device, the contents stored in the buffer storage device may be changed irrespective of the contents of the main storage device. is there. Therefore, when an error occurs in the buffer storage device, the error must be corrected in the buffer storage device to make it accessible again.

Alternatively, it was necessary to correct the error, return the contents of the buffer storage device to the main storage device, and invalidate the buffer storage device. However, if the information itself indicating the position on the main memory to be returned is corrupted, the contents of the buffer storage device could not be returned to the main storage device. For this reason, the processing cannot be continued. Therefore, the processing is continued by issuing an interrupt as a hard error.

An object of the present invention is to provide a buffer storage error processing method capable of avoiding an error occurrence state by performing moveout or block invalidation even when an error occurs in the buffer storage device. To do.

[0012]

The present invention has the following constitution in order to solve the above problems. FIG. 1 shows the principle of the present invention. In FIG. 1, the storage control unit 13 stores a data portion 14b that is accessed in synchronization with a main pipeline that flows in response to a request from the instruction control unit 11 and registers data, and a first portion that manages an entry and registers a block address. Tag unit 14 of the first tag unit 14 that is accessed by a request from another device and
The second tag unit 15 having the same content as the above.

The first tag portion 14 and the second tag portion 1
Reference numeral 5 indicates each of an exclusive flag E indicating that the block can be changed, a change flag C indicating that the block has been changed, and an address part indicating a part of the address on the main memory of the block. , When an error is detected, it has a parity bit independently so that which part of the error can be found.

If an error is detected in the first tag unit 14 and the error is in the address unit, and if the exclusive flag (E) and the change flag C are on, the second tag unit is It was configured to perform moveout using 15 pieces of information. More preferably, the following is desirable. That is, when an error is detected in the second tag section 15 and the error is in the address section, when the exclusive flag (E) and the change flag C are on,
The move-out is performed using the information of the first tag unit 14.

When an error occurs in the first tag unit 14 or the second tag unit 15, the exclusion flag E has no error, and the exclusion flag E is off,
It is configured to invalidate the block. Further, when an error occurs in the first tag unit 14 and the error is the exclusion flag (E) or the change flag (C), the exclusion is performed in the access of the second tag unit 15. When the flag E is off, the block is invalidated, and when an error occurs in the second tag unit 15, the error is the exclusive flag (E) or the change flag (C). In this case, in the access of the first tag unit 14, when the exclusive flag E is off, the block is invalidated.

[0016]

According to the present invention, the first accessed in the request from the instruction control unit IU11 in the central processing unit.
When an error is detected in one of the tag units in the store-in buffer storage having the second tag unit having the same content as the first tag unit accessed in the request from the storage controller Since the move-out is performed on the main storage device by referring to the information of the other tag portion, the error process can be performed.

Further, when there is no error in the exclusive flag E and the change flag C in each tag section and the block is in the unchanged state, the error processing can be performed by simply invalidating the block. Also, the exclusive flag E of one tag part,
In the other tag access when the error is detected by the change flag C, even when the block is not changed, the process at the time of error can be performed by simply invalidating the block.

In this way, paying attention to the fact that the two tag parts provided for use in synchronization with the pipeline of the independent processing device have the same contents, and by using them for the processing at the time of error, it is possible to continue. It has an epoch-making effect that can be processed.

[0019]

EXAMPLES Specific examples of the present invention will be described below. FIG. 2 is a block diagram showing the configuration of an embodiment of a data processing device by a multiprocessor system for realizing the buffer storage error processing system according to the present invention. In FIG. 2, six central processing units (CPU0 to CPU5) 1 are connected to a main storage unit MSU2 via a storage control unit 3, and each central processing unit (CPU0 to CPU5) 1 shares the main storage unit MSU2. It is like this.

The main storage data in the main storage unit MSU2 is moved into a local buffer storage LBS16, which will be described later, for each central processing unit (CPU0 to CPU5) 1. For example, the central processing units CPU0 and CPU2 move the same data on the main memory into a local buffer storage LBS16, which will be described later, and are in a shared state. Also, the central processing unit
CPU1, CPU3, CPU4 move different data in main memory to local buffer storage LBS16,
In the exclusive state, the central processing unit CPU5 moves some data in the main memory into the local buffer storage LBS16 and is in the updated state. The central processing unit 1
May be one.

FIG. 3 shows the detailed structure of each central processing unit CPU 1 and its peripheral circuits. Central processing unit CPU1
Is composed of an instruction control unit IU11 for controlling the entire pipeline of the central processing unit CPU1 and an address calculation for accessing a buffer, an operation execution unit EU12, and a storage control unit SU13. Storage control unit SU13
Includes a store buffer 17, a local buffer storage LBS16 having a TAG1 unit 14, a TAG2 unit 15, and an LBS data unit 14b, an MCU order stack MOS 18, a moveout buffer 19, and an MCU order completion report buffer MRB20. At the time of the memory access, it is judged whether or not the necessary block exists on the LBS data section 14b, and if the target main memory data block exists here, in what state and where it exists. T to check if there is
The AG1 unit 14 is searched and the result is the instruction control unit IU.
Report to 11.

The TAG1 section 14 is accessed in synchronization with the main pipeline flowing in response to a request from the instruction control unit IU11, and manages entries. TAG2 part 15 is T
It has the same contents as the AG1 unit 14 and is accessed in synchronization with the TAG2 pipeline flowing in response to a request from the storage control unit MCU3, and is used for processing moveout requests (MO requests) and buffer invalidation requests (BI requests). The present embodiment is characterized in that the two TAG units 14 and 15 have the same contents, and perform processing at the time of a buffer storage error by referring to each other's information.

<Structure of Local Buffer Storage LBS 16> FIG. 4 shows a detailed structure of the local buffer storage LBS 16. Local buffer storage LBS
16 has an address register TLAR22, an address register BLAR23, an LDS TAG unit 14, an LBS data unit 14b, comparators 25 and 31, a tag matching unit 26, an align selector 27, and a word register 28.

FIG. 5 shows an example of the configuration of the TAG1 section 14. If the TAG1 unit 14 has a block size of 64 bytes, for example, and one associative level (WAY or way) has 64 entries, it has a capacity of 4 KB, so that eight associative levels have a capacity of 32 KB. become. This entry is evicted to the main storage device MSU2 from the one with the lowest reference frequency according to, for example, the LRU method.

FIG. 6 shows the contents of the entry of the TAG1 part 14. One entry is provided corresponding to a 64-byte block. One entry is a valid flag V indicating that the block is valid, its parity VP, and exclusive control indicating that the central processing unit CPU1 has the block exclusively to another central processing unit. A flag E and its parity EP, a change flag C indicating that the block has been stored and its parity CP, and a part of the address of the block on the main memory MSU2 (for example, bits 1 to 25 which are the addresses of the block). Of bits 20 to be used for reading TAG
Address bits (1 to 19) indicating the remainder after subtracting 25
And its parities P0 to P2.

The exclusive control flag E indicates whether or not writing to the block is possible, and the change flag C
Indicates whether the block has been unchanged or changed (updated) since it was moved into the buffer storage. Main memory
A copy of the block on MSU2 is on one line selected by address bits 20-25 of that block.
It is placed in any WAY. Which way is to be placed is determined by an LRU (Least Recently Used) algorithm or the like.

Each output of the TAG1 section 14 is input to eight comparators 25 provided for each WAY, and each comparator 25 has a conversion buffer TLBTLB2 from the TLAR22.
4, address bits 1 to 19 are input via the comparator 31. In addition, TAG2 part 15
Are configured with the same contents as the TAG1 unit 14 as shown in FIGS.

The LBS data portion 14b shown in FIG.
If a block corresponding to the G1 unit 14 exists, TA
Accessed by the address data registered in the G1 unit 14, the desired block is read, the data in the block is sent to the arithmetic control unit EU12, and the fact is reported to the instruction control unit IU11. <Operation of Each Circuit along the Main Pipeline> Next, FIG. 7 shows a flow of operation of each circuit along the main pipeline. The operation of each circuit of the main pipeline will be described with reference to FIGS. 6 and 7.

<T cycle (translation buffer and TAG access)> In the T cycle (translation buffer and TAG access), the logical address bits 20 to 25 of the address register TLAR22 are used to output from the TAG1 unit 14 to TAG1.
Read out. The valid flag V is ON (V = 1) from the TAG1 unit 14 and the address bits (1 to 19, P0
~ P2) searches for a matching WAY.

This will be described in detail below. The logical address from bit 1 to bit 31 sent from the instruction control unit IU11 is set in the TLAR22, and in parallel with this, bits 0 to 19 of the lower address are the line address for accessing the conversion buffer TLB24. Is input to the conversion buffer TLB24. In response to the input of this line address, two entries of primary and alternate are simultaneously read from the conversion buffer TLB 24, and the comparator 31 compares the read logical address with bits 1 to 12 of the EAR 22.

The TAG1 section 14 is an instruction control unit IU1.
It is accessed by bits 20 to 25 of the logical address sent from 1. In the virtual address method, when page address conversion in units of 4 Kbytes is adopted, lower bits 1 to 19 are subject to address conversion, but bits 20 to 31 have the same logical address and real address.

Therefore, bits 20 to 25 of the logical address sent from the instruction control unit IU11 are used as a real address to access the LBS data portion 14b. The TAG1 unit 14 is composed of eight associative levels from way 0 to way 7 in accordance with the LBS data portion 14b, and stored in ways 0 to 7 in response to the input of bits 20 to 25 of the logical address. 8
The individual real address information is read out.

Then, a comparator 2 provided with 8 × 2
5, the actual address read from the TAG1 unit 14 is compared with the actual address read from the conversion buffer TLB 24. Here, the comparator 25 performs a real address comparison process without waiting for the comparison result of the logical address of the conversion buffer TLB 24 executed by the comparator 31, thereby performing the search of the TAG1 unit 14 at high speed. To do.

<B cycle (buffer access)> In the B cycle (buffer access), the address register BL
Address read from AR23 (address register TLAR
(The same value as the address of 22), the LBS data section 14
Read Bb. Although all the WAYs are read at the same time, the align selector 27 inputs the comparison result of the comparator 31 and the comparison result of the comparator 25, and checks whether or not the comparison results are both satisfied. The logical address sent from the control unit IU11 is the TAG1 part 1
It specifies which way of 4 it exists.

Further, the align selector 27 selects a block of the LBS data section 14b output from the specified way, and executes a process of storing the selected block in the word register 28 according to the determined storage format. .. In this way, the instruction word / operand data of the main memory data stored in the word register 28 is sent to the instruction control unit IU11 and the operation control unit EU12, and is used as instruction decode or operation operand data.

Next, the description returns to the configuration shown in FIG. The instruction control unit IU11 reports to the operation execution unit EU12 that the data has been sent. Arithmetic execution unit
The EU 12 performs processing (calculation) such as addition, subtraction, multiplication and division based on the request from the instruction control unit IU 11, and sends the processed data to the store buffer STB 17. The registration in the local buffer storage LBS16 is performed via the store buffer STB17.

The MCU order stack MOS 18 stacks a plurality of move-out requests and buffer invalidation requests from the storage control unit MCU 3, and based on the requests, the TAG is stacked.
The storage control unit MCU3 accesses the second section 15 by an in-pointer or an out-pointer.
Controls the writing or retrieving of requests from.
The TAG2 part 15 is separate from the main pipeline.
In the order processing from the storage control unit MCU3, it is searched whether or not the target block exists on the LBS data section LBS14b (this is called the TAG2 pipeline). Therefore, the pipeline of TAG2 flows according to a request from the MCU order stack MOS18.

The move-out buffer MOB19 receives a move-out request from the storage control unit MCU3,
When the target block exists in the G2 unit 15, the LBS
The block is fetched from the data unit 16 and stored therein, and then moved out to the storage control unit MCU3. MCU
If the target block does not exist in the TAG2 unit 15, the order completion report buffer MRB20 fetches and stores the fact that there is no block, and further reports it to the storage control unit MCU2. When there is a buffer invalidation request from the main memory MSU2 and the TAG2 unit 15 is hit, the block is invalidated, and the MCU order completion report buffer
Report to the storage controller MCU2 through the MRB20.

<Operation of Control Unit of LBS TAG Unit of Embodiment> FIG. 8 shows the configuration of the control unit of the LBS TAG unit 1. The control unit in TAG1 has the same configuration as the control unit in TAG2, and only the configuration of the control unit in TAG1 is shown.
The control unit in TAG1 is configured as follows. The error detection unit 41 detects an error from the TAG1 unit 14, and supplies the detection output to the update unit 51, the exclusion unit 52, the sharing unit 53, and the invalidation unit 54.

The update flag detecting section 42 includes a TAG1 section 14
It is detected whether the change flag C set to "1" is "1", the exclusion flag detection unit 43 detects whether the exclusion flag set to the TAG1 unit 14 is "1", and the validity flag is detected. The detection unit 44 detects whether the valid flag set in the TAG1 unit 14 is “1”. In the store-in type buffer storage as in the embodiment, the valid flag V, the exclusive control flag E, and the change flag C entered in the buffer storage TAG1 unit 14 and TAG2 unit 15 are stored.
Depending on the value of, the state of the block in buffer storage is as follows. (A) The invalidation circuit 54 outputs the output of the error detection unit 41, the change flag C "0" from the update flag detection unit 42, the exclusion flag E "0" from the exclusion flag detection unit 43, and the validity flag detection unit 44. By inputting the valid flag V “0”,
The BI activation unit 35 for activating the block is activated.

That is, when all of the valid flag V, the exclusive control flag E, and the change flag C are "0", there is no data in the buffer storage (invalid state). (B) The exclusive circuit 52 outputs the output of the error detecting unit 41, the change flag C ″ 0 ″ from the update flag detecting unit 42, the exclusive flag E ″ 1 ″ from the exclusive flag detecting unit 43, and the valid flag detecting unit 44. By inputting the valid flag V "1",
The BI activation unit 35 is activated.

That is, when the valid flag V and the exclusive control flag E are "1" and the change flag C is "0", there is data in the buffer memory and the data is moved in. The state that is unchanged and can be changed by the local CPU in the system (exclusive state)
Becomes (C) The shared circuit 53 outputs the output of the error detection unit 41, the change flag C "0" from the update flag detection unit 42, the exclusion flag E "0" from the exclusion flag detection unit 43, and the validity flag detection unit 44. By inputting the valid flag V "1",
The BI activation unit 35 is activated.

That is, the valid flag V is "1",
When the exclusive control flag E and the change flag C are "0", data exists in the buffer storage, and the data remains unchanged when moved in and cannot be changed (shared state). (Non-exclusive state)). (D) The update circuit 51 outputs the output of the error detection unit 41, the change flag C "1" from the update flag detection unit 42, the exclusion flag E "1" from the exclusion flag detection unit 43, and the validity flag detection unit 44. By inputting the valid flag V "1",
The MO activation unit 33 for moving out the block is activated.

That is, when all of the valid flag V, the exclusive control flag E, and the change flag C are "1", data exists in the buffer memory and the data is updated by the store of the own CPU. It becomes the state (updated state). (In this case, the data is always held only by the own CPU). <Explanation of Moveout Operation when Error in TAG1 Portion> Next, moveout when an error occurs in the TAG1 portion will be described. FIG. 9 shows a time chart of the move-out operation when the TAG1 unit 14 of the central processing unit CPU51 has an error. Here, the central processing unit CPU5
1 is set as the exclusive flag E "1" and the change flag C "as the control information of the TAG1 unit 14 of the buffer storage device.
This is because "1" is registered and is in an updated state.

In the T cycle (EXT) of FIG. 9, when an EXT request is sent from the instruction control unit IU11, the TAG1 unit 14 is accessed by the value (00001000) of the address register TLAR22, and an error occurs in the TAG1 unit 14. Check if there is. If there is an error,
A TAG1 match and a TAG1 error are detected by the comparator 25 and the tag matching unit 26.

Here, for example, if there is an error in WAY 6, then the LMD signal rises in the R cycle and R
At the next timing (P cycle) of the (Result: result report) cycle, the request in which an error is detected is put in the error port and kept waiting (WAIT ID = LBS ERRO).
Along with R), a flag indicating that an error has occurred in the TAG1 unit 14 at the error port becomes valid (tag error valid V).

Therefore, in order to read out 64 bytes of data in a move-out request (MO) due to an error in the TAG1 unit 14 as a target of the move-out by the WAY 6, T cycle-B cycle-
The WAY number having an error is retained during the request, which is flowed only four times from the R cycle to the P cycle. On the other hand, T
When the WAY 6 having an error is read from the AG1 unit 14, the block is updated from the exclusive control flag E "1" and the change flag C "1" as the control information.
It is understood that the move-out must be performed and the latest contents must be reflected in the main storage device MSU2.

When the address (00 * E2000) of the address part to be moved out is read from the TAG1 part 14, it is found that the address has an error (* part in the address). On the other hand, at the same time when the TAG1 unit 14 is read, when the WAY 6 in the TAG2 having the same contents as the TAG1 is referenced (accessed by the value 00001000 of the address register TLAR2b), the address destroyed in the TAG1 unit 14 is correct (000E2000). You can see that it is registered.

Therefore, in order to move out the block, the storage controller MCU3 to the MCU order stack M
It is instructed to use the address registered in the TAG2 part 15 via the OS 18 (SELECT FOR BMOAR), and
The address is sent to MOAR. Move-out address register MOAR in move-out buffer MOS19
The address is the moveout data register MODR
The data read out by the address is set in the memory, and the data is subsequently moved out to the main memory MSU2.

In the T cycle of the last move-out request (MO4th), the TAG1 part 14 and the TAG are sent.
The valid flag V of the block of the second copy 15 is set to "0". In addition, move out request (MO1st)
Instruction control unit IU, which had been waiting for as soon as
The request from 11 is reflowed (INT), but no error is detected this time, and the request is accepted normally.

In addition, the data to be obtained has an error WA
If it is Y, the data has been invalidated (BI), and the move-in is performed again. <Explanation of move-out operation when an error occurs in the TAG2 section> FIG. 10 shows the TAG2 section 1 of the central processing unit CPU51.
5 shows a time chart of the move-out operation when there is an error in item 5. Request from storage controller MCU3 (S
RA) is output through the MCU order stack MOS 18, the TAG2 unit 15 is accessed by the value (00001000) of the address register TLAR22, and the TAG2 match and the TAG2 error are detected.

Here, if there is an error in WAY 6, for example, WAY 6 is targeted for moveout at the timing next to the R cycle, and a moveout request (MOE) due to a TAG2 error is issued from P cycle to T cycle to B cycle to R. After being cycled four times, the flag indicating that an error has occurred in the TAG2 unit 15 at the error port becomes valid (TAG2 ERROR VALID),
The WAY number having an error is held during the request.

On the other hand, WAY that has an error from TAG2
When 6 is read, the exclusive control flag E is set as the control information.
Since the block is updated from "1" and the change flag C from "1", the updating unit 51 of the buffer control unit 21 operates. Further, since the MO activation unit 33 is activated, it is understood that the move-out must be performed and the latest contents must be reflected in the main storage device MSU2.

When the address (00 * E2000) to be moved out is read, it is found that the address has an error (* part). At the same time as the TAG2 access, the WAY6 in the TAG1 having the same contents as the TAG2
(Accessed by TLAR), TAG2 part 1
The address destroyed in 5 is correct (000E2000)
You can see that it is registered in.

Therefore, in order to move out the block, it is instructed to use the address registered in the TAG1 section 14 (SELECT FOR BMOAR), and BMOAR
The address is sent to. Then, the move-out address register MOAR in the move-out buffer MOS19 is set with the address, and the move-out data register MODR is set with the data read by the address, and the data is thereafter stored in the main memory as an 8-byte store. Device MSU2
Be moved out.

In the T cycle of the last move-out request (MO4th), TAG1 part 14 and TAG2 are sent.
The valid flag of the block of the section 15 is set to OFF (V
= 1 → V = 0). Then, again the storage controller MCU
Request (SRA) from 3 is MCU order stack MOS
Although no error is detected this time, the request is normally accepted.

As described above, for example, the central processing unit
An error is detected when accessing the TAG1 unit 14 of the CPU 51, the error is an error in the address unit, and the block having the error sets the exclusive flag E to "1" and the change flag C to "1", that is, update. When it is in the state, the TAG2 part 15 is referred to by referring to the TAG2 part 15 as described above.
The move out can be performed using the normal address value in the.

An error is detected when the TAG2 section 15 is accessed, the error is an error in the address section, and the block having the error is in the updated state (E = 1, C).
= 1), refer to the TAG1 section 14 to see the TAG.
It is possible to move out the block using a normal address in the unit 14. (2) <Operation of Hardware when Buffer is Invalid in Embodiment> Next, the operation of hardware when the buffer is invalid in the embodiment will be described. FIG. 11 shows a processing flowchart when an error occurs in the address part of the TAG1 part in the embodiment.

In buffer storage employing the buffer storage error processing method, now in step S1, a request (EXT) from the instruction control unit IU11 is executed, and in step S2.
Then, when the TAG1 section 14 is accessed, step S3
Then, it is assumed that an error is detected in the address part. In that case, in step S5, the same block in the TAG2 section 15 is referred to. At this time, TAG 1 part 1
As control information of the block in step S4, step S6
Then, the valid flag V is "1", and in step S7,
It is assumed that the exclusive flag E is "1". Further, in step S8, it is assumed that the change flag C has no error and the block is unchanged (C = 0).

That is, like the TAG1 unit 14 of the central processing units CPU1, CPU3, and CPU4, the exclusive flag E "1" and the change flag "0" are registered, and the TAG1 unit of any of these central processing units is registered. This is the case where there is an error in the address part of 14. Then, in step S9, the exclusive unit 52 in the control unit in the TAG1 unit operates, it is found that the exclusive state is present, and the BI activation unit 35 is activated. Therefore, it is not necessary to move out the block, In S10, the buffer is invalidated.

That is, in such a case, the buffer invalidation request (BI) is sent once instead of performing the move out request (MO) four times in FIG.
In the T cycle of this request (step S11), TA
The valid flag V of the block of the G1 unit 14 and the TAG2 unit 15 is set to OFF, that is, V is "1" to "0".
Is changed to.

Similarly, when a request (SRA) from the storage controller MCU3 is issued through the MCU order stack MOS18 and an error is detected in the address part when the TAG2 part 15 is accessed, control of that block is performed. If there is no error in the exclusive flag E and the change flag C as the information part and it is unchanged (C is "0"), the block does not need to be moved out.

Therefore, move out request (MOE)
Instead, the buffer invalidation request (BI) is sent once, and in the T cycle of this request, the valid flag of the block of the TAG1 unit 14 and the TAG2 unit 15 is set to OFF, that is, the valid bit V changes from "1". "0"
Is changed to. As described above, when it is not necessary to move out, that is, when the block is not updated, error processing can be performed by simply invalidating the block.

In step S6, the valid flag V is set to "
If it is "0", the state becomes invalid in step S12, and the buffer is invalidated in step S10. Further, the valid flag V is "1" and the exclusive flag E is "."
0 ", that is, as in the case of the control information of the TAG1 unit 14 of the central processing units CPU0 and CPU2, CPU0 and CPU2
If and hold the same contents, step S13
Then, the sharing unit 53 in the control unit in the TAG1 operates,
It turns out to be a shared state. Further, the BI activation unit 33
Starts, and the buffer is invalidated in step S10.

Further, when the valid flag V is "1",
The exclusive flag E is "1" and the change flag C is "
If it is 1 ", as described with reference to FIG. 9, the update state is set in step S14, and the moveout is performed in step S15. (3) <Operation of hardware when buffer is invalid in embodiment> Next The operation of the hardware of the embodiment is described in Fig. 12. Fig. 12 shows a processing flowchart when an error occurs in the control information section in which the exclusive flag E of the TAG1 section 14 is registered.

In buffer storage, step S22
When an error is detected when the TAG1 unit 14 is accessed and the error occurs in the exclusive control flag E and the change flag C in the control information section in step S23,
It is unknown whether the block in error has been updated. However, for the sake of processing efficiency, the data of the block is sent to the move-out buffer MOB19 together with the normal address value in step S25. In step S26, the valid flag V is set to "0", and the block having the error in the TAG2 section 15 is referred to.

If no error is detected in the control information section of the TAG2 section 15 and the state of the block is the unchanged state (C = 0) in step S28, step S28
At 29, there is no need to reflect it in the main memory MSU2, that is, no move out. Therefore, by simply invalidating the block in the move-out buffer MOB19 and not sending the block to the main storage device 2,
Enables error handling.

Similarly, when an error is detected when accessing the TAG2 section 15, the error can be dealt with by the same processing as that of the TAG1 section 14.

[0069]

According to the present invention, the first tag unit accessed in the request from the central processing unit and the second tag unit having the same contents as the first tag unit accessed in the request from the storage control unit. In store-in type buffer storage that has a tag part, if an error is detected in one tag part, an error occurs by referring to the information in the other tag part and moving out to the main storage device. You can do the processing when you do.

Further, when there is no error in the exclusive flag E and the change flag C in each tag part and the block is in the unchanged state, error processing can be performed by simply invalidating the block. Also, the exclusive flag E of one tag part,
When an error is detected by the change flag C, even if the block is unchanged in the other tag access, the block at the time of error can be processed by simply invalidating the block.

As described above, paying attention to the fact that the two tag portions provided for use in synchronization with the pipeline of the independent processing device have the same contents, the tag portion used for the processing at the time of error causes the continuation. It has an epoch-making effect that can be processed.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a diagram illustrating one embodiment of a data processing system implementing the invention.

FIG. 3 is a configuration block diagram of an embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a local buffer storage LBS.

FIG. 5 is a diagram showing an example of the configuration of a TAG1 unit.

FIG. 6 is a configuration diagram of a buffer storage TAG unit in the embodiment.

FIG. 7 is a diagram showing an operation flow of each circuit along the main pipeline.

FIG. 8 is a diagram showing a configuration of an LBS TAG (inside) control unit in the embodiment.

FIG. 9 is a time chart of the move-out operation when an error occurs in the TAG1 part in the embodiment.

FIG. 10 is a time chart of a move-out operation when an error occurs in the TAG2 section in the embodiment.

FIG. 11 is a flow chart of processing when an error occurs in the address part of the TAG1 part in the embodiment.

FIG. 12 is a flowchart of a process when an error occurs in the control information of the TAG1 unit in the embodiment.

[Explanation of symbols]

 1-Central processing unit CPU 2-Main memory MSU 3-Storage controller MCU 11-Instruction control unit IU 12-Operation execution unit EU 13-Storage control unit SU 14-Tag 1 part 14b- LBS data section 15-TAG2 section 16-Local buffer storage LBS 17-Store buffer STB 18-MCU order stack MOS 19-Move-out buffer MOB 20-MCU order completion report buffer MRB 22-Address register TLAR 23 .. Address register BLAR 28. Word register OWR 41 .. Error detection unit PCHK 42 .. Update flag detection unit CCHK 43 .. Exclusive flag detection unit ECHK 44 .. Valid flag detection unit VCHK 33 .. MO (move out) ) Start-up unit 35 ... BI (buffer invalidation) start-up unit

Claims (5)

[Claims] 1. Data processing in which one or more central processing units (1) equipped with a set-associative store-in type buffer storage device (13) share one or more main storage devices (2). In the device, the buffer storage device (13) manages an entry and a data unit (14b) that is accessed by a request from the central processing unit (1) and registers data, and a first part that registers a block address. Tag part (14)
And a second tag unit (15) that is accessed by a request from another device and has the same contents as the first tag unit (14). The first tag unit (14) and the second tag unit (15) Tag part (15)
Is an exclusive flag (E) indicating that the block can be changed, a change flag (C) indicating that the block has been changed, and an address part indicating a part of the address on the main memory of the block. Has a parity bit independently for each of them, and if the change flag (C) is on when an error is detected in the first tag unit (14), the information of the second tag unit (15) is A buffer storage error processing method characterized by performing a moveout by using. 2. When the error is detected in the second tag section (15) and the change flag (C) is on, the move-out is performed by using the information of the first tag section (14). The buffer storage error processing method according to claim 1, wherein: 3. The information of the second tag section (15) is used when an error is detected in the first tag section (14) and the exclusive flag (E) change flag (C) is ON. 3. The buffer storage error processing method according to claim 1, wherein the move-out is performed as a result. 4. The first tag unit (14) or the second tag unit (15) has an error, the exclusion flag (E) has no error, and the exclusion flag (E) is off. 2. The buffer storage error processing method according to claim 1, wherein the block is invalidated when there is. 5. When an error occurs in the first tag section (14) and the error is an error of an exclusive flag (E) or a change flag (C), the second tag section ( In the access of 15), the exclusion flag (E)
Is OFF, the block is invalidated, and when an error occurs in the second tag unit (15), the error is the exclusive flag (E) or the change flag (C) error. The buffer storage according to claim 1, wherein in the access of the first tag unit (14), when the exclusion flag (E) is off, the block is invalidated. Error handling method.