JPH05267682A - Nonvolatile storage element, nonvolatile storage device using same, and driving method for nonvolatile storage device - Google Patents

Abstract

PURPOSE:To instantaneously write data in a switching transistor, by injecting electric charges in the whole part of a gate from the whole part of a channel region except an offset region below a side wall, at the time of writing the data. CONSTITUTION:FET's 20 are arranged in a matrix type on a P-type silicon substrate 30. The FET 20 has a gate 35 which is formed on a channel region 31 via a gate insulating film 34 for storing charges, and a side wall 36 which is formed on the source region 32 side of the gate 35 and has insulating properties. At the time of writing data, a high voltage is applied to the gate of the FET, a low voltage is applied to the source, and a writing voltage is applied to the drain. Thereby hot electrons are generated in the whole part of a channel region 31 except an offset region E below the side wall 36. Said hot electrons are made to tunnel through an ONO film 34 and injected in the whole part of the gate 35. Thus data are instantaneously written.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory element, a nonvolatile memory device using the same, and a method of driving the nonvolatile memory device.

[0002]

2. Description of the Related Art In recent years, with the development of the semiconductor industry, integration of a non-volatile memory device (hereinafter referred to as a non-volatile memory) is required. In order to meet this demand, it is possible to improve the degree of integration of the memory cell circuit. Therefore, a nonvolatile memory as shown in FIG. 6 has been proposed.

The nonvolatile memory shown in FIG. 6 has a plane orientation (1
00), the N-type impurity diffusion layer 3 serving as the source-drain region is formed on the surface layer portion of the P-type silicon substrate 1 with the channel region 2 interposed therebetween, and the floating gate 4 is floating above the channel region 2 in a floating state. Is provided, and a control gate (control gat
The electrode wiring 5 of e) is provided, and the floating gate 4 is surrounded by the gate insulating film 6.

FIG. 7 shows an equivalent circuit diagram of the nonvolatile memory of FIG. The non-volatile memory has a 1-transistor / 1-cell structure as shown in FIG. 7, and is a field effect transistor (hereinafter, referred to as F
ET (Field Effect Transistor)) 10A, 10
B, 10C, 10D, 10E, 10F, 10G, 10
Non-volatile memory elements (hereinafter referred to as non-volatile memory cells) 11A, 1 each including H, 10I, 10J, ...
1B, 11C, 11D, 11E, 11F, 11G, 11
H, 11I, 11J, ... Are arranged in a matrix with a predetermined capacity. In the following description, FET
10A, 10B, 10C, 10D, 10E, 10F, 1
When collectively referred to as 0G, 10H, 10I, 10J, ..., “FET10”, non-volatile memory cells 11A, 11B,
11C, 11D, 11E, 11F, 11G, 11H, 1
.. are collectively referred to as "nonvolatile memory cell 11".

Then, the FETs 10A, 10B, 10C,
10D, 10E and FETs 10F, 10G, 10H,
Gate line G for 10I and 10J control gates
L1 and GL2 are connected to each other, and adjacent FETs 10A, 10B and 1 are provided for each gate line GL1 and GL2.
0C, 10D, 10E and FETs 10F, 10G, 1
The sources and drains of 0H, 10I, and 10J are connected. Further, bit lines BL1, BL2, BL are connected to the sources and drains of the FETs 10A, 10E and 10F, 10J at the source-drain connection intermediate point and both ends.
3, BL4, BL5 and BL6 are respectively connected.

The operations of writing, reading and erasing information (data) in the nonvolatile memory will be described. <Write> For example, when writing data to the memory cell 11C, a high voltage H is applied to the gate line GL1 to which the memory cell 11C is connected, a high voltage H is applied to the bit line BL4, and a gate line GL2 is applied. And bit lines BL1, BL2, BL3, BL5, BL
The voltage L is applied to each of the six. Then, hot electrons are injected into the floating gate of the FET 10C in the memory cell 11C by the operating principle of the FET to be described later, and data writing is performed. <Read> In the same manner as at the time of writing, a voltage is applied, the sensing circuit connected to the outside detects whether the FET 10 in the memory cell 11 is in a conductive (ON) state, and writes in the memory cell 11. The read data. <Erase> For example, by irradiating ultraviolet rays, hot electrons of the floating gate of the FET 10 are used as hot carriers, and the gate insulating film is made into Fowler-Nordheim (Fow).
ler-Nordheim) Allows data to be erased on a line by letting it tunnel to the entire substrate.

The operating principle of the FET 10 is shown in FIG.
Will be described with reference to. FIG. 8 is a conceptual diagram showing the principle configuration of the FET. As shown in FIG. 8, the FET 10 includes a first gate insulating film (hereinafter, referred to as ONO (oxide) on the semiconductor substrate 1 so as to bridge the source region 3a and the drain region 3b.
a nitride oxide) film 6a is formed, a floating gate 4 is provided on the channel region 2 via an ONO film 6a, and a second gate is formed on the floating gate 4.
The gate insulating film 6b is formed, and the control gate 7 is provided on the floating gate 4 via the second gate insulating film 6b. That is, FET10 is M
It has an ONOS (metal oxide nitride oxide silicon) structure.

When a high voltage is applied to the control gate 7 and the drain at the time of writing and a saturated channel current is caused to flow between the source and the drain, a high electric field is generated in the pinch off region near the drain region 3b. The electrons accelerated by the ionization (impact io
electron, which has high energy, so-called hot electron is generated. On the other hand, a capacitance division voltage is generated in the floating gate 4, and hot electrons are injected into the floating gate 4 through the ONO film 6a by the capacitance division voltage.

[0009]

However, in the above non-volatile memory, the FACE (Flash Array) that writes data in an instant is used because the FET that stores the charge in the memory cell has the MONOS structure. Contactle
ss EPROM) was not applicable. This means that Figure 8
In the FET shown in (1), when writing, hot electrons are tunneled through the ONO film and injected into the floating gate. However, hot electrons are generated only near the drain, and the hot electrons tunnel through the ONO film. At this time, since some of the hot electrons are stored in Si ₃ N ₄ of the ONO film, it takes time for the hot electrons to move to the entire floating gate, and data cannot be written in an instant.

In view of the above, it is an object of the present invention to provide a non-volatile memory cell capable of instantaneously writing data, a non-volatile memory using the same, and a non-volatile memory driving method.

[0011]

A non-volatile memory element of the present invention for achieving the above object is a non-volatile memory element for storing information by accumulating charges in a switching transistor. Is a source region and a drain region formed on a semiconductor substrate with a channel region sandwiched between them, a gate insulating film for accumulating charges formed on the semiconductor substrate by bridging the source region and the drain region, and the channel. It has a gate provided on the region via a gate insulating film, and an insulating sidewall formed on the source region side of the gate.

In the nonvolatile memory device using the nonvolatile memory element, the nonvolatile memory elements are arranged in a matrix, and the gate lines are connected to the gates of the switching transistors of the nonvolatile memory elements, respectively. The source and drain of the adjacent switching transistors are connected for each gate line, and the bit line is connected to the source and drain of the switching transistor at each source-drain connection intermediate point and both ends.

In the above method for driving a non-volatile memory device, at the time of writing information, a high voltage is applied to a gate line connected to the non-volatile memory element for writing to select the non-volatile memory element for writing. Therefore, a low voltage is applied to the bit line connected to the source of the switching transistor of the nonvolatile memory element, and a low voltage is applied to the bit line connected to the drain, and when reading information, In order to apply a high voltage to the gate line connected to the nonvolatile memory element for reading and to select the nonvolatile memory element for reading, it is connected to the source of the switching transistor of the nonvolatile memory element. Apply a high voltage to the bit line and a low voltage to the bit line connected to the drain. Is applied, at the time of erasing, a high voltage is applied to the semiconductor substrate, it is characterized by applying a low voltage to the gate line connected to the nonvolatile memory element for erasing.

At the time of writing information by the above driving method, a potential difference is generated between the semiconductor substrate and the gate, and charges are generated in the entire channel region except the offset region below the sidewalls, and the charges tunnel through the gate insulating film. Then, it is injected into the entire gate, and information is written in the switching transistor. When the information is read, the depletion layer in the source region spreads to the offset region below the sidewall. At this time, if information is written in the switching transistor, a channel is formed, the switching transistor becomes conductive, and data is read.

Further, at the time of erasing information, the charges injected into the gate of the switching transistor tunnel and escape to the entire semiconductor substrate, so that the information is erased in a line at a time.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to FIGS. The electrical configuration of the non-volatile memory device (hereinafter referred to as non-volatile memory) according to the present embodiment will be described with reference to FIG. FIG. 1 is an equivalent circuit diagram of a nonvolatile memory according to an embodiment of the present invention.

The non-volatile memory of this embodiment has a one-transistor / one-cell structure as shown in FIG. 1, and stores information (data) by accumulating charges in the switching element. That is, a field effect transistor (hereinafter, FET (Field Eff
ect Transistor)) 20A, 20B, 20C, 2
0D, 20E, 20F, 20G, 20H, 20I, 20
Nonvolatile memory elements (hereinafter referred to as nonvolatile memory cells) 21A, 21B, 21C, 2 each having J ...
1D, 21E, 21F, 21G, 21H, 21I, 21
J ... are arranged in a matrix with a predetermined capacity. In the following description, FETs 20A, 20
B, 20C, 20D, 20E, 20F, 20G, 20
When collectively referring to H, 20I, 20J ..., "FET2
0 ", non-volatile memory cells 21A, 21B, 21C, 2
1D, 21E, 21F, 21G, 21H, 21I, 21
When J is collectively referred to as "nonvolatile memory cell 11"
Say.

The FETs 20A, 20B, 20C,
20D, 20E and FETs 20F, 20G, 20H,
Gate line G on the control gate of 20I and 20J
L1 and GL2 are connected to each other, and adjacent FETs 20A, 20B and 2 are provided for each gate line GL1 and GL2.
0C, 20D, 20E and FETs 20F, 20G, 2
The sources and drains of 0H, 20I, and 20J are connected. Further, bit lines BL1, BL2, BL are connected to the sources and drains of the FETs 20A, 20E and 20F, 20J at the source-drain connection intermediate point and both ends.
3, BL4, BL5 and BL6 are respectively connected.

The operation of writing, reading and erasing data in the nonvolatile memory will be described. <Write> Data is written serially for each gate line. For example, the nonvolatile memory cells 21A, 21B, 21 to which the gate line GL1 is connected
It is assumed that data is written in C, 21D, and 21E.
First, a high voltage H is applied to the gate line GL1,
In order to select the nonvolatile memory cell 21A, a low voltage L is applied to the bit line BL1 connected to the source of the FET 20A of the memory cell 21A, and a write voltage H is applied to the bit line BL2 connected to the drain. Alternatively, L is applied. At this time, FET2 described later
According to the operation principle of 0, when the write voltage H is applied to the bit line BL2, hot electrons are not generated in the channel region of the FET 20A, and the data “0” is written in the memory cell 21A, that is, the write operation. Is not done. On the other hand, when the write voltage L is applied to the bit line BL2, hot electrons are generated in the channel region of the FET 20A, the hot electrons are injected into the gate, and the data "1" is stored in the memory cell 21A.
Is written.

Next, the high voltage H is applied to the gate line GL1 as it is, and the nonvolatile memory cell 21
In order to select B, the FET 20 of the memory cell 21B concerned
A low voltage L is applied to the bit line BL2 connected to the source of B, and a write voltage H or L is applied to the bit line BL3 connected to the drain, so that data "0" is applied to the memory cell 21B. Or "1" is written.

Thereafter, nonvolatile memory cells 21C and 21C for writing are sequentially written in the direction of arrow X shown in FIG.
In order to select D and 21E, the memory cells 21C and 2E
Bit lines BL3, BL4, BL5 connected to the sources of FETs 20C, 20D, 20E of 1D, 21E
To the bit lines BL4, BL5, BL6 connected to the drains, respectively, and the write voltage H or L is applied to the memory cells 21C and 21C.
Data "0" or "1" is written to D and 21E, respectively.

A low voltage L is applied to the gate line GL2 and a high voltage H is applied to the bit lines connected to the unselected memory cells. <Read> For example, assume that the data stored in the nonvolatile memory cell 21A is read. In order to select the non-volatile memory cell 21A by applying the high voltage H to the gate line GL1 connected to the non-volatile memory cell 21A, the bit line BL1 connected to the source of the FET 20A of the memory cell 21A is selected. A high voltage H is applied to the bit line BL connected to the drain.
A low voltage is applied to each of the two. At this time, if data "1" is written in the memory cell 21A, F
The ET20A is electrically connected between the source and the drain to form a channel. By sensing this state by a decoder and a sense amplifier (not shown) connected to the outside, the data stored in the memory cell 21A is read. <Erase> Data is erased line by line for each gate line. For example, the nonvolatile memory cells 21A, 21B, 21C, 21 to which the gate line GL1 is connected
It is assumed that the data of D and 21E are erased. A high voltage H is applied to the semiconductor substrate and a low voltage L is applied to the gate line GL1. Then, the memory cells 21A,
FETs 20A and 20 of 21B, 21C, 21D and 21E
The hot electrons of the gates of B, 20C, 20D, and 20E tunnel through the Fowler-Nordheim tunnel and escape to the entire substrate.
The data stored in 21B, 21C, 21D, and 21E are erased on a line basis.

FIG. 2 shows the structure of the nonvolatile memory.
Will be described with reference to. FIG. 2 is a sectional perspective view showing the structure of the nonvolatile memory. The nonvolatile memory is, as shown in FIG. 2, formed on a P-type silicon substrate 30 having a plane orientation (100).
The FETs 20 are formed by being arranged in a matrix. The FET 20 is formed on the silicon substrate 30 by bridging the source region 32 and the drain region 33 with the N-type source region 32 and the N-type drain region 33 formed on the surface layer of the silicon substrate 30 with the channel region 31 interposed therebetween. Gate insulating film (hereinafter referred to as ONO (oxi
de nitride oxide) film 34 and a gate 35 provided on the channel region 31 with the ONO film 34 interposed therebetween.
And a sidewall 36 having an insulating property formed on the source region 32 side of the gate 35.
It has an S (metal oxide nitride oxide silicon) structure.

On the gate 35, a gate electrode wiring 37 made of polysilicon is laminated. Also,
The ONO film 34 is, for example, SiO ₂ from bottom to top.
20 to 30Å, Si ₃ N ₄ to 80Å, SiO ₂ to 50
Å LOCOS (localox) is formed between the ONO film 34 and the source region 32 and the drain region 33.
A thick field oxide film 38 formed by the ide of silicon method is interposed. Reference numeral 39 in FIG. 2 denotes a bit-line isolation area.

A method of manufacturing the FET 20 will be described with reference to FIG.
Will be described with reference to. Figure 3 shows the steps of the FET manufacturing method.
It is sectional drawing shown in order. First, as shown in Fig. 3 (a), heat
Oxidized to form SiO on the P-type silicon substrate 30. ₂Membrane 40
After the formation of SiO, as shown in FIG.₂On membrane 40
To Si₃N_FourThe film 41 is formed.

Next, as shown in FIG. 3 (c), the resist 42 is coated on the Si ₃ N ₄ film 41, leaving a transistor operation region, the Si ₃ N ₄ film 41, the resist 42 is removed SiO ₂ After exposing the membrane 40, for example,
nt) to dope phosphorus ions to form an N-type source region 32 and a channel region 3 on the surface layer portion of the P-type silicon substrate 30.
1 and N-type drain region 33 are formed.

Then, as shown in FIG. 3D, a SiO ₂ film 40 on the source region 32 and the drain region 33 is grown by a LOCOS method such as steam oxidation to form a thick field oxide film 38. At this time, the source region 3
2. The depth of the drain region 33 is eroded by the growth of the SiO ₂ film 40 and becomes shallow. After that, FIG.
As shown in (g), the ONO film 34 is formed on the silicon substrate 30 by bridging the source region 32 and the drain region 33.
To form. That is, in the step of FIG. ₃ (e), Si 3 N
After removing the _four films 41, a SiO ₂ film 43 is further laminated, for example, 20 to 30 Å, and the CVD (che
3) by depositing a Si ₃ N ₄ film 44 on the SiO ₂ film 43 by, for example, 150 Å.
In the step (g), for example, by steam oxidation, Si ₃ N _{4 is used.}
The upper layer of the film 44 is oxidized to form a SiO ₂ film on the Si ₃ N ₄ film 44 with a film thickness of 50 Å, for example. As a result, on the silicon substrate 30, from the bottom to the top, Si
An ONO film 34 in which O ₂ is ₂₀ to 30 Å, Si ₃ N ₄ is 80 Å, and SiO ₂ is 50 Å is sequentially formed.

Subsequently, as shown in FIG. 3H, after depositing polysilicon on the ONO film 34 by the CVD method,
A gate 35 is formed on the channel region 31 by cutting off part of the polysilicon by photolithography. Next, as shown in FIG. 3I, the gate 35 is formed by the CVD method.
An oxide having an insulating property is deposited on both sides (on the side of the source region 32 and the drain region 33) to form sidewalls 36. In this step, since the film thickness of the polysilicon 35 and the width of the sidewall 36 are substantially equal to each other, the width of the sidewall 36 can be controlled by controlling the film thickness of the polysilicon 35.

Then, as shown in FIG. 3J, a resist 45 is applied so as to cover the side wall 36 on the source region 32 side, and then the side wall 36 on the drain region 33 side is formed by anisotropic etching such as dry etching. Remove. Then, as shown in FIG. 3K, the resist 45 is removed, and then the gate 35 and the resist film shown in FIG.
Polysilicon is deposited so as to cover the sidewalls 36 on the source region 32 side, which are left in the step (j), to form the gate electrode wiring 37.

The operating principle of the FET 20 will be described with reference to FIGS. FIG. 4 is a diagram showing the operating principle of the FET, and FIG. 5 is an equivalent circuit diagram of the FET. Both figures (a) show the write state, and both figures (b) show the read state. <Writing> As shown in FIG. 5A, at the time of writing data, the high voltage H is applied to the gate of the FET 20, the low voltage L is applied to the source, and the write voltage H or L is applied to the drain. At this time, when the write voltage H is applied to the drain, a potential difference is generated between the source region 31 and the drain region 32, but as shown in FIG. 4A, the channel region 32 below the sidewall 36 is always offset. Since it is area E,
No hot electrons are generated in the channel region 31 and no data is written. On the other hand, when the write voltage L is applied to the drain, a potential difference is generated between the substrate 30 and the gate 35, and as shown in FIG. 4A, the entire channel region 31 excluding the offset region E below the sidewall 36. Hot electrons are generated, and these hot electrons tunnel through the ONO film 34 and are injected into the entire gate 35 to write data. <Reading> As shown in FIG. 5B, at the time of reading data, the high voltage H is applied to the gate of the FET 20, the high voltage H is applied to the source, and the low voltage L is applied to the drain. In this way, by applying a high voltage H to the source, the depletion layer 50 of the PN junction of the source region 31 spreads to the offset region E below the sidewall 36, as shown in FIG. 4B. At this time,
When charges are accumulated in the ONO film 34, that is, when data is written, a channel CH is formed and FE
T20 becomes conductive (ON) and data is read.

As described above, in the FET 20, since the sidewall 36 is formed on the source region 32 side of the gate 35 provided on the channel region 31 via the ONO film 34, the gate of the FET 20 is written at the time of writing data. By applying a high voltage H to the source, a low voltage L to the source, and a write voltage L to the drain, hot electrons are generated in the entire channel region 31 except the offset region E below the sidewalls 36, and the hot electrons are generated. To
The ONO film 34 can be tunneled and injected into the entire gate 35, and data can be written instantaneously.

Therefore, even if the FET 20 for accumulating charges in the nonvolatile memory cell 21 has a MONOS structure, it can be sufficiently applied to FACE (Flash Array Contactless EPROM). It should be noted that the present invention is not limited to the above embodiment, and many modifications and changes can be made within the scope of the present invention.

[0033]

As is apparent from the above description, according to the first to third aspects of the present invention, at the time of writing information, it is possible to inject charges from the entire channel region excluding the offset region below the sidewall into the entire gate. Therefore, information can be written in the switching transistor in an instant.

Therefore, there is an excellent effect that it can be sufficiently applied to FACE which needs to write information instantaneously.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of a nonvolatile memory device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional perspective view showing the structure of a nonvolatile memory device.

FIG. 3 is a cross-sectional view showing the method of manufacturing the switching transistor in the order of steps.

FIG. 4 is a diagram showing an operating principle of a switching transistor.

FIG. 5 is an equivalent circuit diagram of a switching transistor.

FIG. 6 is a cross-sectional perspective view showing the structure of a conventional nonvolatile memory device.

FIG. 7 is an equivalent circuit diagram of a nonvolatile memory device.

FIG. 8 is a conceptual diagram showing a principle configuration of a switching transistor.

[Explanation of symbols]

20, 20A, 20B, 20C, 20D, 20E, 20
F, 20G, 20H, 20I, 20J ... FETs 21, 21A, 21B, 21C, 21D, 21E, 21
F, 21G, 20H, 21I, 21J ... Nonvolatile memory cell 30 Silicon substrate 31 Channel region 32 Source region 33 Drain region 34 ONO film 35 Gate 36 Sidewall GL1, GL2 Gate line BL1, BL2, BL3, BL4, BL5 , BL6 bit line

Claims (3)

[Claims] 1. A nonvolatile memory element for storing information by accumulating charges in a switching transistor, wherein the switching transistor comprises a source region and a drain region formed on a semiconductor substrate with a channel region interposed therebetween, and the source. A gate insulating film for accumulating charges formed on the semiconductor substrate by bridging the region and the drain region; a gate provided on the channel region through the gate insulating film; and a gate region on the source region side of the gate. A non-volatile memory element having a formed insulating side wall. 2. The non-volatile memory element according to claim 1, wherein the non-volatile memory elements are arranged in a matrix form, a gate line is connected to a gate of the switching transistor of each non-volatile memory element, and the switching transistor is adjacent to each gate line. The source and drain are connected to each other, and bit lines are connected to the source and drain connection intermediate points and the source and drain of the switching transistors at both ends, respectively. 3. The non-volatile memory device according to claim 2, wherein at the time of writing information, a high voltage is applied to a gate line connected to the non-volatile memory element for writing to perform the non-volatile memory. To select the element,
A low voltage is applied to the bit line connected to the source of the switching transistor of the nonvolatile memory element,
A low voltage is applied to the bit line connected to the drain, and a high voltage is applied to the gate line connected to the non-volatile memory element to read when reading information. A selective memory element,
A high voltage is applied to the bit line connected to the source of the switching transistor of the nonvolatile memory element,
A low voltage is applied to each of the bit lines connected to the drain, and a high voltage is applied to the semiconductor substrate at the time of erasing, so that a low voltage is applied to the gate line connected to the nonvolatile memory element for erasing. A method for driving a nonvolatile memory device, which comprises applying a voltage.