JPH05268533A - Image sensor - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] To realize a high-speed, high-sensitivity, high S / N image sensor. A storage capacitor 30 connected to the gate terminals of horizontal amplification transistors 32 and 33, each of which has a large current driving capability for the bright output voltage and the dark output voltage of an amplification pixel in a selected row during a horizontal blanking period. , 31 and then, during the horizontal scanning period, the horizontal shift transistors 22 sequentially turn on the horizontal switch transistors 36 and 37 to amplify the bright output voltage and the dark output voltage of each storage capacitor by each horizontal amplification transistor. Then, it is connected to each horizontal signal line 38, 39 through each horizontal switch transistor. Further, the device parameters of the horizontal amplification transistor and the horizontal switch transistor, which are the bright output read paths, are matched with the device parameters of the horizontal amplification transistor and the horizontal switch transistor, which are the dark output read path, in the same column.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image sensor that amplifies optical information of an array of photoelectric conversion elements and reads signals at high speed and high S / N.

[0002]

2. Description of the Related Art A method for satisfying high sensitivity and high S / N of an image sensor is discussed in Japanese Patent Laid-Open No. 1-243675. As a configuration diagram of the above-mentioned conventional image sensor, it will be described with reference to FIG. Each pixel exists between the photodiode 1, the pixel amplification transistor 2 for amplifying the voltage applied from the photodiode 1, and the gates of the photodiode 1 and the pixel amplification transistor 2 and the vertical shift register 10 to the photogate line 25. It has a photogate transistor 26 that is scanned through the reset gate 4 and a reset transistor 4 for resetting the photodiode 1. The gate of the pixel amplification transistor 2 and the source of the reset transistor 4 are connected to the photodiode 1 via the photogate transistor 26, the drain of the pixel amplification transistor 2 and the reset transistor 4 are connected.
The drains of are connected to the vertical drain lines 12, respectively. The gate of the photogate transistor 26 is connected to the photogate line 25, and the source of the pixel amplification transistor 2 is connected to the vertical signal line 14. Here, the vertical gate line 13, the vertical drain line 12, and the photogate line 25 connected to the gate of the reset transistor 4 are selectively scanned by the vertical shift register 10. The vertical signal line 14 is dropped to the signal reset line 3 by the signal reset switch transistor 15 whose gate is controlled by the signal reset gate line 16, and also the storage capacitor gate lines 18 and 2.
8 is also connected to storage capacitors 19 and 29 via storage capacitor switch transistors 17 and 27 whose gates are controlled. The storage capacitors 19 and 29 are horizontal shift registers 22.
Is connected to the horizontal signal lines 23 and 24 by the horizontal switch transistor 20 which is selectively scanned through the horizontal gate line 21.

Next, the operation of the conventional example is described as follows. Signal charges are generated and stored in the photodiode 1 by the incidence of light. Within the horizontal blanking period, first, the vertical drain line 12 and the vertical gate line 13 of the row selected by the vertical shift register 10 are set to the “H” level, and at the same time, the signal reset gate line 16 and the signal reset line 3 are set to the “H” level. Setting the level resets the gate of the pixel amplification transistor 2 in the selected row. After that, the storage capacitor 19 of the source terminal output of the pixel amplification transistor 2 whose gate is reset is charged by turning on the storage capacitor switch transistor 17 for a certain period by the storage capacitor gate line 18. After that, the photogate line 26 is turned on to turn on the photogate transistor 26 so that the signal charge accumulated in the photodiode 1 is transferred to the pixel amplification transistor 2
The gate of the pixel amplification transistor 2 is read out to charge the storage capacitor 29 of the output of the source terminal of the pixel amplification transistor 2 by turning on the storage capacitor switch transistor 27 for a certain period by the storage capacitor gate line 28. Next, during the horizontal scanning period, when the horizontal shift register 22 sequentially turns on the horizontal switch transistors 20 via the horizontal gate lines 21,
Each storage capacitor 19, 29 is a horizontal switch transistor 20.
Will be connected to the horizontal signal lines 23 and 24 via the, and the bright output and the dark output due to the amplified signal charge accumulated in the storage capacitors 19 and 29 will be simultaneously output for each pixel at a later stage (not shown). It is obtained as the differential output of.

FIG. 6 is a generalized redrawing of the pixel section including the amplifier section of the circuit configuration diagram described with reference to FIG. 5, and a comparison between this conventional example and the present invention described below. And makes it easy to understand the parts that are essentially necessary for the discussion. In FIG. 6, the components having the same numbers as those in FIG. 5 are the same as those in FIG. Figure 6
5 is a transistor such as an amplification transistor, a reset transistor and a gate transistor acting as a switch.
The constituent elements of the pixel portion associated with each one photoelectric conversion element are collectively referred to as an amplification pixel 5 in the following. Vertical drain line 12 and vertical gate line 1 in FIG.
6, the photogate line 25 and the like are represented by 6 in FIG.
It is redrawn by two types of drive lines from the vertical shift register 10 designated by 7. That is, the content of the amplification pixel 5 is not limited to the corresponding portion in FIG. 5, but the photoelectric conversion element itself or the one obtained by amplifying the photoelectric conversion element output by the drive from the vertical shift register 10 is not passed through the follower output. However, the following argument is valid regardless of what is sequentially output to the vertical output line 14 for each same row. The drive line from the vertical shift register 10 necessary for driving each amplification pixel unit 5 is naturally shown in FIG.
The number is not limited to the two types 6 and 7 shown in the above, and may be one type or three or more types.

[0005]

In the above-mentioned conventional example, the reset noise of the gate of the pixel amplification transistor and the differential output at the time of light and dark are obtained to obtain the differential output. In order to suppress the low frequency component of the noise of the pixel amplification transistor and finally achieve a high S / N output, the potential of the vertical signal line in each column is charged to the storage capacitor, and this is charged to the horizontal signal line. The signal output is extracted by dividing the voltage with the capacity that it has. That is, the potential variation due to the optical information of the terminal potential of the photodiode is attenuated by the gate capacitance of the pixel amplification transistor having a relatively large capacitance value, and the attenuated follower output of the potential variation is determined by the capacitance of the horizontal signal line. It will be attenuated again. This becomes more serious as the number of pixels of the image sensor increases and the photocharge obtained by the photodiode decreases.

[0006]

The cause of the above problem is that the bright output and the dark output of the same pixel are routed through a single amplification path in order to avoid fixed pattern noise caused by the variation of the parameters generated for each amplification element. The signal form after the path is divided between the bright output and the dark output in the form of storing voltage information in the storage capacitor is read out only in the form of charge or the voltage value based on the charge. There is nothing. In order to solve the above problems, the present invention performs impedance conversion of a bright output voltage and a dark output voltage through a follower stage and then stores them in respective storage capacitors in order to avoid output reduction due to the influence of output line capacitance. A separate amplification transistor and its readout switch are provided for each, and for the purpose of suppressing fixed pattern noise, an amplification transistor for light output that belongs to the same column, and a readout switch and an amplification transistor for dark output. Further, a composite element composed of divided basic elements is used as an amplification transistor and a read switch so as to form a pair with a read switch so as to match the geometrical centers of gravity of their in-chip layouts.

[0007]

By using the means for solving the above problems, the bright output and the dark output can be amplified so that the output is not attenuated to improve the sensitivity, and the bright output for the same pixel can be amplified. It is possible to match the element parameters of the element of the stage and the element of the amplification stage of the dark output. That is, by matching the element parameters of the elements of the amplification stage with respect to the paired elements, the bright output and the dark output are amplified through different amplification paths to achieve high sensitivity. Also, suppression of fixed pattern noise is achieved,
By taking the differential output, it is possible to realize an image sensor that can obtain a video signal output with extremely high sensitivity and high S / N.

[0008]

1 is a block diagram of an image sensor according to a first embodiment of the present invention. Similar to those shown by the same numbers in FIG. 6, in this figure, 5 is an amplification pixel, 10 is a vertical shift register, 6 and 7 are both drive lines from the vertical shift register 10, 14 is a vertical signal line, and 22 is a horizontal line. It is a shift register. Each amplification pixel 5 has a vertical shift register 1 for each row.
0 are driven via common drive lines 6 and 7 and are connected to a common vertical signal line 14 for each column.
The vertical signal line 14 is connected to the storage capacitors 30 and 31 column by column via the storage capacitor switch transistors 8 and 9 driven by the storage capacitor gate lines 42 and 43, and the vertical signal driven by the signal reset gate line 41. It is grounded via the line reset switch transistor 11. The storage capacitors 30 and 31 are connected to the gates of the horizontal amplification transistors 32 and 33, respectively, and are also grounded via the storage capacitor clear transistors 34 and 35 driven by the storage capacitor clear gate line 44. Here, the storage capacitors 30 and 31 are composed only of parasitic capacitances such as the gate capacitors of the horizontal switch transistors 32 and 33, the source diffusion junction capacitors of the storage capacitor switch transistors 8 and 9, and the drain diffusion junction capacitors of the storage capacitor clear transistors 34 and 35. Alternatively, a capacity may be newly formed and added to the capacity. The horizontal amplification transistors 32 and 33 are respectively the horizontal shift register 22.
To horizontal signal lines 38 and 39 via horizontal switch transistors 36 and 37 driven by horizontal gate lines 40 from.

Next, the operation of the first embodiment shown in FIG. 1 will be described. In the amplification pixel 5, the signal charge generated in the photodiode or the phototransistor due to the incidence of light is stored. In the horizontal blanking period, first, before charging the storage capacitor of the bright output voltage described below, the vertical signal line reset switch transistor 11 driven by the signal reset gate line 41 resets the vertical signal line 14, and The storage capacitors 30 and 31 are reset by the storage capacitor clear transistors 34 and 35 driven by the storage capacitor clear gate line 44. Next, the drive lines 6 and 7 of the row selected by the vertical shift register 10
The output carrying the light information of the amplification pixel 5 of the selected row, that is, the bright output is output to the vertical signal line 14, and the storage capacitor gate line 42 is driven to turn on the storage capacitor switch transistor 8 for a certain period. The bright output voltage of the amplification pixel 5 in the selected row is stored in the storage capacitor 30 for each column.
After that, the vertical signal line reset switch transistor 11 driven by the signal reset gate line 41 resets the vertical signal line 14 again, and then the amplified pixels 5 in the selected row are reset by the drive lines 6 and 7 and the vertical signal is reset. The output voltage immediately after reset corresponding to the dark output is output to the line 14 and the storage capacitor gate line 4 is output.
The storage capacitor switch transistor 9 is turned on for a certain period by driving 3 and the dark output voltage of the amplification pixel 5 in the selected row is stored in the storage capacitor 31 for each column. As described above, the storage capacitors 30 and 31 in which the bright output voltage and the dark output voltage are stored are connected to the gate terminals of the horizontal amplification transistors 32 and 33 having a large current driving capability. Next, within the horizontal scanning period, the horizontal shift register 22
When the horizontal switch transistors 36 and 37 are sequentially turned on via the horizontal gate line 40, the bright output voltage and the dark output voltage stored in the storage capacitors 30 and 31 are amplified by the horizontal amplification transistors 32 and 33. , Its output is connected to the horizontal signal lines 38 and 39 through the horizontal switch transistors 36 and 37, and the bright output and the dark output due to the amplified signal charges accumulated in the storage capacitors 30 and 31 are amplified. It is simultaneously output for each pixel in the formed form. Although not shown in the figure, differential amplification of these two types of output signals can reduce spike noise and improve S / N.

According to this embodiment, the horizontal amplification transistors 32 and 33 and the horizontal switch transistors 36 and 37 are provided.
Is designed to have a large current drive capability. Therefore, when the bright and dark output voltages stored in the storage capacitors 30 and 31 are output to the horizontal signal lines 38 and 39 as voltage outputs, the follower outputs of the voltage values stored in the storage capacitors 30 and 31 are It is output to the horizontal signal lines 38 and 39 at high speed with almost no voltage value attenuation. That is, a high speed and high sensitivity image sensor is realized. When the bright and dark output voltages stored in the storage capacitors 30 and 31 are output as current outputs to the horizontal signal lines 38 and 39, the voltages stored in the storage capacitors 30 and 31 are applied to the horizontal amplification transistors 32 and 31. 33 and the horizontal switch transistors 36 and 37, the current amplification output is sent to the horizontal signal line 38 at high speed.
And 39, and a high-speed, high-sensitivity image sensor is realized.

In the above description, it was explained that the bright output voltage was stored in the storage capacitor prior to the dark output voltage being stored in the storage capacitor, but the same effect can be obtained by performing the storage operation in the reverse order. Although it has been illustrated and described that the effect can be obtained, and the potential at the time of resetting the vertical signal line 14 and the potential at the time of clearing the storage capacitors 30 and 31 are well ground potentials, they are set to a specific constant voltage value. Needless to say, it is okay. If the gate area is made large enough to provide high driving capability, the parasitic capacitance of the gates of the horizontal amplification transistors 32 and 33 becomes large, and it is not necessary to build a capacitive element especially for the storage capacitance. 2 lines 2 in Figure 1
Although it has been illustrated and described as a column area sensor, it can be easily extended to a larger number of rows and a larger number of columns and a linear sensor of 1 row and N columns.

By the way, in the above-mentioned invention example, when the output form to the horizontal signal lines 38 and 39 is the voltage output force, the matching of the element parameters of the horizontal amplification transistors 32 and 33 forming a pair in each column. Is required, and when the output form to the horizontal signal lines 38 and 39 is current output, the element parameter matching between the horizontal amplification transistors 32 and 33 forming a pair in each column and the horizontal It is a necessary condition that the device parameters of the switch transistors 36 and 37 are well matched. Poor matching of the parameters of these paired elements results in fixed pattern noise. Therefore, in order to improve the matching of the element parameters, each element is divided into a plurality of unit elements, and the unit elements of the elements to be paired are arranged to intersect with each other with respect to the mask layout. Match the geometric centroids of. Such an example is shown in FIG.
Shown in (b), (c) and (d). FIG. 2A is a simple circuit notation. When the two transistors illustrated here form a pair and the matching of the element parameters is required, each element is divided into, for example, two, and the two elements shown in FIG. As shown in b), it is composed of four unit elements. Figure 2
Terminals having the same symbol in (a) and (b) correspond to each other. The circuit diagram layout of each unit element in FIG. 2B almost corresponds to the geometrical layout in the in-chip layout. The actual semiconductor process has a process gradient,
Since the device parameter changes depending on the position within the chip or wafer, the device parameter depends on the local position within the semiconductor substrate on which the device itself is formed. Therefore, the device parameters are not sufficiently matched even between two devices adjacent to each other. P. R. Gray and R.G.
G. Co-authored by Meyer "Analysis and De"
sign of AnalogIntegrated
Circuits, 2nd ed. ", John Wi
ley & Sons, Inc. Pages 393 and 709 provide a method of eliminating the adverse effects of process gradients and taking device parameters between two devices. That is, as shown in FIG. 2B, elements whose terminals are completely connected in common are diagonally arranged, that is, geometric geometric centers of the elements which form a pair and whose element parameters are to be matched are arranged to be coincident with each other. The equivalent coordinates on which the element parameters of the composite element to which each terminal is commonly connected can be regarded as the barycentric coordinates of the coordinates of the unit element group forming the terminal, and the element parameters of the composite element can be considered to depend on the equivalent coordinates. Therefore, by matching the equivalent coordinates of the other composite elements with the equivalent coordinates, it is possible to improve the matching of the element parameters between the two composite elements. The element parameter of the composite element is the average value of the element parameters of the unit elements that compose it. FIG. 2B shows the case where each element is divided into two basic elements, but if the complexity is allowed in the design, if the configuration is made up of more divided basic elements, the consistency is further improved. .. FIG. 2 (c) corresponds to what is drawn by extracting the horizontal amplification transistors 32 and 33 and the horizontal switch transistors 36 and 37 which are paired in FIG. FIG. 2 (d) shows a diagram in which each element is divided into two in order to match the element parameters of the elements to be paired with respect to the horizontal amplification transistor and the horizontal switch transistor, respectively. 2C and 2D, terminals having the same symbol correspond to each other. The circuit diagram layout of each unit element in FIG. 2D substantially corresponds to the geometrical layout in the chip layout. Also in FIG. 2D, the basic elements forming each horizontal amplification transistor are diagonally arranged, that is, the geometrical centers of gravity of the horizontal amplification transistors to be paired with each other are aligned with each other to match the element parameters. Similarly, the device parameters of each horizontal switch transistor are also matched. In FIG. 2D, the case where each element is divided into two basic elements is shown, but if the complexity is allowed, if the configuration is made up of more divided basic elements, the matching is further improved. Since only the horizontal amplification transistor and the horizontal switch transistor for the light output and the horizontal amplification transistor and the horizontal switch transistor for the dark output that belong to the same column and make a pair, good matching is required. If the elements are divided into basic elements and the layout is performed as illustrated in FIGS. 2B and 2D, the requirement of matching the element parameters of the paired elements can be easily satisfied, and high speed and high speed can be achieved. An image sensor with high sensitivity and high S / N can be easily realized.

Next, FIG. 3 shows an image sensor in which the amplification pixel 5 of the first embodiment shown in FIG. 1 is specifically shown. In FIG. 3, reference numeral 45 denotes a photodiode, the anode of which is connected to the gate terminal of the pixel amplification transistor 49 and the reset transistor 50, and the other terminal of the reset transistor 50 is connected to the signal reset line 48 common to each pixel. The source of the pixel amplification transistor 49 is grounded via the amplification pixel output reset transistor 51, and is connected to the vertical signal line 14 via the vertical switch transistor 52. The other parts having the same numbers as those in FIG. 1 are the same as those already described, and thus the description thereof will be omitted.

Next, the operation of the image sensor of FIG. 3 will be described. The incidence of light causes the anode potential of the photodiode 45 to rise from the reset potential. Within the horizontal blanking period, the vertical signal line 14 is reset by the vertical signal line reset switch transistor 11 driven by the signal reset gate line 41, and the storage capacitors 30 and 31 are reset by the storage capacitor clear gate line 44. Storage capacitor clear transistor 34
And 35. Next, the storage capacitor of the bright output voltage is charged, that is, the vertical gate line 46 of the row selected by the vertical shift register 10 is set to the “H” level for a certain period of time, and the light of the photodiode 45 passes through the vertical switch transistor 52. The potential carrying information, that is, the follower output of the bright output voltage via the pixel amplification transistor 49 is output to the vertical signal line 14, and the storage capacitor switch transistor 8 is turned on for a certain period of time via the storage capacitor gate line 42 during this period. By doing so, the follower output that carries the optical information of the selected row is stored in the storage capacitor 30 for each column. Then, the reset transistor 50 and the amplified pixel output reset transistor 51 are turned on for a certain period of time through the vertical reset gate line 47 of the selected row, and the photodiode 45 is turned on.
And the output terminal of the pixel amplification transistor 49 are reset, and the vertical signal line 14 is reset again by the vertical signal line reset switch transistor 11 driven by the signal reset gate line 41. By turning on the vertical gate line 46 for a certain period of time, the output voltage corresponding to the anode potential of the photodiode 45 immediately after resetting, that is, the output at dark time is output via the vertical switch transistor 52.
9 to the vertical signal line 14 and, during this period, the storage capacitor switch transistor 9 is connected to the storage capacitor gate line 43.
The follower output, which is responsible for the dark output of the selected row, is stored in the storage capacitor 31 for each column by being turned on for a certain period via. Hereinafter, although the description is omitted because it is the same as the operation description in FIG. 1, a high-speed, high-sensitivity image sensor can be realized regardless of the output form of voltage output or current output.

In the configuration diagram shown in FIG. 3, the photodiode 45, the pixel amplification transistor 49, the reset transistor 50, and the amplified pixel output reset transistor 5 are used.
1. The pixel configuration including the vertical switch transistor 52 is illustrated as a specific circuit corresponding to the amplification pixel 5 illustrated in FIG. 1. However, the photodiode 1, the pixel amplification transistor 2, the reset transistor 4, and the photodiode 1 illustrated in FIG. The circuit configuration may be constituted by the photogate transistor 26, and various other configurations are conceivable. However, the present invention can be applied to any of them, and its effectiveness in high-speed and high-sensitivity reading is the same. large. Also in FIG. 3, as in the description of FIG. 1, paired horizontal amplification transistors 32 and 33 for amplifying and outputting a bright output and a dark output belonging to the same column, and a pair of horizontal switch transistors similarly paired. 36 and 37 are composed of a plurality of unit elements as already shown in FIG. 2 and are arranged such that the geometrical centers of gravity of the in-chip layouts coincide with each other, so that the element parameters of the paired transistors are matched. Needless to say, an image sensor with a higher S / N can be realized. Although FIG. 3 has been shown and described as an area sensor having two rows and two columns, it can be easily expanded to an area sensor having a larger number of rows and a larger number of columns or a linear sensor having a single row and N columns. When the linear sensor is used, the vertical switch transistor 52 and the vertical signal line reset switch transistor 11 can be omitted.

Next, a second embodiment will be described with reference to FIG. Example 2 shows a linear image sensor. In FIG. 4, the cathode of the photodiode 53 and the light-shielding photodiode 54 that is shielded so that light does not enter are commonly connected to the photodiode voltage line 57, while the anode of the photodiode 53 is connected to the horizontal amplification transistors 59a and 59b. It is connected to a signal reset voltage line 56 via a reset transistor 55 which is connected to and controlled to be turned on and off by a horizontal gate line 58 selected by a horizontal shift register 66, and the anode of the light shielding photodiode 54 is connected to horizontal amplification transistors 60a and 60b. And a reset transistor 5 which is connected to and is controlled to be turned on and off by a horizontal gate line 58 selected by a horizontal shift register 66 like the photodiode 53.
5 to the signal reset voltage line 56.
The terminals of the horizontal amplification transistors 59a and 59b and the horizontal amplification transistors 60a and 60b are commonly connected to each other. Also, horizontal switch transistors 61a and 61b
The horizontal switch transistors 62a and 62b also have their terminals commonly connected. One terminal of each of the horizontal amplification transistors 59a, 59b, 60a, 60b is connected to the amplification transistor voltage source 63, and the other terminal is connected to one terminal of each of the horizontal switch transistors 61a, 61b, 62a, 62b. And 61b, and the other terminals of 62a and 62b are connected to horizontal signal lines 64 and 65, respectively. The gates of the horizontal switch transistors 61a, 61b, 62a, and 62b are the horizontal gate lines 5 output from the horizontal shift register 66.
8 are commonly connected. Here, the horizontal amplification transistor 59
With respect to a, 59b, 60a, 60b and the horizontal switch transistors 61a, 61b, 62a, 62b, the arrangement shown in FIG. 4 corresponds to the geometrical arrangement in the element layout in the sensor chip, and the horizontal amplification transistors 59a in the same column. The geometric center of gravity of 59b and that of 59b are the same as those of the horizontal amplifying transistors 60a and 60b in the same column, and the geometric center of gravity of horizontal switch transistors 61a and 61b in the same column is also the horizontal switch in the same column. The geometric center of gravity of the transistors 62a and 62b is matched. Therefore, the element parameters of the horizontal amplification transistors and the horizontal switch transistors that form a pair of bright and dark outputs in the same column are well matched.

The operation of the second embodiment will be described. The horizontal shift register 66 controls on / off of the horizontal gate line 58 to reset the anodes of the photodiode 53 and the light-shielding photodiode 54 in the selected column via the reset transistor 55, and then the anode of the photodiode 53 is incident with light incidence. The potential rises. After a lapse of time corresponding to the storage time of the optical information, the horizontal switch transistor 61
When a, 61b, 62a, and 62b are turned on via the horizontal gate line 58, the amplified output of the anode voltage of the photodiode 53 and the light-shielding photodiode 54 of the selected column is output to the horizontal signal lines 64 and 65 at the bright time and It is output as a dark output, and a high S / N sensor output can be taken out by taking a differential output of both outputs. The anode potentials of the photodiode 53 and the light-shielding photodiode 54, which have been read when the read-selected column of the horizontal shift register 66 is shifted to the next column, are reset again to start a new optical information storage time.

In the embodiment of FIG. 4, the anode potentials of the photodiode and the light-shielding photodiode are directly received by the gate of the horizontal amplification transistor for simplicity, but the attenuation of the anode potential due to the presence of the gate capacitance of the horizontal amplification transistor is avoided. Therefore, a follower stage such as the pixel amplification transistor 49 and the amplification pixel output reset transistor 51 in FIG. 3 may be inserted in the middle of each of the photodiode and the light shielding photodiode. It is desirable that the follower stages have a basic element arrangement in which the photodiodes in the same row and the light-shielding photodiodes are paired so that the geometric centers of gravity of the photodiodes and the light-shielding photodiodes coincide with each other as shown in FIG.

[0019]

As is apparent from the above description, according to the present invention, when the optical information is output as the voltage output, the follower output of the voltage value accumulated in the storage capacitor is rapidly attenuated. Since it can be amplified and output with a low fixed pattern noise, a high-speed, high-sensitivity, high S / N image sensor can be realized. Further, in the case of outputting the optical information as a current output, a current amplified output of the voltage accumulated in the storage capacitor is output at a high speed and a high sensitivity with a low fixed pattern noise, and a high speed, a high sensitivity and a high S / N ratio. The image sensor of is realized. As described above, the industrial effect of the present invention is extremely large.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a first embodiment of an image sensor of the present invention.

FIG. 2 is a geometrical layout diagram of paired elements used in the present invention.

FIG. 3 is a more specific configuration diagram of Embodiment 1 of the image sensor of the present invention.

FIG. 4 is a configuration diagram of a second embodiment of the image sensor of the present invention.

FIG. 5 is a block diagram of a conventional image sensor.

6 is a more generalized configuration diagram of the conventional image sensor of FIG.

[Explanation of symbols]

1, 45, 53 Photodiode 5 Amplifying pixel 8, 9 Storage capacitance switch transistor 10 Vertical shift register 14 Vertical output line 22, 66 Horizontal shift register 32, 33, 59, 60 Horizontal amplifying transistor 20, 36, 37, 61, 62 Horizontal switch transistors 23, 24, 38, 39, 64, 65 Horizontal signal lines 40, 58 Horizontal gate lines

Claims (6)

[Claims] 1. A plurality of photoelectric conversion elements, which are arranged in an array and accumulate signal charges corresponding to an amount of incident light information, and a plurality of photoelectric conversion elements for amplifying the signal charges accumulated in each photoelectric conversion element. An image sensor comprising an amplification stage for each photoelectric conversion element and a reset unit for each photoelectric conversion element for resetting the photoelectric conversion element state to a state before exposure, For each column, a bright signal storage capacitor for accumulating the output carrying the optical information of the amplification stage for each photoelectric conversion element, its transfer switch, and a column for amplifying the bright signal storage capacitor voltage value. A bright signal amplification stage for each column, a read switch for each column for reading the output of the bright signal amplification stage for each column, a reset switch for resetting the potential of the bright signal storage capacitor, and the photoelectric conversion For each element A dark signal storage capacitor for storing output when carry no optical information after the reset of the amplifier stage,
A transfer switch, a dark signal amplification stage for each column for amplifying the dark signal storage capacitance voltage value, a read switch for each column for reading the dark signal amplification stage output for each column, It consists of a reset switch for resetting the potential of the dark signal storage capacitor and a reset switch for resetting the signal output line of the amplification stage for each photoelectric conversion element. The reading switch for each column for reading the same and the reading switch for each column for reading the dark signal amplification stage output for each column described above are simultaneously driven for each column, and the light for the same column is read. An image sensor characterized in that a time output and a dark output are independently obtained at the same time as differential outputs. 2. The image sensor according to claim 1, wherein
Each of the bright signal amplification stage amplification transistor of each column and the dark signal amplification stage amplification transistor of each column is a composite transistor including a plurality of basic amplification transistors connected in parallel. Geometrical center of gravity in the sensor chip layout of the bright signal amplifying transistor formed by the basic amplifying transistor and the dark signal amplifying transistor formed by a plurality of similar basic amplifying transistors belonging to the same column The image sensor, wherein the geometric center of gravity on the sensor chip layout is matched in each column. 3. The image sensor according to claim 2, wherein
A read switch for each column for reading the output of the bright signal amplification stage for each column and a read switch for each column for reading the output of the dark signal amplification stage for each column are each connected in parallel. It is a composite transistor composed of basic switch transistors, and the geometric center of gravity in the sensor chip layout of the bright signal amplification stage output read switch formed by the above plurality of basic switch transistors and the above-mentioned belonging to the same column Similarly, the image sensor characterized in that the geometrical center of gravity in the sensor chip layout of the dark signal amplification stage output read switch formed by a plurality of basic switch transistors is matched in each column. 4. A plurality of photoelectric conversion elements arranged in an array and accumulating signal charges according to an amount of incident light information, and dummy photoelectric conversion elements which are shielded from light and are in a dark equivalent state. Amplification stage for amplifying the signal charges accumulated in the photoelectric conversion element and the dummy photoelectric conversion element, and reset means for resetting the state of each of the photoelectric conversion element and the dummy photoelectric conversion element to the state before exposure. And a signal amplification stage for each column for amplifying an output voltage value carrying optical information of the amplification stage for each of the photoelectric conversion element and the dummy photoelectric conversion element, and a signal amplification stage for each column. A read switch for each column for reading the output, a reset switch for resetting the signal potential, and a reset switch for resetting the signal output line of the amplification stage for each photoelectric conversion element. The read switch for reading the signal amplification stage output for each column is driven simultaneously for the photoelectric conversion element and the dummy photoelectric conversion element for each column, and the bright output and the dark An image sensor characterized in that the output and the output are simultaneously obtained independently as differential outputs. 5. The image sensor according to claim 4,
Each of the amplification transistors of the signal amplification stage relating to each photoelectric conversion element and each dummy photoelectric conversion element of each column is a composite transistor composed of a plurality of basic amplification transistors connected in parallel, The formed photoelectric conversion element Geometric center of gravity in the sensor chip layout of the composite amplification transistor forming the signal amplification stage and the dummy photoelectric conversion formed by the same plurality of basic amplification transistors belonging to the same column An image sensor, characterized in that the geometric center of gravity of a composite amplifying transistor forming an element signal amplifying stage on the layout in the sensor chip is matched in each column. 6. The image sensor according to claim 5, wherein
A composite transistor composed of a plurality of basic switch transistors, each of which is connected in parallel with each of the readout switches for each column for reading out the signal amplification stage output for each column, and is a photoelectric transistor formed by the plurality of basic switch transistors. Conversion element Signal amplification stage output Geometric center of gravity in the sensor chip layout of the composite switch transistor forming the read switch and a dummy photoelectric conversion element formed by a plurality of basic switch transistors similar to the above belonging to the same column Matching the geometric center of gravity of the composite switch transistor forming the signal amplification stage output read switch in the sensor chip layout in each column,
Image sensor characterized by.