JPH05274255A - Bus arbitration circuit - Google Patents

Abstract

PURPOSE:To improve the processing speed of the whole system by instantly returning/outputting a permission signal to a processor generating a requirement signal excepting for when another processor is already using a shared bus. CONSTITUTION:The circuit is provided with a detection circuit C detecting that all the access requirement signals REQ1 to REQ3 outputted from respective input gate circuits A1 to A3 are true values and a conversion circuit D which is interposed into the signal line of an access permission signal outputted from an output gate circuit corresponding to one previously decided processor and moves in accordance with a detection signal DET from the detection circuit C to convert the permission signal into a true value. Then, when the other processors are not executing access to the shared bus, the permission signal is instantly sent out for each requirement signal inputted from three processors. When the other two requirement signals are inputted during the period of sending the permission signal to another processor, the priority of the requirement signal to output the permission signal next is decided in a tossing system.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention, in a computer system in which a plurality of processors and shared resources are connected to a shared bus, arbitrates access requests for shared resources via a shared bus that occur asynchronously in each processor. The present invention relates to a circuit, and particularly to a bus arbitration circuit applied when the number of processors is three.

[0002]

2. Description of the Related Art For example, a computer system has been put into practical use in which a single shared resource such as a storage device is shared by a plurality of processors so as to reduce the overall size of the system and improve the processing efficiency (Japanese Patent Publication No. 63- 4220). Among such computer systems, there are processing systems in which the processing contents are different for each processor, and only the processing result is written in the shared memory or necessary data is read from the shared memory and arithmetic processing is performed. Therefore, the time required for the arithmetic processing in each processor is different, and the writing / reading to / from the shared memory from each processor is random in terms of timing. It is asynchronous.

Therefore, it is necessary to arbitrate access requests generated by the processors so that the access requests generated by the processors do not conflict with each other so that a plurality of processors do not access the shared bus at one time.

FIG. 6 shows three processors 1a, 1b, 1c.
FIG. 3 is a diagram showing a computer system in which one shared resource 2 such as a memory is connected to one shared bus 3.
Then, in this computer system, for example, FIG.
The bus arbitration circuit 4 having the circuit configuration shown in FIG.

As shown in FIG. 7, the bus arbitration circuit 4 includes processors 1a, 1b. Constant cycle T for 1c
Permission signal ACK1, AC with respectively _A predetermined time width T _B
Outputs K2 and ACK3. Then, each processor 1a, 1
Request signals REQ1, REQ2, and REQ3 are sent from b and 1c to the bus arbitration circuit 4 as needed.

FIG. 9 is a circuit diagram showing the bus arbitration circuit 4. The counter 5 holds the count value with the 6 MHz clock signal output from the oscillator 6 only for the fixed time T _B corresponding to the cycle of the clock signal. Then, the values of the output terminals A and B are updated every time the fixed time T _B ends. The decoder 7 has output terminals A and B of the counter 5.
4 signals, depending on the logic of the two signals
The logic of a predetermined one of the two output terminals is output true. In addition, the permission signal ACK4 corresponding to the fourth [11] is not used. Therefore, in the actual circuit configuration of FIG. 9, the constant period T _A shown in FIG. 7 is four times the constant time T _B (T _A = 4T _B ).

On the other hand, the request signals REQ1, REQ2 and REQ3 output from the processors 1a, 1b and 1c are applied to the operation stop terminal of the counter 5 via the OR gates 8 and 9,
The operation of the counter 5 is stopped. At the same time, the input request signals REQ1, REQ2, and REQ3 are sent to the JK flip-flop 1
Latched to 0.

Therefore, each processor 1a, 1b, 1
As long as the request signals REQ1, REQ2, REQ3 are not output from c,
As shown in FIG. 7, each of the permission signals ACK1, ACK2, and ACK3 has a repetitive waveform with the constant period T _A and the constant time width T _B.

Then, each processor 1a, 1b, 1c
Is a permission signal for itself when an access request occurs
Within the L level period T _B where ACK1, ACK2, and ACK3 show true values,
The L level request signals REQ1, REQ2, REQ3 indicating the true value may be output. For example request signal REQ1 from the processor 1a at time t ₁ is the changes to the L level, the operation of the counter 5 for counting a predetermined time T _B of the permission signal ACK1 is stopped.
Thus, permission signals ACK1, even if a predetermined time at time t ₂ T
_{Even if B} has passed, the L level state is maintained.

Therefore, the processor 1a executes an access process to the shared bus 3 while the enable signal ACK1 continues to be in the L level state. Processor 1a is at time t
_{When the} predetermined access processing is completed in ₃ , the request signal
Return REQ1 to the original H level. As a result, the operation of the counter 5 is restarted, and the L-level permission signal ACK1 output to the processor 1a returns to the original H level. Then, the permission signal ACK2 for the next processor 1b changes to the L level for the fixed time T _B.

As described above, the bus arbitration circuit 4 sequentially outputs L to the processors 1a, 1b, 1c for a predetermined time T _B.
It sends level enable signals ACK1, ACK2, and ACK3. Then, each processor 1a, 1b, 1c has its own permission signal.
Only during the period when ACK1, ACK2, and ACK3 are output, it is possible to output the own request signals REQ1, REQ2, and REQ3.

Therefore, each processor 1a, 1b, 1
Since c does not output the request signals REQ1, REQ2, REQ3 at the same time, each processor 1a, 1b, 1c on the shared bus 3
There is no conflict in access processing from.

[0013]

However, the above-mentioned bus arbitration circuit 4 still has the following problems.

That is, each processor 1a. 1b, 1c
When an access request is generated in, it is necessary to execute the access processing for the access request as soon as possible. However, as shown in FIG. 7, a period that can output a request signal REQ to the bus arbitration circuit 4 is only the period T _B permission signal ACK1 to self is at the L level. Therefore, in FIG. 7, the output possible period of the request signal REQ is only 1/3 of the entire period. Therefore, even after another access request is issued, another processor is
Even a period of non-use, made to wait only a maximum 2T _B.

However, as described above, in the actual circuit shown in FIG. 9, it is the easiest to use a binary counter as the counter corresponding to the counter 5, so that the request signal REQ is output. The possible period is generally ½ of the total period. Therefore, when three processors are used, at least a quaternary counter is used, and the time when the actual request signal can be output is 1/4 of the entire period.

Further, as shown in FIG. 7, each permission signal ACK
1, ACK2, the L level period of ACK3 are adjacent temporally each other, it is assumed that the input request signal REQ to rise just before the after a period T _B has elapsed permission signal. in this case,
If a signal transmission time delay or the like occurs in the bus arbitration circuit 4, there is a concern that an erroneous operation may occur in which the operation of the counter is stopped while the permission signal ACK for the next processor is at L level.

In order to prevent this malfunction from occurring,
As shown in FIG. 8, the permission signal ACK1, ACK2, ACK3 L level period T _B further shortened dead time deliberately of (T _B -
T _C ). Therefore, the period during which each processor 1a, 1b, 1c can output the request signal REQ is further shortened.

Therefore, the processing efficiency of the computer system as a whole is significantly reduced.

Since an oscillator is indispensable for operating the counter, there is a concern that the clock signal output from the oscillator 6 becomes a radiated radio wave and adversely affects other electronic parts.

The present invention has been made in view of the above circumstances, and an enable signal is immediately issued to a processor which has issued a request signal except when another processor is already using the shared bus. By outputting and returning the data, the waiting time in each processor can be greatly reduced, the processing speed of the entire computer system can be improved, and other electronic devices can be constructed by using only simple logic circuit elements without using an oscillator. An object of the present invention is to provide a bus arbitration circuit capable of improving reliability while suppressing adverse effects on parts as much as possible.

[0021]

The present invention is incorporated in a computer system in which three processors and shared resources are connected to a shared bus and each processor asynchronously accesses the shared resources via the shared bus. , A bus arbitration circuit that arbitrates each access request generated in each processor and gives access permission to one processor.

In order to solve the above problems, in the bus arbitration circuit of the present invention, as shown in FIG. 1, if the access request signal from the processor is lower and the priority is lower than that of the self, as shown in FIG. A plurality of input gate circuits A1, A2, A3 are provided to pass an own request signal when an access permission signal for another designated processor is input, and this access permission signal is not a true value, and each processor is provided. Correspondingly, the access request signal that has passed through the input gate circuit corresponding to the processor concerned and the access request signal output from the input gate circuit corresponding to another processor designated as having a higher priority than itself are input. , When the access request signal is not a true value, the access request signal of its own is given as an access permission signal ACK1 to its own processor, A plurality of output gate circuits B1, B2, B3 for outputting as ACK2, ACK3 are provided.

Further, each input gate circuit A1, A2, A
3 is a detection circuit C for detecting that all access request signals REQ1, REQ2, REQ3 are true values, and an access permission signal signal output from an output gate circuit corresponding to one predetermined processor. And a conversion circuit D which is inserted in the path and responds to the detection signal DET from the detection circuit C to convert the permission signal into a true value.

[0024]

With the bus arbitration circuit configured as described above,
As can be judged from the pass condition of the access request signal (hereinafter abbreviated as a request signal) in each of the input gate circuits A1, A2, A3, the request signal output from each processor must have another priority lower than its own. There is a processor request signal. Also, each output gate circuit B1, B
2, so that it can be judged from the pass condition of the request signal in B3 that there is always a request signal of another processor having a higher priority than itself. Therefore, one particular request signal does not dominate over the other two request signals. The method of determining the priority order is the so-called "rock-paper-scissors system".

Therefore, assuming that the request signals of each processor occur at the same frequency, each request signal of the three processors has a fair priority as a whole. Therefore,
Only the access request of a particular processor is not prioritized. Moreover, when two requests occur at the same time, the mutual priorities are set, so that access requests do not conflict on the shared bus.

When an access request is generated, each processor can output a request signal to the bus arbitration circuit at the time of generation. Then, if the permission signal for the other processor is not output at this time point, an access permission signal (hereinafter abbreviated as a permission signal) is output to the processor.

If a permit signal for another processor is output at the time when one processor outputs a request signal to the bus arbitration circuit, this request signal is output by the input gate circuit or the output gate circuit. Be blocked. When the output permission signal is released, the own request signal passes through each gate circuit, is converted into a permission signal for itself, and is input to its own processor.

At the time when one processor outputs a request signal to the bus arbitration circuit, a permission signal for another one processor has been output and a request signal for another processor has already been output. In such a case, one's request signal is naturally blocked by one of the gate circuits. When the currently output permission signal is released, which of the request signals in the waiting state is released from the blocking state is determined by the priority of the two request signals in the waiting state.

When the request signals are simultaneously output from the three processors (so-called rock-paper-scissors and lanterns), the detection circuit outputs the detection signal DET and the conversion circuit outputs the permission signal to one processor. It

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a circuit diagram showing the bus arbitration circuit of the embodiment. The overall configuration of a computer system incorporating this bus arbitration circuit conforms to the conventional computer system shown in FIG.

In the circuit of this embodiment, the request signals REQ1 and REQ output from the processors 1a, 1b and 1b, respectively.
2) The mutual priority in REQ3 is set as shown in Eq. (1).

REQ1> REQ3, REQ3> REQ2, REQ2> REQ1 (1) Further, from this bus arbitration circuit, each processor 1a, 1b,
Permission signals ACK1, ACK2, and ACK3 are transmitted to 1c, respectively. Then, each request signal REQ1, REQ2, REQ3 and each permission signal ACK1, ACK2, ACK3 operate in negative logic, and become a true value when each signal becomes L level.

In FIG. 2, the request signal REQ1 sent from the processor 1a has its signal level inverted by an inverter 21a and is input to one input terminal of an input gate circuit 22a composed of, for example, a NAND gate. The request signal Ra that has passed through the input gate circuit 22a is level-inverted by the inverter 23a, and then input to one input terminal of the output gate circuit 24a composed of, for example, a NAND gate. The permission signal Aa output from the output gate circuit 24a is passed through the conversion circuit 25 configured by, for example, an OR gate, and the protection gate circuit 26a configured by a NAND gate.
Is input to one of the input terminals. Then, the final permission signal ACK1 is sent from the protection gate circuit 26a to the processor 1a.

Similarly, the signal level of the request signal REQ2 sent from the processor 1b is inverted by the inverter 21b and input to one input terminal of the input gate circuit 22b. Request signal R passed through the input gate circuit 22b
The level of b is inverted by the inverter 23b and then input to one input terminal of the output gate circuit 24b. The permission signal Ab output from the output gate circuit 24b is input to one input terminal of the protection gate circuit 26b. Then, the final permission signal ACK2 is sent from the protection gate circuit 26b to the processor 1b.

Further, the request signal REQ3 sent from the processor 1c is inverted in signal level by the inverter 21c and input to one input terminal of the input gate circuit 22c. Request signal R passed through the input gate circuit 22c
The level of c is inverted by the inverter 23c and then input to one input terminal of the output gate circuit 24c. The permission signal Ac output from the output gate circuit 24c is input to one input terminal of the protection gate circuit 26c. Then, the final permission signal ACK3 is sent from the protection gate circuit 26c to the processor 1c.

The enable signal Ac output from the output gate circuit 24c corresponding to the processor 1c having a lower priority than the processor 1a is input to the other input terminal of the input gate circuit 22a corresponding to the processor 1a. .. Therefore, the request signal REQ1 input from the processor 1a while the permission signal Ac is other than the true value of the H level passes through the input gate circuit 22a as it is and becomes the L level request signal Aa.

The request signal Rb passed through the input gate circuit 22b corresponding to the processor 1b having a higher priority than the processor 1a is input to the other input terminal of the output gate circuit 24a corresponding to the processor 1a. Therefore, the request signal Ra corresponding to the processor 1a passes through the output gate circuit 24a only during the H level period when the request signal Rb of the processor 1b is not a true value and becomes the enable signal Aa.

Therefore, the request signal REQ1 of the processor 1a
Is output as the permission signal Aa when both the permission signal Ac for the processor 1c and the request signal Rb from the processor 1b are input within a period that is not a true value.

Similarly, the enable signal Aa output from the output gate circuit 24a corresponding to the processor 1a having a lower priority than the processor 1b is input to the other input terminal of the input gate circuit 22b corresponding to the processor 1b. It Further, the request signal Rc passed through the input gate circuit 22c corresponding to the processor 1c having a higher priority than the processor 1b is input to the other input terminal of the output gate circuit 24b corresponding to the processor 1b. Therefore, the request signal REQ2 of the processor 1b is output as the enable signal Ab when both the enable signal Aa for the processor 1a and the request signal Rc from the processor 1c are input within a period that is not a true value.

Similarly, the permission signal Ab output from the output gate circuit 24b corresponding to the processor 1b having a lower priority than the processor 1c is input to the other input terminal of the input gate circuit 22c corresponding to the processor 1c. It Further, the request signal Ra passed through the input gate circuit 22a corresponding to the processor 1a having a higher priority than the processor 1c is input to the other input terminal of the output gate circuit 24c corresponding to the processor 1c. Therefore, the request signal REQ3 of the processor 1c is output as the enable signal Ab when both the enable signal Ab for the processor 1b and the request signal Ra from the processor 1a are input within a period that is not a true value. Further, the request signals Ra, Rb, Rc output from the respective input gate circuits 22a, 22b, 22c are transmitted to the inverters 23a, 23b. 23
It is input to the detection circuit 27 configured by a NAND gate through c. The detection circuit 27 receives all the request signals Ra and R.
Only when b and Rc indicate the true L level, the L level detection signal DET is output. Therefore, the conversion circuit 25 outputs the L-level permission signal Aaa to the next protection gate circuit 26a regardless of whether the permission signal Aa output from the output gate circuit 24a is true or false.

Two other permission signals Aa and Ac and Aa and Ab are input to the other ends of the protection gates 26b and 26c through AND gates 28b and 28c, respectively. In addition, the protection gate circuit 2 for the processor 1a
The other two permission signals Ab and Ac are directly input to the other input terminal of 6a. That is, in each of the protection gate circuits 26a, 26b, and 26c, when the enable signal is switched and output to another processor, the enable signal is transmitted to a plurality of processors due to the difference in the time response characteristic in each gate circuit. To prevent them from being output at the same time.

Next, the specific operation of the bus arbitration circuit shown in FIG. 2 will be described with reference to the time chart shown in FIG.

First, in the section T1, the request signal REQ3 is first input from the processor 1c, then the request signal REQ1 of the processor 1a is input, and finally the request signal REQ2 of the processor 1b is input. Then, it is assumed that the first request signal REQ3 is canceled at the end of this section T1.

First, in a state where the request signals REQ1 to REQ3 are not input at all, the output gate circuits 24a to 24a.
The permission signals Aa to Ac output from 24c are H level indicating a false value. In addition, each input gate circuit 22a-22
The request signals Aa to Ac output from c are also at the H level indicating a false value.

When the request signal REQ3 is first input from the processor 1c in this state, the request signal passes through the input gate circuit 22c and the output gate circuit 24c as it is and is sent to the processor 1c as a permission signal ACK3. ..

Next, when the request signal REQ1 is input from the processor 1a while the permission signal ACK3 is output, the processor 1c is connected to the other input terminal of the input gate circuit 22a.
The request signal REQ1 cannot pass through the input gate circuit 22a because the L-level permission signal Ac indicating the true value is input from the output gate circuit 24c. Therefore, the permission signal ACK1 in response to the request signal REQ1 is not output.

Further, when the request signal REQ2 is input from the processor 1b while the request signals REQ3 and REQ1 are output, the request signal REQ2 passes through the input gate circuit 22b. However, the L-level request signal Rc indicating the true value from the input gate circuit 22c of the processor 1c receiving the permission signal ACK3 is input to the other input terminal of the output gate circuit 24b. Therefore, the permission signal ACK2 for the processor 1b is not output.

Next, the operation of the section T2 will be described. Section T2
When the request signal REQ3 of the processor 1c is canceled, the request signal Rc of the input gate circuit 22c also becomes a false value and the output gate circuit 24 for the processor 1b is started.
b becomes conductive. Therefore, the permission signal ACK2 for the processor 1b is output via the output gate circuit 24b and the protection gate circuit 26b. It should be noted that the output gate circuit 24a has a true request signal R from the input gate circuit 22b.
Since b is still input, the permission signal ACK1 for the processor 1a is not yet output. When the request signal REQ3 is input again from the processor 1c while the permission signal ACK2 for the processor 1b is output, the request signal REQ3 is naturally input.
The permission signal ACK3 for REQ3 is not output.

When the section T2 ends and the section T3 starts and the request signal REQ2 for the processor 1b is released, the request signal Rb input to the other of the output gate circuits 24a corresponding to the processor 1a is at the H level. Therefore, the output gate circuit 24a outputs the L-level permission signal Aa. The permission signal Aa indicating the true value passes through the next conversion circuit 25 to be converted into a new permission signal Aaa, and is sent to the processor 1a as the permission signal ACK1 via the protection gate circuit 26a.

When the section T3 ends and the section T4 starts and the request signal REQ1 for the processor 1a is released, the permission signal ACK3 for the previously input request signal REQ3 of the processor 1c is output.

When the section T4 ends and the section T5 starts and the request signal REQ3 to the processor 1c is released, the request signals REQ1 to REQ1 to REP1 of all the processors 1a to 1b are released.
When the output processing of the respective permission signals ACK1 to ACK3 for REQ3 is completed, the state of waiting for the input of the next request signals REQ1 to REQ3 is entered.

When request signals REQ1 to REQ3 are simultaneously input from the processors 1a to 1c at the start of the section T6, true value request signals Ra, Rb and Rc are simultaneously output from the input gate circuits 22a to 22c. Is output. Therefore, the detection circuit 27 is established, and the L-level detection signal DE
Output T. As a result, the conversion circuit 25 forces L
The level permission signal Aaa is output. Then, the protection gate circuit 26a sends a permission signal ACK1 to the processor 1a.
Is sent.

When the section T6 is finished and the section T7 is started and the request signal REQ1 for the processor 1a is released, the request signal REQ3 having the highest priority among the remaining two request signals REQ2 and REQ3 is dealt with. Permission signal ACK3 is output.

When the request signal REQ3 of the processor 1c is released, the section T7 ends and the section T8 starts, the permission signal ACK2 for the remaining one request signal REQ2 is output.

When the request signal REQ2 to the processor 1b is released and the section T9 starts, each of the processors 1a to 1a is restarted.
The system waits for the input of request signals REQ1, REQ2, and REQ3 from 1c.

FIG. 4 shows one processor 1 in a computer system incorporating the bus arbitration circuit shown in FIG.
It is a block diagram which shows schematic structure of a. In addition, FIG.
It is a time chart which shows the access process with respect to the shared bus 3 which this processor 1a performs.

When the CPU 34 needs to access each of the components 2a, 2b, ..., 2c connected to the shared bus 3, the bus arbitration circuit 3 via the address decoder 35.
The request signal REQ1 is output to 0. The permission signal ACK1 transmitted from the bus arbitration circuit 30 is input to the control terminal of the driver / receiver circuit 31 for the shared bus 3 in the processor 1a and is also transmitted to the ready signal generation circuit 32. The ready signal generating circuit 32 includes components 2a, 2b, ...
In consideration of the setup time of 2c and the delay time at each gate, a reticle signal indicating that the access is executable is sent to the CPU 34 after a predetermined time. When the CPU 34 receives the ready signal, the CPU bus 36 and the driver /
The shared bus 3 is accessed via the receiver circuit 31.

According to the bus arbitration circuit thus configured, as shown in the time chart of FIG. 3, when an access request is generated in each of the processors 1a to 1c, there is no waiting time, and the bus arbitration circuit is present at that time. Request signals REQ1 to REQ3 are output to 30. Then, if another processor is not accessing the shared bus at the time of outputting the request signal, the access is immediately performed.

Therefore, as shown in the conventional time chart shown in FIG. 7 or FIG. 8, it is not necessary to wait until the fixed period T _B allocated to itself arrives. Therefore, the waiting time in the entire computer system is significantly reduced, so that it is possible to increase the processing speed of the entire system. Moreover, the request signals REQ1 to REQ3 output from the processors 1a to 1c are connected to each other. Priority is (1)
As shown in the equation, one particular request signal is
It does not dominate the individual request signals. The method of determining the priority order is the so-called "rock-paper-scissors system".

REQ1> REQ3, REQ3> REQ2, REQ2> REQ1 (1) Therefore, the request signals REQ1 to REQ3 of the processors 1a to 1c
, The request signals REQ1 to REQ3 of the three processors 1a to 1c have fair priority as a whole. Therefore, only the demands of a particular processor are not prioritized. Moreover, when an access request is issued from two other processors while one processor is executing the access processing, the mutual priorities are set as in equation (1). When the access processing is completed, the access request with the higher priority is executed first. Therefore, access requests do not conflict on the shared bus 3.

Further, when the request signals REQ1 to REQ3 are simultaneously output from the processors 1a to 1c, the detection circuit 2
A detection signal DET is output from 7 and a permission signal is sent from the conversion circuit 25 to one predetermined processor 1a. Therefore, even if each request signal REQ1 to REQ3
Even if is output, the access operation can be surely executed. Therefore, the reliability of the entire bus arbitration circuit can be improved.

Further, as shown in FIG. 2, the entire circuit can be constructed by a logic circuit IC such as an inexpensive PLD (Progrmable Logic Array). Therefore, since the entire bus arbitration circuit can be realized by one IC element, the manufacturing cost can be significantly reduced.

Furthermore, since an oscillator is not used in this bus arbitration circuit as in the conventional circuit shown in FIG. 9, the clock signal output from the oscillator may adversely affect other electronic components. To be prevented. Therefore, the reliability of the entire bus arbitration circuit can be further improved.

In the embodiment, the case where the present invention is applied to a computer system composed of three processors is shown. However, even in a computer system in which one processor is removed, devices having the same circuit configuration can be used as they are.

[0066]

As described above, according to the bus arbitration circuit of the present invention, the request signals input from the three processors are immediately notified when another processor does not access the shared bus. Send a permission signal for the request signal. In addition, when another two request signals are input during the transmission period of the permission signal to another processor,
Next, the priority order of the request signal for outputting the permission signal is determined by the “paper-scissors system”. Therefore, the waiting time in each processor can be significantly reduced, and the processing speed of the entire computer system can be improved. Further, without using an oscillator, the hardware can be configured only with simple logic circuit elements, adverse effects on other electronic components can be suppressed as much as possible, and reliability can be improved.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing a bus arbitration circuit of the present invention,

FIG. 2 is a circuit diagram showing a bus arbitration circuit according to an embodiment of the present invention,

FIG. 3 is a time chart showing the operation of the circuit of the embodiment.

FIG. 4 is a block diagram showing an internal structure of one processor of a computer system incorporating the circuit of the embodiment.

FIG. 5 is a time chart showing the operation of the processor,

FIG. 6 is a schematic configuration diagram showing a general computer system,

FIG. 7 is a time chart showing the operation of a conventional bus arbitration circuit,

FIG. 8 is a time chart showing the operation of another conventional bus arbitration circuit,

FIG. 9 is a circuit diagram showing a schematic configuration of the conventional bus arbitration circuit.

[Explanation of symbols]

1a, 1b, 1c ... Processor, 2 ... Shared resource, 3 ... Shared bus, 22a, 22b, 22c ... Input gate circuit, 2
4a, 24b, 24c ... Output gate circuit, 25 ... Conversion circuit, 26a, 26b, 26c ... Protection gate circuit, 27 ...
Detection circuit, REQ1 to REQ3 ... Request signal, ACK1 to ACK3 ... Enable signal, DET ... Detection signal.

Claims (1)

[Claims] 1. Three processors (1a to 1c) and a shared resource (2) are connected to a shared bus (3), and each processor asynchronously accesses the shared resource via the shared bus. A bus arbitration circuit incorporated in a computer system that arbitrates each access request generated in each processor and gives access permission to one processor. A request signal and an access permission signal for another one of the processors designated as lower priority than itself are input, and a plurality of input gates that pass the access request signal of the self when the access permission signal is not a true value. Circuits (22a to 22c) and an input gate circuit provided corresponding to each processor and corresponding to the processor. And the access request signal output from the input gate circuit corresponding to another one of the processors designated as having a higher priority than itself is input, and the access request signal of the other processor is a true value. If not, a plurality of output gate circuits (24a to 24c) that output their own access request signals as access permission signals to their own processors, and the access request signals output from the respective input gate circuits are all true values. And a detection circuit (27) for detecting the fact that it is inserted in a signal path of an access permission signal output from a predetermined output gate circuit corresponding to one processor, and responds to the detection signal from the detection circuit. A conversion circuit for converting the access permission signal to a true value (2
5) Bus arbitration circuit with and.