JPH05316387A - Synchronizing signal detection circuit - Google Patents

Abstract

PURPOSE:To considerably decrease the disturbance in a display picture by switching a detected output of 1st and 2nd synchronization detection sections with a switching signal outputted from a switching signal output section. CONSTITUTION:A comparator circuit 42 compares a position of a preceding synchronizing signal with that of a current synchronizing signal and detects any discontinuous portion, then a flip-flop circuit 44 applies switching control to a switch 28 to switch to raw data from a synchronizing signal detection circuit 27 in place of a synchronization output from a flywheel circuit 13, and a horizontal/frame counter 24 is forcibly reset, and when the flywheel circuit 13 is locked, lets it be an output of the flywheel circuit 13. The method is stable against a transmission error due to noise or the like, and a synchronizing signal coincident with input information is obtained at a high speed for a switched source data. Thus, when the detection circuit is applied to a VTR or the like, the disturbance of a displayed picture is remarkably decreased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sync signal detection circuit suitable for application to, for example, a beta type digital VTR or the like.

[0002]

2. Description of the Related Art Conventionally, various digital VTRs have been put into practical use in various formats in conformity with the 4: 2: 2 digital VTR format standardized based on the digital TV standard for studios by CCIR recommendation. Various formats such as D1 and D2 are widely used in commercial VTRs.

FIG. 4 shows a 4: 2: 2 standard digital VTR.
7 shows a system for recording a signal, which will be described below.

In the system shown in FIG. 4, for example, a synchronizing signal supplied to the input terminal 1 is supplied to the input terminal 1 via the cable ca 4: 4.
2: 2 standard equipment (eg video camera, VTR, etc.) 2
And output to the device 2 of the 4: 2: 2 standard 10
Bit digital image data is supplied to the parallel / serial converter 3 via the cable ca, the 10 bit digital image data is converted into 1 bit digital image data by the parallel / serial converter 3, and the 1 bit is converted. Is supplied to one fixed contact 4a of the switch 4 via the cable ca.

On the other hand, similarly to the above, for example, a synchronizing signal supplied to the input terminal 1 is supplied to a device (for example, video camera, VTR, etc.) of the 4: 2: 2 standard via a cable ca, and the 4: 2 is supplied to the device. : 10-bit digital video data output from the device 2 of 2 standards is supplied to the parallel / serial converter 6 via the cable ca, and this 10-bit digital video data is converted into 1-bit digital data by the parallel / serial converter 6. It is converted into digital video data, and the 1-bit digital video data is supplied to the other fixed contact 4b of the switch (switcher) 4 via the cable ca.

Then, by selectively connecting the movable contact 4c of the switch 4 to the fixed contact 4a or 4b, the cables ca from the parallel / serial converters 3 and 6 respectively.
The digital video data supplied via the cable VCA is selectively supplied to the digital VTR 7 via the cable ca, and is recorded so that an inclined track is formed on the recording surface of the tape cassette mounted on the digital VTR 7.

By the way, when a plurality of signal sources are selected by the switch 4 and transmitted through the cable ca in this way, a signal delay due to the length of the cable ca (for example, a delay of 500 nsec per 100 m) and the cable ca. The signal sources may be transmitted out of phase due to variations in length and the like.

Therefore, it may be considered to use a synchronizing signal detecting circuit as shown in FIG. The synchronization signal detection circuit (flywheel circuit 9) cannot detect the synchronization signal by utilizing the continuity of the synchronization signal when the synchronization signal supplied via the input terminal 8 cannot be detected due to the occurrence of a transmission error or the like. The portion is corrected and the corrected synchronization signal is output from the output terminal 10.

The operation when the synchronizing signal detecting circuit using the flywheel circuit 9 shown in FIG. 5 is used in the system shown in FIG. 4 (for example, the digital VTR 7) will be described below with reference to FIG. Become.

First, the movable contact 4 of the switch 4 shown in FIG.
When c is connected to the fixed contact 4a, the flywheel circuit 9 receives the digital data from the parallel / serial converter 3 as shown in FIG. 6A via the input terminal 8. Then, the EA of the received received digital data
V (End of Active Video) and S
AV (Start of Active Video)
6B, output digital data whose phase matches the EAV and SAV of the received digital data is obtained during the period t1, and this is output through the output terminal 10.

Next, when the movable contact 4c of the switch 4 shown in FIG. 4 is switched to the fixed contact 4b, the flywheel circuit 9 causes the source data switch point p1 shown in FIG. 6A.
Subsequent digital data from the parallel / serial converter 6 is received via the input terminal 8.

If the digital data output from the parallel / serial converter 3 and the parallel / serial converter 6 are used.
Each EAV and SAV of digital data output from
6A and B, the flywheel circuit 9 is in phase with the EAV and SAV of the digital data currently supplied from the parallel / serial converter 6 during the period indicated by t2. Different digital data will continue to be output from the output terminal 10, which continues until the flywheel counter reset point p2 shown in FIG. 6B, and from this reset point p2 onward, the EAV of digital data from the parallel / serial converter 6 is finally reached. , And SAV, the digital data having the same phase is output.

[0013]

As described above, when the conventional synchronizing signal detecting circuit using the flywheel circuit 9 is used in the system as shown in FIG. 4, the digital signal initially selected by the switch 4 is selected. Since the data is locked, there is a drawback that it takes time to lock the synchronization of the next selected digital data (different sync positions), and the sync output differs from the actual received data.

A method of detecting a sync signal from the received data is also conceivable. However, when this method is used in the system shown in FIG. 4, synchronization is disturbed when a transmission error occurs and video data is supplied to a monitor or the like. When projected as an image on the tube surface, the image is significantly deteriorated.

The present invention has been made in view of the above points, and it is possible to obtain a synchronization signal that is stable against a transmission error due to noise or the like and that matches the input information at high speed with respect to the switched source data. Therefore, the present invention intends to propose a sync signal detection circuit capable of significantly reducing the disturbance of the projected image when applied to a VTR, for example.

[0016]

The sync signal detecting circuit of the present invention detects the sync of the input information and the first sync detecting sections 12 and 13 for detecting the sync of the input information, as shown in FIGS. 1 to 3, for example. A second synchronization detecting section 27, and switching signal output sections 30, 31 for outputting a switching signal based on the input information.
42, 43 and 44, the switching signal output unit 30 switches the outputs of the first and second synchronization detection units 12, 13 and 27,
The switching signals output from 31, 42, 43, and 44 are used for switching.

The synchronizing signal detecting circuit of the present invention is shown in FIG.
As shown in FIG. 3, the first synchronization detection units 12 and 13 for detecting the synchronization of the input information by the flywheel unit 13,
The second synchronization detection unit 27 that detects the synchronization of the input information, and the first and second synchronization detection units 1 based on the continuous attribute of the input information.
The switching signal forming sections 42, 43 and 44 for forming switching signals for selectively switching the outputs of 2, 13, and 27.

The synchronizing signal detecting circuit of the present invention is shown in FIG.
As shown in FIG. 3, the first synchronization detectors 12 and 13 that detect the synchronization of the input information and the second synchronization detectors that detect the synchronization of the input information.
Synchronization detection unit 27 and switching signal output units 30, 31, 42, 43 for outputting switching signals based on input information.
44 for switching the outputs of the first and second synchronization detecting units 12, 13 and 27, and switching signal output units 30, 31, 42,
The switching signal output units 30, 31, 42, 43, 44 are provided during the switching period with the switching signals output by the output signals 43, 44.
Thus, the first synchronization detectors 12 and 13 are set to the reset mode.

[0019]

According to the present invention described above, the detection outputs of the first and second synchronization detecting sections 12, 13 and 27 are switched by the switching signals output from the switching signal output sections 30, 31, 42, 43 and 44. Therefore, it is possible to obtain a synchronization signal that is stable against a transmission error due to noise or the like and that matches the input information at high speed with respect to the switched source data. Distortion of the output image can be significantly reduced.

According to the present invention described above, the input information is detected by the flywheel unit 13 of the first synchronization detecting units 12 and 13, and the input information is detected by the second synchronization detecting unit 27. Since the detection output is switched based on the continuity of the input information, it is possible to obtain a synchronization signal that is stable against transmission errors due to noise and that matches the input information at high speed with respect to the switched source data. This makes it possible to significantly reduce the disturbance of the projected image when applied to a VTR, for example.

Further, according to the present invention described above, a period in which the outputs of the first and second synchronization detecting units 12, 13 and 27 are switched by the switching signals output from the switching signal output units 30, 31, 42, 43 and 44. The switching signal output unit 3
Since the first synchronization detectors 12 and 13 are set to the reset mode by 0, 31, 42, 43 and 44, they are stable against a transmission error due to noise and the like, and high speed with respect to the switched source data. To obtain a synchronization signal that matches the input information.
When applied to R, the disturbance of the projected image can be significantly reduced.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the sync signal detecting circuit of the present invention will be described in detail below with reference to FIG.

In FIG. 1, reference numeral 11 denotes an input terminal to which digital video data received by a digital VTR main circuit circuit conforming to the 4: 2: 2 standard (not shown) is input, and digital video data from the input terminal 11 is It is supplied to the synchronization signal detection circuits 12 and 27 and the timing reference signal detection circuit 31, respectively.

As shown in FIG. 2, the sync signal detection circuit 12 detects the frames in the data x, y, z, the horizontal and vertical sync signals recorded in the sync signal area e2 of the magnetic tape 50, and detects them. Flywheel circuit 1 for detection signal
3 is supplied to the differentiating circuit 14.

The differentiating circuit 14 is a synchronizing signal detecting circuit 12
A differential signal is obtained from the falling edge of the detection signal from, and this differential signal is applied to the fixed contact 15b of the switch 15 and the OR circuit 18
And AND circuit 16, respectively.

The fixed contact 15a of the switch 15 is supplied with an output from a decoder 25 which will be described later.
Reference numeral 5 designates the movable contact 15c of the fixed contact 15a or 1 based on the output from the flip-flop circuit 23 described later.
5b and supplies this switching output to the horizontal / frame counter 24. That is, this switch 15 is
In the locked state, the signal from the decoder 25
The frame counter 24 is cleared, and in the unlocked state, the frame bit is cleared at the fall of the differentiation signal from the differentiation circuit 14.

The horizontal / frame counter 24 is composed of a counter for one line period of the horizontal synchronizing signal and a counter for one frame period for counting with a clock delayed by one line, and after being cleared by the signals from the switches 15, respectively. The periods of the horizontal and frame synchronization signals are counted, and the counting results are supplied to the decoders 25 and 26, respectively.

The decoder 25 sends a control signal obtained based on the counting result from the horizontal / frame counter 24 to the fixed contact 15a of the switch 15, the OR circuit 18 and the inverter 1.
Supply to 7 respectively.

The decoder 26 also generates a frame, vertical and horizontal synchronizing signal based on the counting result from the horizontal / frame counter 24, and uses this as a flywheel frame, vertical and horizontal synchronizing signal, and a fixed contact 28b of the switch 28. Supply to.

On the other hand, the OR circuit 18 obtains the logical sum of the differential signal from the differentiating circuit 14 and the control signal from the decoder 25, and supplies this to the error counter 19 and the flip-flop 23, respectively.

Further, the AND circuit 16 has a differential signal from the differential circuit 14, a signal obtained by inverting the control signal from the decoder 25 by the inverter 17, and the flip-flop circuit 23.
The logical product of the output signals from the
Supply to 9.

The error counter 19 is cleared by the output from the OR circuit 19, performs counting based on the output (enable signal) from the AND circuit 16, and supplies the counting result (for example, 2 bits) to the decoder 20.

Based on the counting result from the error counter 19, the decoder 20 obtains a signal which falls when an error occurs consecutively a predetermined number of times, for example, and this signal is differentiated by the differentiating circuit 2.
Supply to 1.

The differentiation circuit 21 obtains a differentiation signal at the trailing edge of the signal from the decoder 20 and supplies it to the AND circuit 22. The AND circuit 22 obtains the logical product of the differential signal from the differential circuit 43 described later and the differential signal from the differential circuit 21, and supplies the logical product to the flip-flop circuit 23.

The flip-flop circuit 23 is set or reset according to the output of the OR circuit 18, and supplies the output from the AND circuit 22 to each of the above circuits as a frame flywheel status signal. The frame flywheel status signal has a high level "1" when locked, for example.

On the other hand, as shown in FIG. 2, the timing reference signal detection circuit 30 detects the timing reference signal recorded in the timing reference signal area e1 of the magnetic tape 50, and outputs the detection result to the flywheel circuit 31. The OR circuit 32, the fixed contact 39b of the switch 39 and the AND circuit 33, and the synchronization signal detection circuit 27 are supplied to the constituents.

The switch 39 is controlled by the output of a flip-flop circuit 38 described later, and by selectively connecting the movable contact 39c to the fixed contact 39a or 39b, a control signal from a decoder 41 described later (when locked) ) And a detection signal (when unlocked) from the timing reference signal detection circuit 30 are selectively supplied to the horizontal counter 40 as a clear signal.

The horizontal counter 40 is a one-line cycle counter, counts the horizontal cycle after being cleared by a signal from the switch 39, and supplies the count result to the decoder 41.

The decoder 41 obtains a control signal on the basis of the counting result from the horizontal counter 40, and the control signal is supplied to the switch 39.
To the fixed contact 39a, the OR circuit 32, the inverter 34, and the comparison circuit 42.

The OR circuit 32 obtains the logical sum of the control signal from the decoder 41 and the detection output from the timing reference signal detection circuit 30, and outputs this logical sum to the error counter 35.
And the flip-flop circuit 38 and the sync signal detection circuit 12 described above.

On the other hand, the AND circuit 33 obtains the logical product of the output of the flip-flop circuit 38, the output of the inverter 34, and the output from the timing reference signal detection circuit 30, which will be described later, and supplies this to the error counter 35 as an enable signal. ..

The error counter 35 is cleared by the output from the OR circuit 32 and starts counting based on the enable signal from the AND circuit 33. Here, in the locked state and normally, this enable signal becomes low level “0”, the error counter 35 stops counting,
If there is no detection output from the timing reference signal detection circuit 30, the output from the decoder 41 counts up. Further, in the unlocked state, the enable signal becomes low level “0”, and the error counter 35
Stops counting.

The count output (for example, 4 bits) of the error counter 35 is supplied to the decoder 36. Decoder 3
6 is, for example, 1 from the counting result from the error counter 35.
A signal that falls when an error occurs five times in a row is supplied to the differentiating circuit 60.

The differentiation circuit 60 obtains a differentiation signal from the edge of the output from the decoder 36 and supplies it to the AND circuit 37. The AND circuit 37 obtains the logical product of the differential signal from the differential circuit 60 and the differential signal from the differential circuit 43, which will be described later, and supplies the logical product to the flip-flop circuit 38.

The flip-flop circuit 38 sets and resets the output from the AND circuit 37 according to the output from the OR circuit 32. The output (timing reference signal lock flag) of the flip-flop circuit 38 is at a high level “1” when locked and at a low level “0” when unlocked.

The output of the flip-flop circuit 38 is supplied to the comparison circuit 42, and the comparison circuit 42 is further supplied.
A signal obtained by inverting the output of the decoder 41 by the inverter 34 and a detection signal from the timing reference signal detection circuit 30 are supplied to the circuit.

The comparator circuit 42 outputs the output from the flip-flop circuit 38, that is, the output from the decoder 41 (synchronized output by the timing reference signal flywheel) and the timing reference signal when the timing reference signal is in the locked state. Detection circuit 30
It is detected whether or not there is a discontinuous portion in the input signal by comparison with the detection signal from, and a signal falling at the time of detecting the discontinuous portion is supplied to the differentiating circuit 43.

The differentiating circuit 43 obtains a differentiating signal at the trailing edge of the comparison result from the comparing circuit 42 and flips it.
It is supplied to the flop circuit 44 and the AND circuits 37 and 22, respectively.

On the other hand, the sync signal detection circuit 27, like the sync signal detection circuit 12, as shown in FIG. 2, is based on the detection output from the timing reference signal detection circuit 30 described later, and the sync signal area e2 of the magnetic tape 50. The frame, horizontal and vertical sync signals in the data x, y, z recorded in the above are detected, and the detection signals are supplied to the fixed contact 28a of the switch 28.

The flip-flop circuit 44 sets or resets the differential signal from the differentiating circuit 43 based on the output from the flip-flop circuit 23, and the movable contact of the switch 28 based on the differentiating signal from the differentiating circuit 43. 28c is selectively connected to the fixed contact 28a or 28b, so that the so-called raw data from the sync signal detection circuit 27 or the sync output from the decoder 26 is selectively supplied to the VTR main circuit (not shown) via the output terminal 29. Let

Next, two sources video1 and v, such as the system described with reference to FIG. 3 for example in FIG.
Regarding the detection and correction operation of the horizontal synchronizing signal of the above-mentioned synchronizing signal detecting circuit when the video 2 is switched to record on the magnetic tape 50 (the description is omitted because the frame and the vertical synchronizing signal are also performed similarly) explain.

As shown in FIG. 3A, first, the source v
The sync output of the decoder 26 outputs a horizontal sync signal for each line by the EAV and SAV of video 1 (shown in FIG. 2), and similarly, the output of the sync signal detection circuit 27 also outputs a horizontal sync signal for each line.

Here, when a data error indicated by a broken line occurs as shown in FIG. 3A, the output of the sync signal detection circuit 27 is missing for one line, but the output of the decoder 26 remains horizontal and the horizontal synchronization is performed. Since the signal is output, the output synchronizing signal from the output terminal 29 shown in FIG. 1 has the missing portion corrected as shown in FIG. 3E.

On the other hand, as shown in FIG. 3A, when the source video1 is switched to the source video2 at the switch point p10 shown by the solid arrow and the wavy line,
The output of the decoder 26 shown in is the EA of the source video2.
Although it is deviated from V and SAV, the movable contact 28c of the switch 28 is switched to the fixed contact 28a by the output of the flip-flop circuit 44 shown in FIG. 3D, and the output from the synchronization signal detection circuit 27 (see FIG. 3C) is selected. Therefore, during this period, the horizontal synchronizing signal output from the output terminal 29 coincides with the EAV and SAV recorded in the source video2 as shown in FIG. 3E.

Then, as shown in FIG. 3A, the horizontal / frame counter 24 of the flywheel circuit 13 is further forcibly reset at the forced reset point p11 to fly the synchronous output matching the EAV or SAV of the source video2. It is output to the wheel circuit 13. Therefore, if a so-called raw data is not obtained when the data error shown by the solid line in FIG. 3A occurs, the synchronous output of the flywheel circuit 13 output by the forced reset is obtained as shown in FIG. 3E.

Thus, in this example, the comparison circuit 4
2 compares the positions of the past sync signal and the current sync signal,
When a discontinuous portion is detected, the flip-flop circuit 44 controls the switching of the switch 28 to switch the synchronous output from the flywheel circuit 13 to the so-called raw data from the synchronous signal detecting circuit 27, and also the horizontal / frame counter. 24 is forcibly reset, and when the flywheel circuit 13 is locked next time, the output of the flywheel circuit 13 is set, so that it is stable against a transmission error due to noise or the like, and the source data is switched. It is possible to obtain a sync signal that matches the input information at high speed, and thereby, when applied to a VTR, for example, it is possible to significantly reduce the disturbance of the projected image.

The above embodiment is an example of the present invention.
Of course, various other configurations can be adopted without departing from the scope of the present invention.

[0058]

According to the present invention described above, the first and second
Since the detection output of the synchronization detection unit is switched by the switching signal output by the switching signal output unit, it is stable against transmission errors due to noise, etc., and matches the input information at high speed with the switched source data. It is possible to obtain a synchronized signal, which is advantageous in that the disturbance of the projected image can be significantly reduced when applied to a VTR, for example.

Further, according to the present invention described above, the input information is detected by the flywheel section of the first synchronization detecting section, the input information is detected by the second synchronization detecting section, and these detected outputs are detected as input information. Since switching is performed based on continuity, it is stable against transmission errors due to noise, etc., and
It is possible to obtain a sync signal that matches the input information at high speed with respect to the switched source data, and this has the advantage that, when applied to a VTR, for example, the disturbance of the projected image can be greatly reduced.

Further, according to the present invention described above, during the period in which the outputs of the first and second synchronization detection units are switched by the switching signal output by the switching signal output unit, the switching signal output unit causes the first synchronization detection unit to operate. Since it is set to the reset mode, it is stable against transmission errors due to noise, etc.
In addition, it is possible to obtain a sync signal that matches the input information at high speed with respect to the switched source data, which has the advantage that the disturbance of the projected image can be significantly reduced when applied to a VTR, for example. is there.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a synchronization signal detection circuit of the present invention.

FIG. 2 is an explanatory diagram for explaining a synchronization signal detection circuit of the present invention.

FIG. 3 is a timing chart provided for explaining one embodiment of the synchronization signal detection circuit of the present invention.

FIG. 4 is a configuration diagram showing an example of a system for recording a digital signal on a digital VTR.

FIG. 5 is a configuration diagram showing an example of a conventional synchronization signal detection circuit.

FIG. 6 is a timing chart used for explaining an example of a conventional synchronization signal detection circuit.

[Explanation of symbols]

 12 synchronization signal detection circuit 13 flywheel circuit 27 synchronization signal detection circuit 30 timing reference signal detection circuit 31 flywheel circuit 42 comparison circuit 43 differentiation circuit 44 flip-flop circuit

Claims (3)

[Claims] 1. A first synchronization detecting section for detecting synchronization of input information, a second synchronization detecting section for detecting synchronization of the input information, and a switching signal output for outputting a switching signal based on the input information. And a switching section for switching the outputs of the first and second synchronization detection sections by a switching signal output from the switching signal output section. 2. A first synchronization detection unit for detecting synchronization of input information by a flywheel unit, a second synchronization detection unit for detecting synchronization of the input information, and a linkage attribute of the input information, And a switching signal forming section for forming a switching signal for selectively switching the outputs of the first and second synchronization detecting sections. 3. A first synchronization detecting section for detecting synchronization of input information, a second synchronization detecting section for detecting synchronization of the input information, and a switching signal output for outputting a switching signal based on the input information. And a section for switching the outputs of the first and second synchronization detecting sections by a switching signal output from the switching signal output section,
A synchronization signal detection circuit, wherein the switching signal output unit sets the first synchronization detection unit in a reset mode.