JPH05313189A - Method of manufacturing thin film transistor matrix - Google Patents

Abstract

PURPOSE:To prevent the gate insulating film of the TFT matrix from being destroyed or deteriorating in characteristics owing to the accumulation of static electricity in a manufacture process. CONSTITUTION:Wide capacity electrodes 10 which are parallel to gate bus lines 2 are formed in areas nearby end sides of a substrate 1 and after the gate insulating film 5 is deposited, end parts of drain bus lines 3 formed thereupon are extended onto the capacity electrodes 10. In the final stage of the manufacture process of the TFT matrix or the liquid crystal display device using it, etc., the end side nearby areas are disconnected from the substrate 1 and the drain bus lines 3 and their end parts are separated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor matrix (TFT) which constitutes a so-called active matrix type liquid crystal display device.

[0002]

2. Description of the Related Art Attempts to put a portable personal computer, a color display device of a word processor, or a wall-mounted color television into practical use by utilizing a liquid crystal and a TFT have been vigorously pursued in various fields.

The TFT applied to the display device or the color television as described above is defective in one of several hundreds of millions to several millions of transistors arranged in a matrix on an insulating substrate such as a glass plate. Is not allowed either. One of the main reasons why these transistors are defective is the electrostatic breakdown of the insulating film. For example, in processes such as sputtering or CVD (Chemical Vapor Deposition) for depositing conductive films or insulating films, or in processes for patterning wiring such as gate electrodes or bus lines, which use plasma,
Static electricity accumulates on the floating gate electrode and the source and drain electrodes, causing dielectric breakdown of the insulating film, especially the gate insulating film. Dielectric breakdown due to such static electricity also occurs due to various other causes. For example, in the lithographic process for forming the source and drain electrodes, static electricity is accumulated in the electrodes due to so-called peeling charging that occurs when the substrate coated with the resist is baked and then removed from the support. Also,
When touching these bus lines with a finger during the manufacturing process of TFT, the process of bonding a substrate with TFT formed on it to another substrate, or the process of injecting liquid crystal into the gap between the bonded substrates, The accumulated static electricity may flow to the bus line, causing dielectric breakdown of the gate insulating film. In addition, the accumulation of static electricity as described above may deteriorate the characteristics of the TFT, especially the threshold voltage.

[0004]

In order to avoid the electrostatic breakdown as described above, as shown in FIG. 4, the end portions 2A of the gate bus line 2 and the drain bus line 3 respectively.
The electrodes 3 and 3A are interconnected by an electrode 20 formed of an aluminum thin film or the like formed in a region near the edge of the substrate 1. However, conventionally, the interconnect electrode 20 was formed after the TFT matrix was completed. For this reason, it was not effective against static electricity destruction or TFT characteristic deterioration due to charging or peeling charging due to plasma treatment as described above in the existing process.

According to the present invention, the capacitance between the gate electrode and the gate bus line and the source and drain electrode and the drain bus line is in parallel with the capacitance only in a necessary period of the manufacturing process of the TFT or the liquid crystal display device using the TFT. The purpose is to prevent the electrostatic breakdown of the insulating film between the gate electrode and the source and drain electrodes or between the gate bus line and the drain bus line, which directly affects the quality of the TFT, by temporarily forming the capacitance. And

[0006]

The above-mentioned object is to provide a plurality of gate electrodes arranged in a matrix on an insulating substrate, a plurality of gate bus lines each connecting the gate electrodes on the same row, and A gate insulating film covering the gate electrode and the gate bus line, and a plurality of active regions each formed of a semiconductor layer deposited on the gate insulating film and arranged in the matrix corresponding to the gate electrode, A plurality of source and drain electrode pairs, each pair being a pair of electrodes formed in contact with one of the active regions and facing each other through a channel region defined in the active region; In manufacturing an inverted stagger type thin film transistor matrix having a plurality of drain bus lines connecting the drain electrodes in contact with the active regions on the same row,
The gate electrode and the gate bus line are formed in a central region on one surface of the insulating substrate, and the gate electrode and the gate bus line extend in parallel to the gate bus line in a region near an edge parallel to the gate bus line in the insulating substrate. Forming a capacitance electrode having a width larger than that of the gate bus line,
A gate insulating film covering the gate electrode, the gate bus line, and the auxiliary electrode is formed, a plurality of the active regions made of the semiconductor layer is formed on the gate insulating film, and a plurality of the active regions corresponding to the active regions are formed. Forming a pair of source and drain electrodes and forming a plurality of drain bus lines each having an end portion connecting the drain electrodes on the same column and extending on the capacitance electrode; This is achieved by the method of manufacturing a thin film transistor matrix according to the present invention, which includes various steps of separating the corresponding end portions.

[0007]

At the same time as forming the gate electrode and the gate bus line, a wide electrode (hereinafter referred to as a capacitor electrode) extending in parallel with the gate electrode is formed in a region near the edge of the substrate. Then, similarly to the normal manufacturing process, formation of a gate insulating film, formation of an active region made of an amorphous silicon film, formation of source and drain electrodes and a drain bus line are sequentially advanced. The width of the gate electrode, the source and drain electrodes, the gate bus line and the drain bus line is about 15 μm. On the other hand, the width of the capacitance electrode is
It can be increased to about 30 mm. Therefore, the total facing area between the conductive film forming the source and drain electrodes or the source and drain electrodes and the like formed by patterning the conductive film and the gate electrode and the gate bus line, and the facing area between the capacitive electrodes. Comparing the area, the latter can be made several hundred times larger. As a result, the electrostatic breakdown occurring in the gate insulating film is larger in proportion to the area ratio on the capacitor electrode than on the gate electrode or at the intersection of the bus lines. Therefore, the electrostatic breakdown that occurs in a few TFTs in a normal TFT matrix virtually disappears. Further, since the potentials of the electrodes and the bus line due to the accumulated charges are reduced in almost inverse proportion to the large auxiliary capacitance by the capacitance electrode as described above, there is an effect that electrostatic breakdown is less likely to occur.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to facilitate understanding of the present invention, the structure and manufacturing process of a stagger type TFT matrix to which the present invention is applied will be described with reference to FIGS.

FIG. 1 is a plan view showing an arrangement of one TFT and gate bus lines 2 and drain bus lines 3 related thereto. That is, TFT is a gate bus line 2
A drain electrode 3B extending from the drain bus line 3, and a source electrode 4 made of the same conductive film as the drain electrode 3B.

FIG. 2 shows how the XX cross section in FIG. 1 changes with the manufacturing process of the TFT. Same figure
As shown in the sectional view of (a), a gate electrode 2B made of a titanium film is formed on the surface of a substrate 1 made of, for example, transparent glass. The gate bus line 2 (not shown) is also formed of the same titanium film as the gate electrode 2B. Further, usually, an auxiliary electrode made of, for example, an aluminum film is previously formed between the gate bus line 2 and the substrate 1. Then, on the surface of the substrate 1, a gate insulating film 5 made of, for example, Si ₃ N ₄ and having a thickness of about 0.3 μm and a semiconductor layer 6 made of non-doped amorphous silicon so as to cover the gate electrode 2B and the gate bus line 2. And a channel protective film 7 of Si ₃ N _{4 having a} thickness of about 0.1 μm is sequentially deposited.

Then, as shown in FIG. 2 (b), the channel protection film 7 is patterned into a shape substantially corresponding to the gate electrode 2B, and then, as shown in FIG. 2 (c), a thickness of about 0.05 μm is obtained.
Depositing a conductive film 3 ₀ made of amorphous silicon film 3 ₁ and thickness of about 0.05μm titanium film 3 ₂ of the n-type. Then, the conductive film 3 _0, as shown in FIG. 2 (d), is patterned into the shape of the drain electrode 3B and the source electrode 4 and the drain bus line 3, further semiconductor layer 6, separated for each TFT active Pattern the regions. The drain bus line 3 extends perpendicularly to the paper surface.

Then, as shown in FIG. 2 (e), the drain bus line 3 is extended, for example, connected to the auxiliary electrode 8 and the source electrode 4 made of an aluminum film, for example,
After forming the display electrode 9 made of ITO (indium tin oxide) film, a protective film 10 made of, for example, Si ₃ N ₄ is formed to cover the TFT, the gate bus line 2 and the drain bus line 3.
The TFT matrix is completed.

In one embodiment of the present invention, for example, a titanium film forming the gate electrode 2B and the gate bus line 2 is patterned to form a capacitor electrode extending to a region near one end side of the substrate 1, To form a large auxiliary capacitance. This step will be described with reference to FIG. Note that FIG.
(a), (c), (e) are plan views, and FIGS. 3 (b), (d), (f) are partially enlarged sectional views in the XX direction in these plan views.

As shown in FIGS. 3 (a) and 3 (b), a titanium film is deposited on a substrate 1 made of, for example, glass, and the titanium film is patterned to form a gate bus line 2. The capacitor electrode 10 is formed on the substrate 1 in the region 1A near the edge parallel to the gate bus line 2.
The capacitive electrode 10 may be formed only in at least one edge vicinity region 1A. As mentioned above, gate bus line 2
The width of the gate electrode 2B extending from this point onward is about 15 μm, while the width of the capacitor electrode 10 is about 30 μm. Although not shown in the figure, it goes without saying that the gate electrode 2B as shown in FIG. 1 extends from the gate bus line 2. In addition, the capacitance electrode 10 is the gate electrode 2
It can be formed separately from B etc.

Next, as shown in FIG. 3B, a gate insulating film 5 made of Si ₃ N ₄ and having a thickness of about 0.3 μm is deposited on the surface of the substrate 1. A non-doped amorphous silicon film with a thickness of about 0.02 μm is deposited on the gate insulating film 5, and further,
After forming the channel protection film 7 as shown in FIG. 2 in a predetermined region on the amorphous silicon film, the amorphous silicon film is patterned into active regions (not shown) for each TFT. Furthermore, an n-type amorphous silicon film with a thickness of about 0.05 μm and a titanium film with a thickness of about 0.05 μm are sequentially deposited on the surface of the substrate 1, and these are patterned,
A drain bus line 3 orthogonal to the gate bus line 2 is formed. Although not shown in the figure, it goes without saying that the drain electrode 3B as shown in FIG. 1 extends from the drain bus line 3 and the source electrode 4 is simultaneously formed. After forming the drain bus line 3, an auxiliary electrode 8 made of, for example, an aluminum film, as shown in FIG. 2E, may be formed thereon. In the above, the case where the patterning of the amorphous silicon film forming the active region of the TFT and the patterning of the conductive film forming the drain bus lines 3 and the like are performed separately has been described. However, a mask for forming the drain bus lines 3 and the like is described. The non-doped amorphous silicon film may be patterned by using. In this case, the amorphous silicon film is interposed between the drain bus line 3 and the end 3A in FIG. 3 (d) and the gate insulating film 5, but there is no problem.

Providing an n-type amorphous silicon film as a lower layer of the conductive film forming the drain bus line 3 and the like has the following advantages. That is, since amorphous silicon can be deposited by a low power plasma CVD (chemical vapor deposition) method, there is a low probability that electrostatic breakdown will occur in the gate insulating film 5 in this step. Further, in the step of depositing the upper titanium film by the sputtering method, a large capacitance is generated between the lower n-type amorphous silicon film and the capacitor electrode 10, so that the probability of electrostatic breakdown of the gate insulating film 5 is reduced. To do.

The drain bus line 3 has an end 3A extending in a region 1A near the edge of the substrate 1. From the widths of the gate bus line 2 and the drain bus line 3 and the like and the width of the capacitor electrode 10 as described above, for example, 480 gate bus lines 2
And the total area of the intersections of the 1920 drain bus lines 3 and the areas of the facing portions of the gate electrode 2B, the drain electrode 3B and the source electrode 4, and the end portions 3A of the 1920 drain bus lines 3 and the capacitor electrodes. The ratio with the total of facing areas with 10 is 1: 4 or more. Therefore, considering the fact that the thickness of the insulating film deposited on the large-area liquid crystal display panel substrate is somewhat thin in the peripheral portion, electrostatic breakdown of the gate insulating film 5 at the intersections of these bus lines and the portions facing the electrodes is considered. The probability of is reduced to several tens of minutes by providing the capacitive electrode 10. Further, since the potentials of these bus lines and electrodes due to the accumulated charges are reduced to several tens to several tens of minutes by providing the capacitive electrode 10, the probability of electrostatic breakdown is reduced.

As shown in FIG. 3 (c), the substrate 1 on which the TFT matrix is formed as described above is overlapped with another substrate 11 with a predetermined gap, and the periphery of these substrates 1 and 11 is, for example, After bonding with the adhesive layer 12 and filling the liquid crystal in the gap, the drain bus line 3 and its end 3A are electrically separated to complete the liquid crystal display device. For the separation, a diamond cutter or the like may be used to cut the edge region 1A from the substrate 1. Alternatively, instead of cutting the substrate 1, only the drain bus line 3 and its end 3A may be cut. Needless to say, when the auxiliary electrode 8 is formed on the drain bus line 3, the auxiliary electrode 8 is also cut.

The substrate 1 on which the TFT matrix according to the present invention is formed or the substrate 1 bonded to another substrate 11
In each case, since the gate bus line 2 and the drain bus line 3 are electrically separated, disconnection inspection for each bus line, between the bus lines, and between the gate electrode 2B and the drain electrode 3B and the source electrode 4 are performed. It is possible to perform short circuit inspection and further TFT characteristic testing.

[0020]

According to the present invention, the TFT matrix is completed from the initial stage of the step of depositing the conductive film forming the source and drain electrodes and the drain bus line on the substrate on which the gate potential and the gate bus line are formed. The probability of electrostatic breakdown in the gate insulating film is significantly reduced over the period up to the final stage of the manufacturing process of liquid crystal display devices using this, and TFT characteristic deterioration is prevented. Has an effect of contributing to the improvement of manufacturing yield.

[Brief description of drawings]

[Fig.1] Schematic diagram of TFT

[Figure 2] TFT manufacturing process explanatory diagram

FIG. 3 is a process explanatory view of an embodiment of the present invention.

FIG. 4 is an explanatory diagram of conventional problems

[Explanation of symbols]

1, 11 Substrate 4 Source electrode 1A Edge neighborhood 5 Gate insulating film 2 Gate bus line 6 Semiconductor layer 2B Gate electrode 7 Channel protective film 3 Drain bus line 8 Auxiliary electrode 3A End 9 Display electrode 3B Drain electrode 10 Capacitive electrode 3 ₀ Conductive film 12 Adhesive layer 3 ₁ Amorphous silicon film 20 Interconnection electrode 3 ₂ Titanium film

Claims (8)

[Claims] 1. A plurality of gate electrodes arranged in a matrix on an insulating substrate, a plurality of gate bus lines each connecting the gate electrodes on the same row, and the gate electrodes and the gate bus lines. A gate insulating film for covering, a plurality of active regions each formed of a semiconductor layer deposited on the gate insulating film and arranged in the matrix corresponding to the gate electrode, and each pair of active regions. A plurality of source and drain electrode pairs, which are a pair of electrodes formed in contact with each other and facing each other through a channel region defined in the active region, and In manufacturing an inverted stagger type thin film transistor matrix having a plurality of drain bus lines connecting the drain electrodes in contact with each other, the gate is formed in a central region on one surface of the insulating substrate. A step of forming a gate electrode and the gate bus line, and a width larger than a width of the gate bus line and extending in a region near an end side of the insulating substrate parallel to the gate bus line. A step of forming a capacitive electrode having a gate electrode, a step of forming a gate insulating film covering the gate electrode, the gate bus line, and the auxiliary electrode, and forming a plurality of the active regions made of the semiconductor layer on the gate insulating film. A step of forming a plurality of source and drain electrode pairs corresponding to each of the active regions and connecting a plurality of source and drain electrode pairs on the same column and having an end portion extending on the capacitance electrode. A thin film transistor including a step of forming a drain bus line and a step of separating each of the drain bus lines and the corresponding end portion thereof. Method of manufacturing a static matrix. 2. The method according to claim 1, further comprising a step of depositing a conductive film on one surface of the insulating substrate and then forming the conductive film into the gate electrode, the gate bus line and the capacitor electrode. Method of manufacturing thin film transistor matrix. 3. The drain bus line and the end portion corresponding to the drain bus line are separated by cutting and separating a region near the end side in which the capacitance electrode is formed in the insulating substrate from a central region. The method of manufacturing a thin film transistor matrix according to claim 1. 4. The method according to claim 3, further comprising the step of joining the insulating substrate to another substrate with a predetermined gap prior to the step of cutting and separating the edge vicinity region of the insulating substrate from the central region. Method for manufacturing thin film transistor matrix. 5. The method according to claim 1, further comprising the step of forming an auxiliary electrode on each of the plurality of drain bus lines, the auxiliary electrode being made of a conductive film having a resistance lower than that of each drain bus line.
A method for manufacturing the thin film transistor matrix described. 6. A step of depositing the semiconductor layer on the gate insulating film, and a step of forming the source and drain electrode pair and the drain bus line and then molding the semiconductor layer in the active region. The method of manufacturing a thin film transistor matrix according to claim 1, wherein. 7. Before forming the gate electrode and the gate bus line on one surface of the insulating substrate, the gate bus line is formed so as to selectively extend at least in a region where the gate bus line is arranged. 2. The method of manufacturing a thin film transistor matrix according to claim 1, further comprising the step of forming an auxiliary electrode made of a low resistance conductive film. 8. The method of manufacturing a thin film transistor matrix according to claim 1, wherein the source / drain electrode pair and the drain bus line are made of at least an n-type amorphous silicon film.