JPH05328168A - Synchronizing signal detector - Google Patents

Abstract

(57) [Abstract] [Purpose] To accurately extract the horizontal sync signal position from a digitized composite color video signal including noise and burst signals with a simple configuration. [Structure] From the outputs of the pedestal level detector 1 and the sync tip level detector 2, it is determined whether or not the digitized composite color video signal has changed from the pedestal level to the sync tip level at a predetermined time. Only when this change occurs in a predetermined time, the change point of the comparator 8 that compares the intermediate value between the pedestal level and the sync tip level with the video signal is output as the synchronization detection position.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sync signal detecting device for detecting the position of a sync signal of a digital composite color video signal.

[0002]

2. Description of the Related Art When a horizontal synchronizing signal is obtained from an analog video signal, an intermediate value between a pedestal level and a sync tip level is compared with a reference value to obtain a sync signal position. A low pass filter (LPF) is generally inserted before the synchronization detection in order to prevent the influence of noise and burst signals being generated. The same configuration is used for digital video signals as shown in FIG.
Shows the block diagram in this case. In FIG. 4, reference numeral 12 is a digital filter, and 13 is a comparator (see, for example, Japanese Patent Laid-Open No. 62-11372).

[0003]

However, in the case of handling a digital video signal, this method requires a digital filter to be constructed, resulting in a large circuit scale.

The present invention has been made in view of the above-mentioned drawbacks, and an object of the present invention is to detect the horizontal synchronizing signal position directly from a digital composite color video signal without using a digital filter for removing noise and subcarrier components. And

[0005]

To achieve this object, in the present invention, a first detector for detecting whether or not an input digital composite color video signal has a value near a pedestal level, and A second detector for detecting whether the signal has a value near the sync tip level,
A circuit that determines whether or not the input video signal changes from the pedestal level to the sync tip level in a predetermined time from the outputs of the first and second detectors, and the signal determines the pedestal level and the sync tip level. Using a third detector that determines whether or not it is greater than the approximate intermediate value of, the change point of the output of the third detector only when the input signal changes from the pedestal level to the sync tip level in a predetermined time. Is output as a synchronization signal position.

[0006]

With the above structure, the position of the horizontal synchronizing signal can be accurately extracted from the digital composite color video signal in which the subcarrier components such as noise and burst signal are still superposed.

[0007]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a sync signal detecting apparatus according to an embodiment of the present invention. Further, FIG. 2 shows signal waveforms in each part of FIG.

The input digital composite color video signal is a pedestal level detector 1 for detecting whether it is near the pedestal level and a sync chip level detector 2 for detecting whether it is near the sync chip level. Is supplied to. These detectors output "H" level if the input is near each level, and output "L" level otherwise.

The output C of the sync tip level detector 2 is supplied to the rising edge detection circuit 3. The output B of the pedestal level detector 1 is supplied to the delay circuits 4 and 5. The delay circuit 4 defines the lower limit of the change time T from the pedestal level of the video signal to the sync tip level, and the delay circuit 5 defines the upper limit of the conversion time T. Therefore, the delay time of the delay circuit 4 is set to be slightly shorter than the standard value of the change time T, and conversely the delay time of the delay circuit 5 is set to the change time T.
Is set to be slightly longer than the standard value of.
That is, the output D of the delay circuit 4 is output by the AND circuit 6.
Is at "L" level and the output E of the delay circuit 5 is at "H" level, the output F of the edge detection circuit 3 is supplied to the timer circuit 7. In other cases, the output F of the edge detection circuit 3 is masked. Will end up. The timer circuit 7 generates a pulse H having a constant period width from the output of the edge detection circuit 3.

On the other hand, the input video signal is also supplied to a comparator 8 which compares the magnitude with an intermediate value M between the pedestal level and the sync tip level. Output I of comparator 8
Is input to the falling edge detector 9, and its output J passes through the delay circuit 10 and then the outputs H and A of the timer circuit 7
ND is taken. This output L is output as the sync signal position.

When it is not necessary to set a lower limit on the change time T from the pedestal level to the sync tip level,
As shown in FIG. 3, the delay circuit 4 and the edge detection circuit 3 can be omitted, and the configuration can be further simplified.

[0012]

As described above, according to the present invention, only when the pedestal level of the digital composite color video signal is changed from the pedestal level to the sync tip level in a predetermined time, the intermediate value between the pedestal level and the sync tip level during that time is crossed. By outputting the timing as the sync signal position, the sync signal can be accurately extracted from the digital composite color video signal in which the subcarrier components such as noises and burst signals are still superposed with a simple configuration.

[Brief description of drawings]

FIG. 1 is a block diagram of a synchronization signal detection device according to an embodiment of the present invention.

FIG. 2 is a timing chart of signal waveforms in each part of FIG.

FIG. 3 is a block diagram of a synchronization signal detection device according to another embodiment of the present invention.

FIG. 4 is a block diagram of a conventional synchronization signal detection device.

[Explanation of symbols]

 1 pedestal level detector 2 sync tip level detector 3 rising edge detection circuit 4, 5, 10 delay circuit 6, 11 AND circuit 7 timer circuit 8 comparator 9 falling edge detection circuit

Claims (1)

[Claims] 1. A first detector for detecting whether an input digital video signal has a value near a pedestal level, and a second detector for detecting whether the video signal has a value near a sync tip level. Detector and the first and second
A discriminating circuit for discriminating whether or not the input video signal changes from the pedestal level to the sync tip level from the output of the detector in a predetermined time, and the approximate intermediate value between the pedestal level and the sync tip level of the video signal. A third detector for determining whether or not it is larger than the third detector, and synchronizes the change point of the output of the third detector when the input video signal changes from the pedestal level to the sync tip level in a predetermined time. A synchronization signal detecting device which outputs as a signal position.