JPH05334894A - Data delay system - Google Patents

Abstract

PURPOSE:To provide the delay of an audio signal by a fixed time without newly providing a shift register and a memory. CONSTITUTION:A memory control circuit 18 generates respective addresses for writing and reading main data 16 inputted through a multiplexer 31 and respective addresses for writing and reading surround data 33 inputted through the multiplexer 31 and supplies these addresses to a memory 17 in synchronism with switching of multiplexers 31, 32. In the address area of the memory 17, the storage area of main data moves at a fixed speed and the storage area of the surround data moves at the sychronized speed with the former. Since reading of the surround data begins from the address later than the write address by 540 addresses, time delay of 10ms is attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data delay method using a memory, and more particularly to data for delaying sub data using the memory when main data moves in a memory address space. Regarding the delay method.

[0002]

2. Description of the Related Art In recent years, so-called MUSE (MUltiple Sub) has been carried out in order to carry out high-definition broadcasting on radio waves of satellite broadcasting.
-nyquist sampling Encoding) method has been developed and is being broadcast experimentally. In this MUSE method, the audio signal is digitally encoded without a dedicated band and is multiplexed by compressing the time axis in the vertical blanking period of the video. Further, in this method, so-called frame interleaving is applied to a signal to be transmitted in advance, in order to deal with burst errors that intensively occur on the transmission path.

Therefore, in order to correctly reproduce the received signal on the receiving side, the time axis of the received signal is expanded to the original state and the data is rearranged by performing frame deinterleaving, which is the reverse operation of frame interleaving. There is a need and audio signal decoders have been developed to do this.

By the way, conventionally, the audio signal of the television by the satellite broadcasting is limited to the monaural or the two-channel stereo system, but in the above high-definition broadcasting, the so-called 3-1 system of the four-channel stereo system is also implemented. It has become. In this 3-1 system, in addition to the front left and right speakers, signals for the front center speaker and two surround speakers hung from the rear left and right ceilings are also transmitted. Then, if these 5 speakers are properly installed and receive the above-mentioned 4-channel audio signals and reproduce them together with the high-definition high-definition and large-screen images, the realistic sensation of being seen in a special seat in a first-class movie theater You can enjoy rich audiovisual.

Two or four surround speakers are suitable, but the signals Ls and Rs for these speakers are surround signals S which are one of the signals of four channels.
Is synthesized from. The easiest way to do this is
It is possible to set Ls = S and Rs = S. However, this method has the following problems. That is,
Although it is desirable that the surround sound from these two speakers be indeterminate as an ambient sound in order to secure a realistic sensation, in the above method, the two speakers are driven at the same phase and the same level. Therefore, the sound is localized in the middle of these two speakers, that is, it sounds as if it is being output from one speaker at the rear center, and the surround effect is lost.

Therefore, as another method, Ls = S, Rs =
-S is possible. However, although this method does not cause the above-mentioned localization phenomenon, such a reverse-phase sound often gives an unpleasant impression to the ear, which is also not preferable.

Therefore, it is generally considered desirable to delay one of Ls and Rs by about 10 to 20 ms to perform time difference reproduction. That is, Ls = S, R
It is better to set s = S '. However, S'is the surround signal S delayed by about 10 to 20 ms.

[0008]

Normally, since the delay circuit for delaying such a surround signal is not built in the above-mentioned audio signal decoder LSI, a so-called DSP (digital signal processor) is provided outside. A method of delaying is considered. However, this is not realistic because it complicates the design and causes a cost increase.

On the other hand, the sampling frequency of the audio signal is 2
There are types, 32 KHz in A mode, 48 in B mode
Since the frequency is KHz and the number of quantization bits at the time of demodulation is 16 bits, the number of storage bits shown in the following equation (1) is required to perform a delay of 10 ms corresponding to both modes.

48 KHz × 16 bits × 1 / 100s =
7680 bits ...... (1) 20 mm to configure this with a shift register or memory
A chip area of about 2 is required, which is an area increase of about 30% from the perspective of the entire LSI. For this reason, there is a problem that the chip size does not fit within a predetermined size, which also causes a cost increase.

The present invention has been made to solve the above problems, and it is an object of the present invention to provide a data delay method capable of realizing a delay of a voice signal for a predetermined time without providing a new shift register or memory. To aim.

[0012]

In the data delay system according to the invention described in claim 1, the data A input from the first data source is written to an address which is sequentially incremented, and the data is written. In the occasional writable and readable memory in which the data A holding area moves in the address space by reading the data A from the sequentially incremented address at a constant speed, (i) The data B from the second data source is sequentially written in the area other than the data A holding area above while maintaining a constant address distance from the read address of the data A, and (ii) this data The data held at the address separated by a predetermined address distance from the write address of B in the direction opposite to the moving direction of the data A holding area. By reading B in synchronization with the writing of the data B, the data B holding area is moved in the address space in synchronization with the data A holding area, and a time delay corresponding to the predetermined address distance is provided. The data is added to the data B.

In the data delay method according to the second aspect of the present invention, when the writing speed and the reading speed of the data B are slower than the reading speed of the data A, the writing address and the reading address of the data B are set. It is characterized in that the moving speeds of the data A holding area and the data B holding area are synchronized by periodically skipping only the required address.

[0014]

In the data delay method according to the first aspect of the present invention, in the address space of the memory, the data B holding area moves in the address space in synchronization with the data A holding area while the write address of the data B is written. Data is read from an address separated by a predetermined distance from, and a time delay corresponding to the predetermined address distance is added to the data B.

In the data delay method according to the second aspect of the present invention, the write address and the read address of the data B are regularly set even if the write speed and the read speed of the data B are slower than the read speed of the data A. By physically skipping by the required address, the moving speeds of the data A holding area and the data B holding area are synchronized.

[0016]

Embodiments will be described in detail below with reference to the drawings.

FIG. 1 shows a main part of an audio signal decoder to which a data delay method according to an embodiment of the present invention is applied. This decoder includes a ternary / binary conversion circuit 11
8 bit digital signal 15 provided with
Is converted to three-value / two-value, and 3-bit binary data 13 is output. This 3-bit binary data 13 is sequentially stored in each of the registers R _{1 to} R ₂₅ of the register group 12 provided in the subsequent stage.
It is stored bit by bit.

A data selector 14 is provided at the subsequent stage of the register group 12 to select 1-bit or 8-bit data from the 75-bit data held in the register group 12 to select 8-bit data (hereinafter referred to as "8-bit data"). It is sent to the multiplexer 31 as 16).

On the other hand, the multiplexer 31 has a configuration shown in FIG.
Sampling frequency Fs from the DPCM decoder circuit that reproduces digital audio data based on the decoder output of
A 16-bit audio signal (surround signal) input at = 38 KHz is divided into upper and lower parts and input as 8-bit data (hereinafter referred to as surround data) 33. The multiplexer 31 selects either one of the main data 16 from the data selector 14 and the surround data 33 and inputs it to the memory 17.

The memory 17 is, for example, a 64 KB SRAM.
It is composed of (static RAM), and data is read and written under the control of the memory control circuit 18. The memory control circuit 18 uses the address bus 24
The memory 17 is controlled by the control bus 25.

The 8-bit read data 19 is read from the memory 17 and input to the multiplexer 32. The read data 19 includes data corresponding to the main data 16 and data corresponding to the surround data 33. The multiplexer 32 switches the output destination according to the data source, and the bit selector 21 or D (not shown). The signal is output to the / A conversion circuit. The bit selector selects 1 bit from the input 8-bit data and outputs it as serial bit data 22.

The operation of the audio signal decoder having the above configuration will be described.

[1] Processing of Main Data (Time Axis Expansion and Frame Deinterleaving) First, main data processing, that is, the multiplexer 3
The operation during the period when both 1 and 32 are switched to the main data side will be described.

The audio signal data multiplexed and transmitted from the transmitting side in the vertical blanking period of the analog video signal is transmitted by an A / D conversion circuit (not shown) at a frequency of 16.2 MHz shown in FIG. 6 (a). After being sampled with the basic clock of 1 to be converted into an 8-bit digital signal, the frequency is converted by a frequency conversion circuit (not shown) composed of a digital filter and the like, and the average 1 shown in FIG.
It is output in blocks of 2.15 MHz. 8-bit data 15 converted to 12.15 MHz in this way
Is input to the ternary / binary conversion circuit 11, where the ternary signal is discriminated using the two threshold levels.
Then, for every two samples of the ternary signal, the 3-bit binary data 13 is output, and the bit rate is 18.22.
It is 5 MHz.

On the transmitting side, voice data having a bit rate of 1.35 MHz is time-axis compressed to 18.225 MHz, and this amount of data is multiplexed in one vertical blanking period, so one vertical blanking period is performed. The bit amount of 2500 bits from the ternary / binary conversion circuit 11 is 750 in 3 bit units.
Output is performed 0 times.

Further, the ternary / binary conversion circuit 11 averages data of 3 bits each by 6.0 as shown in FIG. 6 (c).
The data is output at a rate of 75 MHz, and the output 3-bit data is sequentially held in the registers R _{1 to} R ₂₅ of the register group 12. At this time, control is performed so as to return to R ₁ after R ₂₅ .

The received bit sequence in this state is shown in FIG.
Is shown in. On the transmitting side, since the frame interleaving is performed every 25 frames, the bit number b ′ in the reception sequence matches the bit number b in the original sequence every 25 bits. Here, 1 frame means
It is 1350 bits and corresponds to a time of 1 ms. Therefore, on the reception sequence, the data in one frame on the original sequence is distributed over 54 blocks of 25 bits each. Therefore, as will be described later, in order to perform frame deinterleaving, it is convenient to write in the memory in units of 25 bits.

The data converted into the bit stream as shown in FIG. 2 by the ternary / binary conversion circuit 11 is stored in the register group 12 of 75 bits in total, and then stored in 25 bits.
It is read in bit units and written in the memory 17. However,
Since the memory 17 has an 8-bit parallel configuration, it is written in 8-bit units in writing.

Writing to the memory 17 is performed by dividing this 25-bit block into four groups of (1, 8, 8, 8) bits as shown in FIG. That is, first, the first write is performed by writing 7 to the _first bit 27 of the register R _1.
A dummy bit is added to the memory 17 and a total of 8 bits are written to the memory 17. Then, the second time, the 2 bits of the register R _{1 and} the 3 bits of R ₂ and R ₃ respectively, a total of 8 bits, are stored at the next timing. Write in 17. Thereafter, writing is performed in the same manner, and finally, the combination of (1, 8, 8, 8) bits is repeated three times, thereby writing data of 75 bits by writing 12 times in total. In this case, 1
Since 22,500-bit data arrives within the vertical blanking period of times, correspondingly, writing in 25-bit units is 9 times.
It is performed 00 times.

FIG. 4 shows a memory map of the memory 17. Since a memory having a capacity of 8 bits × 8K is assumed here, it has an address space of 0 to 8191. Then, this address space is divided into four, and the 1st, 5th, and 9th 1-bit + dummy 7-bit write (A write) of the above-described 12-time write starts from the address X, The writing (B writing) of each 8 bits of the 2nd, 6th and 10th times starts from X + 2048. 2nd, 6.10th 8-bit writing (B writing)
Starts at X + 2048. Also, the third, seventh and first
The first 8-bit write (C write) is X + 409
The 6th, 4th, 8th and 12th writing of each 8 bits (D writing) starts from X + 6656.

As shown in FIG. 4, when the starting address for writing the 22500-bit data that arrives during a certain vertical blanking period is X, the ending address of A writing corresponding to this group of data is X + 899. .. Therefore, the 22,500 bits that arrive in the next vertical blanking period must be written in the area having the start address of X + 900.
That is, X is added 900 for each vertical blanking period.

The area where the A writing is performed is continuous with the area where the B written data is read, and the area where the B writing is performed is the area where the C written data is read. In succession. Similarly, the memory 17 stores A, B, C, D
Each write of is configured on a loop.

On the other hand, the data storage in the 75-bit register group 12 is performed at a pitch of 6.075 MHz as described above, and is completed 25 times, but this takes at least about 4.1 μs. Then, after the 25th time, the first time writing is performed.

During one vertical blanking period, as described above, 22500-bit audio data is sent at 18.225 MHz, so the 75-bit register group 12 performs a store operation of 300 revolutions. This is not performed at a constant rhythm, but is 0.99 for each horizontal scanning line.
μs to 7.4 μs are interrupted. Therefore, the writing of the 75-bit register is also temporarily stopped on the way, and the operation becomes intermittent. Therefore, reading from the 75-bit register 12 and writing to the memory 17 are performed as follows.

(1) After writing to register R ₉ ... 1st to 4th reading (1A, 1B, 1C, 1D) (total 25 bits) (2) After writing to register R ₁₈ ... 5th to 8th Read for the second time (2A, 2B, 2C, 2D) (total 25 bits) (3) After writing to the register R ₂₅ ... Read for the 9th to 12th times (3A, 3B, 3C, 3D) (total 25 bits) The reading from the register group 12 is performed at a pitch of 4.05 MHz as shown in FIG. 6D, and the time required for reading 12 times is within 3 μs, which is faster than writing. Therefore, the reading is not delayed from the writing.

The timing of writing to and reading from the memory 17 is as shown in FIGS. 6 (d) and 6 (e). As shown in this figure, after writing the register R ₉ to the register group 12, writing to the memory 17 is performed at 1A to 1D at the timing of the frequency of 4.05 MHz. Then, after writing to the register R ₁₈ of the register group 12, writing to 2A to 2D is performed, and after writing to the register R ₂₅ , writing to 3A to 3D is performed.
These writings are performed at the same timing of 4.05 MHz as the reading from the register group 12 described above.
In addition, reading from the memory 17 is the same as that on the transmitting side.
It is performed constantly at a frequency of 5 MHz.

FIG. 5 shows the memory map in FIG. 4 more specifically. As shown in this figure, assuming that the leading address of A writing is X, the leading addresses of the areas of B writing, C writing, and D writing are (X + 204).
8), (X + 4096), and (X + 6656). Then, 1 of the bit number b'on the reception sequence shown in FIG.
Data up to 1350 bits (data for one frame on the reception sequence) is written in the area F shown in FIG. That is, “1” is written as 1-bit data A1 in A writing, and “1352”, “2703”, as 8-bit data B1 to B8 in B writing.
... is written. Hereinafter, the same applies to C writing and D writing. Then, by writing the 1-bit data A1 for A writing to the data D8 for D writing at the address (X + 53), data writing for 1350 bits per frame is completed.

The main data written in the memory 17 as described above is controlled by the memory control circuit 18.
Reading is performed in the following order. That is, for example, if the read is performed from the address X, the read start address of the area in which the A writing is performed becomes X, and 8 bits of this address X are read, and the bit selector 21 reads 1 bit out of them. Data "1" is selected and output as (A1). Next, corresponding to this address X, the start address (X + 204
8) 54 addresses ahead of address (X + 199
4) becomes the read start address of the written data, the 8-bit data (B1 to B8) is read from this address, and the data "2" that is the first bit (B1) of this is output.

Then, the previously read address (X + 19
94) 54 addresses ahead (X + 19
40 bits), 8 bits (B1 to B8) are read out, and data "3" which is the second bit (B2) among them is output.
In the same manner, the reading of the data written in B is completed. Similarly, the read start address of the C-written data is X + 3610, and the read start address of the D-written data is X + 5738. In this way, reading is sequentially performed up to the frame number (F-24) on the reception sequence. When the data "25" is read in this frame (F-24), the data "2" of 1 bit (A1) from the address (X + 1) of the A writing area of frame F is next read.
6 "is read out in this way. By sequentially reading out one bit from the written areas A to D while shifting forward by 54 addresses, the frame deinterleaved state is obtained. The data is read and the original signal sequence is reproduced.

The reading timing at this time is as follows.
As shown in FIG. 6 (e), the audio signal is transmitted at the transmission rate of 1.35 MHz, and the time axis expansion is performed.
That is, according to the present embodiment, by reading from the memory 17, the expansion of the time axis and the frame deinterleaving are simultaneously performed.

In this embodiment, the binary data output from the ternary / binary conversion circuit 11 is 3 bits.
And the bit interval for frame deinterleaving is 25
Considering that it is a bit, a 75-bit register that is the least common multiple of these is provided, and this is set to 25 bits for 3
Since each group is divided into four groups and each 25 bits is divided into four groups of (1,8,8,8) bits and written into the memory 17, each bit of the register group 12 and the bit width of the memory are 8 bits. It is possible to satisfactorily match the corresponding relations of each other, and the configuration becomes simple in design.

[2] Surround data processing (10 ms
Next, the processing of surround data, that is, the operation when the multiplexers 31 and 32 are switched to the surround data 33 and 34 side will be described.

Now, assuming that the audio mode is the A mode, the surround signal quantized at 32 KHz / 16 bits is input to the memory 17 as the surround data 33 (FIG. 1) with the upper 8 bits and the lower 8 bits alternately. To be done.
The memory control circuit generates a predetermined write address at any of the writable timings shown in FIG. 6 (f) and alternately writes the upper 8 bits and the lower 8 bits of the surround data in the memory 17. As shown in FIG. 7, the write address of the upper 8 bits at this time is (X + 8160) of the read area of the data written in A, and the write address of the lower 8 bits is the write address of the data written in B. (X in the read area
+1536). Here, X is an address to write the first audio data in the vertical blanking period. The write address of the surround data is 32 to 80 addresses behind the read address immediately before the main data.

The read address of the main data is moved in the increment direction by 54 addresses per 1 ms (one frame), as described in [1]. On the other hand, the sampling frequency of the surround signal in A mode is 32K.
Since it is Hz, the surround data write address is 1
It moves in the increment direction by 32 addresses per ms. Therefore, there is a speed difference of 22 addresses / 1 ms between them. In order to adjust this difference, the memory control circuit 1
8 performs write control by generating an address that skips 22 addresses each time 32 surround data are sequentially written.

The surround data thus written is read from an address 540 addresses after the write address. That is, 54 addresses / ms × 10
Since ms = 540 address, 10ms from writing
After the lapse of time, reading is performed, and a time delay of 10 ms is eventually performed.

As shown in FIG. 6 (f), the surround data write / read timings are the main data write timing (FIG. 6 (d)) and the read timing (FIG. 6 (e)). 16.2 Select a timing that does not overlap
This is performed in synchronization with the basic clock of KHz, and the frequency of access to the memory 17 is 8.1 MHz as a whole.
Therefore, the access interval is 120 ns or less, and a general SRAM can be sufficiently used.

Next, the generation mechanism of the above-described surround data write / read address will be described.

FIG. 8 shows a part of the address generator provided in the memory control circuit 18. This circuit is provided with an X counter 41 which counts the clock 42 of 54 KHz and outputs the count value to the latch circuit 43. The latch circuit 43 latches the output of the X counter 41 at the timing of the 1 KHz clock 47 input to the latch terminal L, and outputs it to the adder 44.

On the other hand, this circuit is provided with a counter 46 which counts the 32 KHz clock 48 and outputs the count value to the adder 44. This counter 46
Are reset at the timing of the above-mentioned 1 KHz clock 47.

The adder 44 adds the output of the latch circuit 43 and the output of the counter 46 and inputs them to the four constant adders 51 to 54 provided in parallel. These adders 5
1 to 54 are “816
0 "," 1536 "," 7620 ", and" 996 "are added and output, whereby the outputs of the adders 51 and 52 are the write addresses of the upper 8 bits and the lower 8 bits of the surround data 16 bits, respectively. And adders 53, 5
The outputs of 4 are read addresses of upper 8 bits and lower 8 bits of the surround data 16 bits, respectively.

The address thus created is
In synchronism with the switching of the multiplexers 31 and 32, switching is performed between an address created by a main data address generating unit (not shown) in the memory control circuit 18, and the address is supplied to the memory 17. As a result, the main data and surround data can be written and read as shown in FIG.
This is performed at the timings shown in (f) to (f), and the surround data is delayed by 10 ms.

[0052]

As described above, according to the present invention,
In the address space of the memory, since the data B holding area moves in the address space in synchronization with the data A holding area, the data is read from the address separated from the write address of the data B by a predetermined distance. The time delay corresponding to the predetermined address distance can be added to the data B. Therefore, even if the memory is provided for a certain data and used such that the used area moves, the moved blank area can be efficiently used and the memory can be saved. effective.

[Brief description of drawings]

FIG. 1 is a block diagram showing an audio signal decoder according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a correspondence relationship between bit numbers on a reception sequence and bit numbers on an original sequence.

FIG. 3 is an explanatory diagram showing a timing of reading from a register.

FIG. 4 is an explanatory diagram showing a memory map for explaining a write operation and a read operation with respect to the memory.

FIG. 5 is an explanatory diagram showing details of a memory map.

FIG. 6 is a timing chart showing the timing of writing and reading to and from the memory.

FIG. 7 is an explanatory diagram showing a relationship between a surround data write / read area and a main data read area.

FIG. 8 is a block diagram showing an address generation unit that generates a write / read address of surround data.

[Explanation of symbols]

 11 3-value / 2-value conversion circuit 12 Register group 14 Data selector 16 Main data 17 Memory 18 Memory control circuit 21 Bit selector 31, 32 Multiplexer 33 Surround data 41 X counter 43 Latch circuit 44 Adder 46 Counter 51-54 Constant adder

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04S 7/00 Z 8421-5H

Claims (2)

[Claims] 1. A data A input from a first data source is written to an address which is sequentially incremented, and the written data A is read from the sequentially incremented address at a constant speed, whereby In the writable and readable memory where the A holding area moves in the address space, in the area other than the data A holding area in the address space of the writable and readable memory as needed, a fixed address from the read address of the data A Second while maintaining the distance
While sequentially writing the data B from the data source, the data B held at the address separated from the write address of the data B by a predetermined address distance in the direction opposite to the moving direction of the data A holding area, By reading the data B in synchronism with the writing of the data B, the data B holding area is moved in the address space in synchronism with the data A holding area, and a time delay corresponding to the predetermined address distance is added to the data B. A data delay method characterized by being added to B. 2. When the writing speed and the reading speed of the data B are slower than the reading speed of the data A,
2. The write address and the read address of the data B are periodically skipped by a required address so that the moving speeds of the data A holding area and the data B holding area are synchronized with each other. Data delay method.