JPH05335311A - Flip chip semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve contact performance with an inspection substrate by arranging the height of ends of solder bump to evaluate electric characteristics in the condition of a chip. CONSTITUTION:An integrated circuit (IC) 1 is mounted on a glass board 6 whose flat side to contact with edges of a solder bump 2 of the IC is finished under + or -mum. A dead-weight 7 is arranged on the rear of the IC 1. In such condition, heat treatment is conducted in a flow furnace, thereby the solder bump 2 can be formed as a solder bump 21 having flat side at the edges. It is also possible for the IC as a single unit to evaluate electric characteristics by contacting electrically with an inspection substrate 3 in the pressed condition.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip chip semiconductor device and a method for manufacturing the same, and more particularly to a solder bump shape and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, due to miniaturization in the manufacturing technology of semiconductor ICs (hereinafter referred to as ICs) and the accompanying trend toward higher integration, higher functionality and more terminals, the connection terminals of these ICs and circuit boards There is also a demand for miniaturization and multi-terminal connection with the connection terminals.

The wire bonding method, the TAB method, the flip chip method and the like are known as the method of connecting the IC and the circuit board, and the flip chip method is suitable as a high density mounting method of an IC having multiple terminals. .. This is because in the flip chip method, the connection terminals can be provided on the entire surface of the IC, and the number of terminals can be easily increased as compared with the wire bond method or the TAB method in which the connection terminals are provided on the peripheral portion of the IC surface. Is. Further, the flip chip method has excellent electrical characteristics because the wiring length for connection is short.

For these reasons, a flip-chip method has been studied or put into practical use as one of the mounting methods, especially as a mounting method for large-sized computers, for 10 years ago, and recently, it has also been considered as a mounting method for liquid crystal display electronic parts. Has been done. Conventionally, the flip-chip method has been a method in which, for example, solder bumps are formed on a pad portion formed by patterning on the surface of an IC by a plating method or a solder ball supplying method. Regarding the gold ball bump formation and the solder bump shape by the bonding method, various researches and experiments have been conducted such as changing from spherical shape to drum shape, or forming multiple bumps via polyimide film.

Conventionally, flip-chip type semiconductor devices are electrically evaluated for DC characteristics and the like in a wafer state before being cut into chips. However, for electrical evaluation of AC characteristics and the like, the chip is mounted. It is performed after flip-chip bonding to a package or a circuit board to form a final product. Therefore, if flip chip bonding is performed and then the characteristics are evaluated, and if there is something wrong with the chip, it is very difficult to remove (repair) this chip, and it is also very difficult to regenerate the substrate on which the chip is mounted. Is.

In general, since it is inevitable that a small amount of defective products will be mixed in the IC as the degree of integration increases, in an expensive IC, the added value is still low, that is, the package is packaged as much as possible. In addition, in a flip chip IC, it is desired that the characteristics can be evaluated in the state before the flip chip connection, which is close to permanent connection.

As described above, the electrical evaluation of the conventional flip chip is performed in the state of the product with the highest added value by performing the flip chip bonding on the package or the circuit board on which the chip is mounted, so that there is a chip abnormality. In that case, there was a problem that the loss in the manufacturing process was large and the cost of the product was greatly affected.

[0008]

In the flip-chip method, as described above, conventionally, the final characteristic evaluation is performed after the flip-chip bonding is performed. Therefore, there is a problem that the loss in the manufacturing process is large when the chip is abnormal.

These causes are because it is difficult to sufficiently perform final electrical characteristic evaluation in a chip state before performing flip chip bonding. That is, for example, in the process of forming the solder bumps 2 by a plating method or the like in a wafer state as shown in the cross-sectional view of FIG. 3, the height of the solder bumps 2 varies in the wafer or in one IC 1, In the chip state, there is a problem that electrical conduction with the pad of the inspection substrate 3 cannot be sufficiently obtained only by applying pressure.

As another method, as shown in the sectional view of FIG. 4, for example, a conductive elastic sheet 4 or the like is interposed between the IC 1 and the inspection substrate 3, and the solder bumps 2 of the IC 1 and the inspection substrate 3 are separated. There is a method of obtaining electrical conduction only by applying pressure to the pad. In this method, since the conductive elastic sheet can absorb the slight difference in height between the solder bumps of the IC, the contact between the solder bump and the pad of the inspection substrate can be completely obtained.

However, the conductive resistance of the conductive elastic sheet is large, for example, about several Ω to several hundred Ω, and when the IC is a power IC or the like, the conductive elastic sheet generates heat due to a large current at the time of inspection, and its physical property value is increased. Deterioration and the difference in the height of the solder bumps causes a difference in the contact resistance between each solder bump and the conductive elastic sheet. In particular, in the case of a multi-terminal IC, complete contact is required. In order to obtain it, a large pressure, for example, a pressure of about 4.5 kg to 6 kg is required for a 300-pin IC, and there is a problem that the IC and the inspection board may be damaged.

Because of these problems, as shown in the sectional view of FIG. 5, solder bumps of the IC are melted on the inspection substrate 3 or the circuit substrate to perform flip chip bonding, and the final electrical characteristics are obtained. I was doing an evaluation.

[0013]

A flip-chip semiconductor device and a method of manufacturing the same according to the present invention are a flip-chip semiconductor device in which a plurality of solder bumps provided on the surface of an IC are formed with flat surfaces at their tips. The manufacturing method is a method in which a flat plate is arranged at the tip of the solder bump and reflow is performed in that state to form a flat surface at the tip of the solder bump.

Further, the IC is electrically contacted in a pressurized state to a test substrate having a plurality of electrode patterns provided directly on the tip of the solder bump of the IC or via a conductive elastic sheet, and finally. Since the electrical characteristics are evaluated,
It is possible to solve the problems of the conventional flip chip method.

[0015]

The present invention will be described below with reference to the drawings. 1A and 1B are cross-sectional views showing the manufacturing process of the first embodiment of the present invention.

In FIG. 1A, 1 is a semiconductor IC, 2 is a solder bump, 6 is a glass plate, and 7 is a weight. The solder bumps 2 are formed in a wafer state by a plating method as described below, for example. For example, Cr, Pd,
A thin film is formed in the order of Cu, a resist having an opening is arranged in the electrode portion by processing such as resist coating, exposure, and development, and a solder bump is formed in this opening by electrolytic plating.
Next, resist peeling, Cr, Pd, C other than solder bumps
The semi-spherical solder bumps 2 are formed by removing u and finally performing wet back treatment of the solder bumps.

In the solder bumps manufactured by this solder bump forming process, the height of the solder bumps 2 within one IC 1 is, for example, ± 10 to 30 with respect to an average of 100 μm.
There is a variation of μm. Therefore, after cutting the wafer into chips, the solder bumps 2 of the IC corresponding to the chip size
IC1 is inserted into, for example, a quartz glass plate 6 whose flatness of the surface in contact with the tip of the is finished to be ± 1 μm or less.
Place the weight 7 on the back surface of the. In this state, in a reflow furnace using an inert gas such as nitrogen, for example, MAX230
The solder bumps 2 are formed on the solder bumps 2 by applying a heat treatment of 2 to 4 minutes at a temperature of 190 ° C to 230 ° C.
It is formed in the shape shown in FIG.

The shape of the solder bump 21 is the glass plate 6
Can be formed arbitrarily according to the height dimension h of the edge portion 10. For example, if the pitch of the solder bumps is 300 μm and the height h of the solder bumps is 100 μm, the flat surface of the tip end of the solder bumps has a diameter of 50 to 50 μm. It is obtained in a size of 60 μm, and the variation in height is formed within ± 1 μm.
During processing in this reflow furnace, flux may be applied to the solder bumps if necessary. According to the present embodiment, it is possible to easily reduce the height variation of the flip-chip solder bump portion manufactured by the conventional manufacturing method to an extremely small value.

Flip chip IC1 manufactured by this manufacturing method
As shown in FIG. 1C, the solder bumps 21 are aligned with the electrodes 5 formed on the inspection substrate 3 and brought into a pressurized state, whereby sufficient electrical conduction can be obtained. .. Since it is preferable that the height variation of the electrodes 5 on the inspection substrate 3 is also small, when the inspection substrate 3 is made of alumina ceramic, for example, a polishing process is performed before the electrodes 5 are formed, and then the screen printing method is performed. The electrode 5 is formed by vapor deposition, plating, etc., and the height variation of the electrode 5 is ± 1 μm.
This needs to be formed below, but this can be realized by the conventional technique.

Here, the height of the solder bump 21 of the IC 1 is set to 1
If the diameter of the flat surface is 00 μm and the diameter of the flat surface is 60 μm, applying 5 g to one solder bump deforms the solder bump by about 1 μm.
Electrical connection between the inspection substrate and the IC can be obtained with a low load of about 5 kg to 3 kg. Further, in an IC other than the power IC, which does not require a large current at the time of inspection, the conductive elastic sheet 4 as shown in FIG. 1D may be interposed between the IC and the inspection substrate 3.

By manufacturing an IC having a solder bump shape as described above and combining it with an inspection substrate, I can be manufactured before the final flip chip bonding.
It becomes possible to perform final electrical characteristic evaluation with C alone. Conventionally, a flip-chip IC has been electrically evaluated after flip-chip bonding. Therefore, when a defective product is produced, repair or the like is difficult and productivity is extremely deteriorated.
The manufacturing method solves this problem, and has a great effect on improving the manufacturing efficiency and reliability of the flip chip IC.

2A to 2F are sectional views showing the manufacturing process of the second embodiment of the present invention. In the figure, 1 is a semiconductor IC, 22 and 23 are solder bumps, 61 is a glass plate, 71 is a weight, 8 is a resist, 9 is an electrode on the semiconductor IC, 32 is a vacuum suction port, 31 is an inspection shell, Reference numeral 10 is an inspection prober, and a method of forming the solder bumps 22 and 23 is shown in FIGS. The solder bumps 22 are formed in a wafer state by a plating method or the like, and FIG. (A) shows a pre-stage of solder bump formation. Electrode 9
A resist 8 having an opening is disposed around the periphery of the substrate by exposure to a phenomenon or the like, and then solder bumps 22 are formed by a plating method as shown in FIG. One IC at this stage
Among them, the height of the solder bump varies.

FIG. 3C shows the state after the resist is peeled off, and then the IC is cut into chips as shown in FIG. 2D.
IC solder bumps 22 corresponding to this chip size
Inserted into, for example, a quartz glass plate 61 whose flatness of the surface in contact with the tip end of is 1 μm or less, and a weight 71 is arranged on the back surface of the IC 1. By performing heat treatment in a reflow furnace using an inert gas in this state, the solder bumps 22 are formed into the solder bumps 23 as shown in FIG.

In this manufacturing method, the wet back process of the solder bumps after the resist peeling and the flat surface forming process of the solder bumps are simultaneously performed. According to the present embodiment, it is possible to easily reduce the height variation of the flip-chip solder bump portion manufactured by the conventional manufacturing method and without increasing the number of steps.

Flip chip IC1 manufactured by this method
Using the inspection substrate 3 shown in FIGS. 1 (c) and 1 (d) in the first embodiment of the present invention, all the electrical components are left as they are before the final flip-chip bonding. Characterization can be carried out. An inspection method that does not use an inspection substrate is also possible. For example, an IC is mounted on an inspection jig 31 having a vacuum suction port 32 as shown in FIG.
1 is adsorbed and the inspection prober 10 is brought into direct contact with the solder bumps 23 to evaluate the electrical characteristics.

When the height of the solder bump is 100 μm, the flat surface of the solder bump surface has a diameter of 50 to 60 μm.
This is because the solder bump shape forming method that can obtain the area of the solder bump is adopted. These inspection methods use the solder bump shape size, the number of solder bumps, the IC chip size, and the large current I
It can be used properly depending on whether it is C or not.

[0027]

As described above, the present invention is a flip chip semiconductor device in which a flat surface is formed at the tip of a plurality of solder bumps provided on the surface of an IC, and the manufacturing method thereof is a solder bump. Is a method of forming a flat surface on the tip of the solder bump by disposing a flat plate at the tip of the solder bump, applying pressure, and then performing reflow in that state.

Further, the IC is electrically contacted with the inspection substrate provided with a plurality of electrode patterns corresponding to the two solder bumps in a pressurized state, so that the final evaluation of the electrical characteristics of the IC alone can be performed. Since it can be carried out as it is, the deterioration of productivity caused by the electrical characteristic evaluation after the conventional final flip-chip bonding is improved, and the reliability is greatly improved.

[Brief description of drawings]

FIG. 1 is a process diagram showing a manufacturing method of a first embodiment of the present invention, and FIGS. 1 (a) to 1 (d) are cross-sectional views, respectively.

FIG. 2 is a process drawing showing the manufacturing method of the second embodiment of the present invention, and FIGS. 2 (a) to 2 (f) are sectional views.

FIG. 3 is a cross-sectional view showing a conventional technique.

FIG. 4 is a cross-sectional view showing another example of the conventional technique.

FIG. 5 is a cross-sectional view illustrating a conventional manufacturing method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor IC 2,21,22,23 Solder bump 3 Inspection substrate 4 Conductive elastic sheet 5 Electrode 6,61 Glass plate 7,71 Weight 8 Resist 9 Electrode 10 Inspection prober 31 Inspection recovery shell 32 Vacuum suction port

Claims (4)

[Claims] 1. A flip-chip semiconductor device, wherein a plurality of solder bumps provided on the flip-chip semiconductor device are formed with flat surfaces at respective tip portions of the solder bumps so as to have the same height. 2. A flip characterized by forming a flat surface on the tip of the solder bump by pressing a flat plate against the tip of a plurality of solder bumps provided on the flip chip semiconductor device and performing reflow. Manufacturing method of chip semiconductor device. 3. A plurality of electrode patterns provided on the inspection substrate and a plurality of solder bump tips are simultaneously brought into pressure contact with each other directly or via a conductive elastic sheet to perform electrical evaluation. A method for manufacturing a flip-chip semiconductor device having a feature. 4. A method of manufacturing a flip-chip semiconductor device, wherein an inspection probe is directly brought into contact with a flat surface of a tip portion of a solder bump to perform electrical evaluation.