JPH05343621A - Transistor provided with current detection function - Google Patents

Abstract

PURPOSE:To obtain a transistor provided with current detection function capable of precise current detection, which is the transistor constituted of PNP type multibase.multiemitter structure. CONSTITUTION:On the surface of a silicon oxide film 12 obtained by oxidizing the surface of a P-type silicon substrate 11 positioned between an N-type main base region 13 and an N-type sense base region 14, a P<+> type poly silicon film 17 is formed, and further the P<+> type poly silicon film 17 is electrically connected with the N-type main base region 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor with a current detection function, and more specifically, a multi-base transistor.
The present invention relates to a transistor with a current detection function having a multi-emitter structure.

[0002]

2. Description of the Related Art Generally, due to the nature of its application, a transistor used for high power switching, high power amplification, etc., is destroyed by an overcurrent that exceeds the rated value. It is equipped with a function to prevent it from happening. And as an example, a current detection using a multi-base / multi-emitter structure in which a sense transistor section for current detection is provided together with a main transistor section for flowing a main current, and the occurrence of an overcurrent is detected by this sense transistor section Functional transistors are known.

FIG. 5 is a vertical cross-sectional view showing the internal structure of a conventional PNP type transistor with a current detecting function, which adopts a multi-base / multi-emitter structure. As shown in the figure,
A conventional transistor with a current detecting function is configured with a P-type silicon substrate 1 containing P-type impurities in a predetermined concentration as a base material. However, this P-type silicon substrate 1
It is obtained by performing epitaxial growth on a P-type silicon wafer which is a raw material. The P-type silicon substrate 1 in such a state substantially constitutes the P-type collector region of the transistor with the current detection function, and the collector terminal C is drawn out from the back surface of the P-type silicon substrate 1. Has been.

On the other hand, in the surface layer portion of the P-type silicon substrate 1, an N-type main base region 2 containing an N-type impurity in a predetermined concentration is formed with a predetermined depth.
In the surface layer portion of the N-type main base region 2, a P ⁺ -type main emitter region 3 containing a high concentration of P-type impurities is formed with a depth shallower than the depth of the N-type main base region 2 described above. There is. The main base terminal B _M is drawn from the surface of the N-type main base region 2 and the main emitter terminal E _M is drawn from the surface of the P ⁺ -type main emitter region 3, respectively. A PNP type main transistor part T _M for flowing a main current is formed in the transistor with a current detection function by the P type collector region), the N type main base region 2 and the P ⁺ type main emitter region 3. become.

On the other hand, in the surface layer portion of the P-type silicon substrate 1 on the side of the main transistor portion T _M (on the left side of the figure), the N-type sense base region 4 containing N-type impurities at a predetermined concentration is first. Of the N-type main base region 2, and the surface layer portion of the N-type sense base region 4 further contains P-type impurities at a high concentration.
^{The +} type sense emitter region 5 is formed in the same form as the P ⁺ type main emitter region 3 described above. Then, as in the case of the main transistor portion T _M described above, the sense base terminal B can be seen from the surface of the N-type sense base region 4.
_S is, P ⁺ -type sense emitter from the surface region 5 is led sense emitter terminal E _S, respectively, over P-type silicon substrate 1 (P-type collector region), N-type sense base region 4 and the P ⁺ -type With the sense emitter region 5, a PNP type sense transistor section T _S for current detection
Will be configured.

The silicon oxide film 6 selectively provided on the surface of the P-type silicon substrate 1 has the above-described N-type main base region 2, P ⁺ -type main emitter region 3, N-type sense base region 4 and It also serves as a mask when the P ⁺ type sense emitter region 5 is partially formed by thermal diffusion of impurities or ion implantation.

Here, a PNP having the main transistor section T _M and the sense transistor section T _S constructed in this way
In addition, the current detection function is added only when the sense resistor R _S having a predetermined resistance value is connected between the main emitter terminal E _M and the sense emitter terminal E _S of the type-type transistor with current detection function. become. That is, when the transistor with the current detection function actually operates, the sense resistor R
The terminal voltage of _S is measured, and the current is detected by the terminal voltage based on the measured value. And by the above, PNP which adopts a multi-base multi-emitter structure
Type transistor with a current detection function is configured.

FIG. 6 is a vertical cross-sectional view showing the internal structure of an NPN-type transistor with a current detecting function, which has a conventional multi-base / multi-emitter structure and is formed with the conductivity type opposite to that of the transistor shown in FIG. It is a figure.

As shown in FIG.
N-type silicon forming the N-type collector region of the entire transistor
The P-type main base region is provided on one surface layer of the control board 21.
22 is formed on the surface of the P-type main base region 22.
Is N⁺A mold main emitter region 23 is formed. So
Then, on the other surface layer portion of the N type silicon substrate 21, a P type
The sense base region 24 is formed, and the P-type sense base region is formed.
N on the surface of the area 24 ⁺Type sense emitter region 25 is shaped
Is made.

The N-type silicon substrate 21 (N-type collector region), P-type main base region 22 and N ⁺ -type main emitter region 23 described above constitute an NPN-type main transistor portion T _M , Silicon substrate 21, P-type sense base region 24 and N ⁺ -type sense emitter region 25
Thus, the NPN type sense transistor section T _S is configured.

In addition, an N-type substrate having various semiconductor regions is formed.
There is a contact hole on the surface of the recon substrate 21.
A silicon oxide film 26 is selectively installed. That
Of the upper surface of the P-type main base region 22 and its periphery.
The main base electrode 27 is covered with N by covering the recon oxide film 26.
⁺Of the upper surface of the mold main emitter region 23 and its periphery
The main emitter electrode 28 is covered with P
Silicon on the upper surface of and around the sense base region 24
The sense base electrode 29 is covered with N by covering the oxide film 26. ⁺Type
The upper surface of the sense emitter region 25 and its periphery silicon oxidation
Each of the sense emitter electrodes 30 covering the film 26 is made of aluminum.
It is installed using N.

A main base terminal B _M is connected from the main base electrode 27, a main emitter terminal E _M is connected from the main emitter electrode 28, a sense base electrode B _S is connected from the sense base electrode 29, and a sense emitter is connected from the sense emitter electrode 30. The terminals E _S are respectively drawn out, and the sense emitter terminal E _S and the main emitter terminal E _M are connected to a common emitter terminal E with a sense resistor R _S having a predetermined resistance value connected between them. The collector terminal C is led out from the back surface of the N-type silicon substrate 21.

As described above, an NPN-type transistor with a current detecting function having a multi-base / multi-emitter structure is constructed, the terminal voltage of the sense resistor R _S is measured, and the current is detected by the terminal voltage based on the measured value. It

[0014]

By the way, a PN adopting the conventional multi-base / multi-emitter structure shown in FIG.
In the P-type transistor with current detection function, the surface concentration of P-type impurities of the P-type silicon substrate 1 is low, and
Since the surface state density Q _{SS at} the interface between the silicon substrate 1 and the silicon oxide film 6 provided on the surface of the silicon substrate 1 usually takes a positive value, the vicinity of the surface of the P-type silicon substrate 1 is changed from P-type to N-type. It has been reversed to. Therefore, N
A depletion type parasitic N channel MOS transistor (not shown) is generated near the surface of the P type silicon substrate 1 located between the type main base region 2 and the N type sense base region 4.

As a result, when the use form of the current detecting transistor causes a potential difference between the N-type main base region 2 and the N-type sense base region 4, for example, at turn-on and turn-off. , And between them, the depletion-type parasitic N-channel M described above.
Unnecessary leak current flows through the OS transistor, and along with this, the base currents flowing through the N-type main base region 2 and the N-type sense base region 4 also change. With this, it is not possible to expect high-precision current detection by the transistor with the current detection function, and it is impossible to sufficiently cope with an overcurrent that exceeds the rated value.

In the above description, the normal case where the surface level density Q _SS takes a positive value has been exemplified, but there are cases where variations occur in the manufacturing process and the surface level density Q _SS takes a negative value.

In such a case, the NPN shown in FIG.
In the N-type transistor with a current detection function, the vicinity of the surface of the N-type silicon substrate 21 located between the P-type main base region 22 and the P-type sense base region 24 is in a state of being inverted from N-type to P-type, The enhancement type parasitic MOS transistor may become a depletion type P-channel MOS transistor.

Therefore, for example, when a potential difference occurs between the P-type main base region 22 and the P-type sense base region 24 at the time of turn-on and turn-off, it transiently passes through the above-mentioned depletion-type parasitic P-channel MOS transistor. Unnecessary leak current may flow, and eventually, as in the conventional example shown in FIG. 5, accurate current detection may not be possible.

The present invention has been made in view of such circumstances, and an object thereof is to provide a transistor with a current detection function capable of detecting a current with high accuracy.

[0020]

According to a first aspect of the invention, a main base region and a sense base region containing N-type impurities are provided at a predetermined distance on a surface layer portion of a silicon substrate containing P-type impurities. The main base region and the sense base region have a P-type impurity at a concentration sufficiently higher than the P-type impurity concentration at the surface layer of the silicon substrate. In a transistor with a current detection function formed by forming an emitter region and a sense emitter region at a predetermined depth, a silicon oxide obtained by oxidizing the surface of the silicon substrate located between the main base region and the sense base region. A polysilicon film containing a P-type impurity is formed on the surface of the film, and the polysilicon film has a predetermined semiconductor region at a ground potential. It is characterized by comprising electrically connected to the base region.

According to a second aspect of the invention, the main base region and the sense base region containing the second conductivity type impurities are separated by a predetermined distance from the surface layer of the silicon substrate containing the first conductivity type impurity. And a first conductivity type having a concentration sufficiently higher than the concentration of the first conductivity type impurities in the surface layer portion of the silicon substrate in the surface layer portions of the main base region and the sense base region. In a transistor with a current detection function formed by forming a main emitter region and a sense emitter region containing impurities at a predetermined depth, a surface of the silicon substrate located between the main base region and the sense base region is formed. An electrode is formed on the surface of a silicon oxide film obtained by oxidation, and the electrode is electrically connected to a power supply.

Further, a third aspect of the present invention is that a main base region and a sense base region containing a second conductivity type impurity are separated by a predetermined distance from a surface layer portion of a silicon substrate containing the first conductivity type impurity. And a first conductivity type having a concentration sufficiently higher than the concentration of the first conductivity type impurities in the surface layer portion of the silicon substrate in the surface layer portions of the main base region and the sense base region. A transistor with a current detection function, in which a main emitter region and a sense emitter region containing impurities are formed at a predetermined depth, and a main base electrode, a sense base electrode, a main emitter electrode and a sense emitter electrode are formed on the main emitter region and the sense emitter region. , A surface obtained by oxidizing the surface of the silicon substrate located between the main base region and the sense base region. An electrode formed on the surface of the con oxide film,
The electrode is short-circuited to the main base electrode or the sense base electrode.

[0023]

In the first aspect of the invention, the polysilicon film formed above the silicon substrate located between the main base region and the sense base region causes the threshold voltage V _{TH of the} region to have a positive value, Conventionally, the depletion type parasitic N-channel MOS transistor generated in that region becomes the enhancement type. As a result, even in a use mode in which a potential difference is generated between the main base region and the sense base region, an unnecessary leak current does not flow between them, and accordingly, the main base region and the sense base region The base current flowing in the region is stable without changing and the current can be detected with high accuracy.

In the second invention, since the electrode formed above the silicon substrate located between the main base region and the sense base region is electrically connected to the power supply,
Conventionally, the parasitic MOS transistor generated in that region returns from the depletion type to the enhancement type.
Therefore, as in the first aspect, unnecessary leak current does not flow, and highly accurate current detection can be performed.

In the third invention, the electrode formed above the silicon substrate located between the main base region and the sense base region is short-circuited to the main base electrode or the sense base electrode. The parasitic MOS transistor generated in the above step returns from the depletion type to the enhancement type. Therefore, as in the first and second inventions, unnecessary leak current does not flow, and high-precision current detection becomes possible.

[0026]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a PNP adopting a multi-base / multi-emitter structure according to a first embodiment of the present invention.
FIG. 3 is a vertical cross-sectional view showing the internal structure of a positive-type transistor with a current detection function. Most of the parts shown in this figure are common to the parts already shown in FIG. 5, but here, the structure of the embodiment will be described along with a general manufacturing process, For that reason, the respective parts shown in this figure will be denoted by reference numerals different from the reference numerals of the respective parts shown in FIG.

As shown in the figure, the transistor with a current detecting function of this embodiment is obtained by performing epitaxial growth on a P-type silicon wafer containing P-type impurities in a predetermined concentration as in the conventional case. The obtained P-type silicon substrate 11 is used as a base material. The P-type silicon substrate 11 in such a state substantially constitutes the P-type collector region of the entire transistor with current detection function.

Next, on the surface layer portion of the P-type silicon substrate 11, the silicon oxide film 12 obtained by oxidizing the surface of the P-type silicon substrate 11 is selectively removed at a predetermined distance, and the silicon oxide film 12 is further removed. The N-type main base region 13 containing the N-type impurity in a predetermined concentration is formed by performing thermal diffusion or ion implantation of the N-type impurity on the removed portion.
And the N-type sense base region 14 are simultaneously formed at a predetermined depth. Note that the state near the surface of the P-type silicon substrate 11 where the silicon oxide film 12 was present on the surface when the N-type main base region 13 and the N-type sense base region 14 were formed is at this point the P-type silicon substrate. It has already been inverted from P-type to N-type due to the influence of the surface level density Q _SS at the interface between the film 11 and the silicon oxide film 12.

Next, the P type silicon substrate 1 including the surfaces of the N type main base region 13 and the N type sense base region 14 is formed.
A silicon oxide film 12 is provided on the surface of 1.
A polysilicon material is deposited on the surface of the silicon oxide film 12 by the CVD method or the like. And first, N
The polysilicon material is removed, leaving a portion above the P-type silicon substrate 11 located between the type main base region 13 and the N-type sense base region 14, and subsequently, the silicon exposed by the removal of the polysilicon material. Oxide film 12
Are selectively removed with respect to the portions located on the respective surfaces of the N-type main base region 13 and the N-type sense base region 14. However, when removing the polysilicon material, for example, it is preferable that the portion that surrounds the N-type sense base region 14 in a circular shape remains.

Next, in this state, the P-type impurities are thermally diffused or ion-implanted, so that the P-type impurities are added to the surface layer portions of the N-type main base region 13 and the N-type sense base region 14, respectively. A P ⁺ -type main emitter region 1 containing both P-type impurities having a concentration sufficiently higher than the concentration of P-type impurities in the surface layer portion of the silicon substrate 11.
5 and the P ⁺ -type sense emitter region 16 are formed at a depth shallower than the depths of the N-type main base region 13 and the N-type sense base region 14 described above, and at the same time, the polysilicon material forming the circular shape is P ⁺ Type main emitter region 15
And it is denatured to the P ⁺ -type polysilicon film 17 comprising a P-type impurity equivalent concentration and the concentration of P type impurity in the P ⁺ -type sense emitter region 16. And P ⁺
The type polysilicon film 17 is further electrically connected to the N type main base region 13. The P ⁺ type polysilicon film 17 may be connected to the N type main base region 13 as well as the N type sense base region 14 and the P ⁺ type polysilicon film 17, for example.
It may be connected to the type main emitter region 15 or the P ⁺ type sense emitter region 16 or the like.

As a result, the state in the vicinity of the surface of the P-type silicon substrate 11 which has been inverted from P-type to N-type before the P ⁺ -type polysilicon film 17 is formed is the P ⁺ -type polysilicon film 17 The threshold voltage V _TH has a positive value in the vicinity of the region in which the depletion type is formed, and the depletion type parasitic N-channel MOS transistor conventionally generated in that region becomes the enhancement type. As a result, even if a potential difference may occur between the N-type main base region 13 and the N-type sense base region 14, an unnecessary leak current does not flow between them, and accordingly, the N-type main base region 13 Both the base currents flowing through the base region 13 and the N-type sense base region 14 become stable. In addition, since the P ⁺ -type polysilicon film 17 is formed at the same time as the P ⁺ -type main emitter region 15 and the P ⁺ -type sense emitter region 16, the process becomes particularly complicated by adding it. There is no.

Next, when various semiconductor regions are formed in this way, the silicon oxide film 12 provided on the surface of each of the N-type main base region 13 and the N-type sense base region 14 is selectively removed. As a result, the main base terminal B _M is drawn from the surface of the N-type main base region 13 that is exposed to the outside, and the sense base terminal B _S is drawn from the surface of the N-type sense base region 14.
Further, from the surface of the P ⁺ type main emitter region 15 which is already exposed to the outside in the previous process, the main emitter terminal E
_M , a sense emitter terminal E _S from the surface of the P ⁺ type sense emitter region 16 and a collector terminal C from the back surface of the P type silicon substrate 11, respectively, and further, a main emitter terminal E _M and a sense emitter terminal E. A sense resistor R _S having a predetermined resistance value is connected between _S and _S.

Then, as described above, the P-type silicon substrate 1
1 (P-type collector region), N-type main base region 13 and P ⁺ -type main emitter region 15 together with a PNP-type main transistor portion T _M for flowing a main current, a P-type silicon substrate 11 (P-type collector region), A PN having a multi-base / multi-emitter structure including a PNP type sense transistor section T _S for current detection, which is composed of an N type sense base area 14 and a P ⁺ type sense emitter area 16.
A P-type transistor with a current detection function is configured.

As described above, according to the first embodiment, the P ⁺ -type polysilicon formed above the P-type silicon substrate 11 located between the N-type main base region 13 and the N-type sense base region 14. Due to the action of the silicon film 17, the depletion type parasitic N-channel MOS transistor which has been conventionally formed in that region becomes an enhancement type. As a result, even if there is a potential difference between the main base region and the sense base region, no unnecessary leak current flows between them, and as a result, the main base region and the sense base region do not flow. Both the base currents that flow are stable and high-precision current detection becomes possible. Further, in forming the P ⁺ -type polysilicon film 17, the steps are not particularly complicated.

FIG. 2 is a vertical cross-sectional view showing the internal structure of an NPN type transistor with a current detecting function having a multi-base / multi-emitter structure according to the second embodiment of the present invention.
Of the parts shown in this figure, the same parts as the parts of the conventional example shown in FIG. 6 are denoted by the same reference numerals to omit redundant description, and the manufacturing process will not be particularly described in detail.

In this embodiment, aluminum is used for the P-type main base region 22, the P-sense base region 24 and the silicon oxide film 26 provided on the N-type silicon substrate 21 located between these regions. The gate electrode 31 is installed. The gate electrode 31 is provided with a pad (not shown) on the upper portion thereof, and the gate terminal G pulled out from the upper portion of the pad is connected to a power source V _CC (for example, about 12V) by wire bonding or the like.

Therefore, for example, a variation occurs in a certain process of the manufacturing process, and the N-type silicon substrate 21 located between the P-type main base region 22 and the P-type sense base region 24 and the silicon oxide film 26 located on the surface thereof. The surface level density Q _{SS at} the interface with and becomes a negative value, and the vicinity of the surface of the N-type silicon substrate 21 is inverted from N-type to P-type, and a depletion-type parasitic P-channel MOS transistor is generated. even, the gate electrode 31 is in the power supply V _CC and the equipotential is connected to a power supply V _CC (approximately 12V). Therefore, the influence due to the negative surface state density Q _SS is canceled out, and the inverted state near the surface of the N-type silicon substrate 21 is eliminated.

That is, the threshold voltage V _TH of the parasitic P-channel MOS transistor is changed by the negative value of the surface state density Q _SS to be the depletion type. The parasitic P-channel MOS transistor is changed to a normal enhancement type. After returning, the P-channel MOS transistor remains in the off state.

As described above, according to the second embodiment, the parasitic MO due to the action of the gate electrode 31 connected to the power source V _CC.
Since the S-transistor returns from the depletion type to the enhancement type, even if a potential difference may occur between the P-type main base region 22 and the P-type sense base region 24, an unnecessary leak current is generated between them. The current does not flow, and accordingly, the base currents flowing in the P-type main base region 22 and the P-type sense base region 24 are both stabilized, and the current can be detected with high accuracy. Further, in the above, the gate electrode 31 is formed at the same time as the main base electrode 27, the main emitter electrode 28, the sense base electrode 29, and the sense emitter electrode 30, so that the process is not particularly complicated.

FIG. 3 is a vertical cross-sectional view showing the internal structure of an NPN type transistor with a current detecting function adopting a multi-base / multi-emitter structure according to a third embodiment of the present invention. In the respective parts shown in this figure, the same parts as those of the second embodiment shown in FIG. 2 are designated by the same reference numerals to omit redundant description, and the manufacturing process will not be described in detail.

In this embodiment, the second one shown in FIG.
The gate electrode 31 in the above embodiment is short-circuited with the main base electrode. For example, as shown in FIG. 3, the main base electrode 27 ′ has a P type main base region 22.
And the P-type sense base region 24 and the silicon oxide film 26 provided on the N-type silicon substrate 21 located between these regions, and also serves as a gate electrode.

Therefore, as in the second embodiment, the surface level density Q _SS has a negative value, and the vicinity of the surface of the N-type silicon substrate 21 is inverted from N-type to P-type and depletion occurs. Type parasitic P-channel MOS transistor is formed, the gate electrode is formed by extending the main base electrode 27 '.
Type main base region 22 and N ⁺ type main emitter region 2
A positive potential corresponding to the potential difference (about 0.7 V) created by the PN junction with 3 is applied. Therefore, the influence due to the negative surface state density Q _SS is canceled out, and the inverted state near the surface of the N-type silicon substrate 21 is eliminated.

That is, the depletion type parasitic P-channel MOS transistor in which the threshold voltage V _TH of the parasitic P-channel MOS transistor is changed by the negative value of the surface level density Q _SS is changed to a normal enhancement type. After returning, the P-channel MOS transistor remains in the off state.

As described above, according to the third embodiment, due to the action of the gate electrode short-circuited with the main base electrode, the P-type main base region 22 and the P-type sense base region 24 are formed as in the second embodiment. Unnecessary leakage current does not flow between and, and it becomes possible to detect current with high accuracy.
Further, the steps for forming the gate electrode are not particularly complicated.

FIG. 4 is a vertical cross-sectional view showing the internal structure of an NPN type current detecting transistor having a multi-base multi-emitter structure according to the fourth embodiment of the present invention.
In the respective parts shown in this figure, the same parts as those of the second embodiment shown in FIG. 2 are designated by the same reference numerals to omit redundant description, and the manufacturing process will not be described in detail.

In this embodiment, the second shown in FIG.
The gate electrode 31 in this embodiment is shorted to the sense base electrode. For example, as shown in FIG. 4, the sense base electrode 29 ′ is a silicon oxide provided on the P type main base region 22, the P type sense base region 24, and the N type silicon substrate 21 located between these regions. It extends to the upper part of the film 26 and also serves as a gate electrode.

Therefore, similarly to the second embodiment, the surface level density Q _SS has a negative value, and the vicinity of the surface of the N-type silicon substrate 21 is inverted from N-type to P-type and depletion occurs. Type parasitic P-channel MOS transistor is formed, the gate electrode is formed by extending the sense base electrode 29 ', so that the gate electrode is P-type when the transistor with current detection function is conductive. Sense base region 24 and N ⁺ type sense emitter region 25
A positive potential corresponding to the potential difference (about 0.7 V) created by the PN junction with and is applied. Therefore, the surface state density Q
_The influence of the negative value of _SS is canceled, and the inverted state near the surface of the N-type silicon substrate 21 is eliminated.

That is, the threshold voltage V _TH of the parasitic P-channel MOS transistor is changed by the negative value of the surface rank density Q _SS , and the parasitic P-channel MOS transistor, which has been a depletion type, returns to the normal enhancement type. Therefore, the P-channel MOS transistor remains off.

As described above, according to the fourth embodiment, due to the action of the gate electrode short-circuited with the sense base electrode, the P-type main base region 22 and the P-type sense base region 24 are formed as in the second embodiment. Unnecessary leakage current does not flow between and, and it becomes possible to detect current with high accuracy.
Further, the steps for forming the gate electrode are not particularly complicated.

In the above description, the second to fourth embodiments have been described by taking the NPN type transistor as an example. However, the present invention is not limited to this, and the present invention is a PNP type transistor having the opposite conductivity type. Of course, it is applicable. Further, in these cases, the material of each electrode is not limited to aluminum, and other electrode materials may be used.

[0051]

As described in detail above, in any of the first to third inventions, the parasitic M formed in the region between the main base region and the sense base region.
The OS transistor is changed from the depletion type to the enhancement type. As a result, even if a potential difference may occur between the main base region and the sense base region, the parasitic M
Since the OS transistor is kept in the off state, an unnecessary leak current does not flow between these two regions, so that the base current flows stably, which enables highly accurate current detection. In this case, the manufacturing process is not particularly complicated.

[Brief description of drawings]

FIG. 1 is a vertical cross-sectional view showing the internal structure of a PNP-type transistor with a current detection function that adopts a multi-base / multi-emitter structure according to a first embodiment of the present invention.

FIG. 2 is a vertical cross-sectional view showing the internal structure of an NPN-type transistor with a current detection function that adopts a multi-base / multi-emitter structure according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view showing an internal structure of an NPN-type transistor with a current detecting function, which adopts a multi-base / multi-emitter structure according to a third embodiment of the present invention.

FIG. 4 is a vertical cross-sectional view showing an internal structure of an NPN-type transistor with a current detection function, which adopts a multi-base / multi-emitter structure according to a fourth embodiment of the present invention.

FIG. 5 is a vertical cross-sectional view showing the internal structure of a PNP-type transistor with a current detecting function, which adopts a conventional multi-base / multi-emitter structure.

FIG. 6 is a vertical cross-sectional view showing the internal structure of a conventional NPN-type transistor with a current detection function that adopts a multi-base / multi-emitter structure.

[Explanation of symbols]

11 P-type silicon substrate (P-type collector region) 12 Silicon oxide film 13 N-type main base region 14 N-type sense base region 15 P ⁺ type main emitter region 16 P ⁺ type sense emitter region 17 P ⁺ type polysilicon film 21 N Type silicon substrate (N type collector region) 22 P type main base region 23 N ⁺ type main emitter region 24 P type sense base region 25 N ⁺ type sense emitter region 26 Silicon oxide film 27 Main base electrode 28 Main emitter electrode 29 Sense base Electrode 30 Sense emitter electrode 31 Gate electrode V _CC power supply

Claims (3)

[Claims] 1. A main base region and a sense base region containing an N-type impurity are formed in a surface layer portion of a silicon substrate containing a P-type impurity at a predetermined distance and at a predetermined depth. A main emitter region and a sense emitter region are formed in the surface layers of the main base region and the sense base region at a predetermined depth, the main emitter region and the sense emitter region containing P-type impurities at a concentration sufficiently higher than the concentration of P-type impurities in the surface layer of the silicon substrate. In the transistor with a current detection function formed by, the surface of a silicon oxide film obtained by oxidizing the surface of the silicon substrate located between the main base region and the sense base region contains a P-type impurity. To form a polysilicon film and electrically connect the polysilicon film to a predetermined semiconductor region or base region at ground potential. Current detection with transistor characterized by comprising Te. 2. A main base region and a sense base region containing a second conductivity type impurity in a surface layer portion of a silicon substrate containing a first conductivity type impurity with a predetermined depth at a predetermined depth. While being formed, the surface layer portions of the main base region and the sense base region contain a first conductivity type impurity having a concentration sufficiently higher than the concentration of the first conductivity type impurity in the surface layer portion of the silicon substrate. In a transistor with a current detection function formed by forming a main emitter region and a sense emitter region with a predetermined depth, a silicon obtained by oxidizing a surface of the silicon substrate located between the main base region and the sense base region. A transistor with a current detecting function, characterized in that an electrode is formed on the surface of an oxide film and the electrode is electrically connected to a power supply. 3. A main base region and a sense base region containing a second conductivity type impurity in a surface layer portion of a silicon substrate containing a first conductivity type impurity with a predetermined depth at a predetermined depth. While being formed, the surface layer portions of the main base region and the sense base region contain a first conductivity type impurity having a concentration sufficiently higher than the concentration of the first conductivity type impurity in the surface layer portion of the silicon substrate. A transistor with a current detection function, comprising a main emitter region and a sense emitter region formed at a predetermined depth, and a main base electrode, a sense base electrode, a main emitter electrode and a sense emitter electrode formed on the main emitter region and the sense emitter region. On the surface of the silicon oxide film obtained by oxidizing the surface of the silicon substrate located between the sense base region and Forming a pole, the current detection function with transistors, characterized by comprising by shorting the electrode to the main base electrode or the sense base electrode.