JPH05343979A - High speed level shift circuit - Google Patents

Abstract

(57) [Summary] [Objective] In an integrated circuit having insulated gate field effect transistors and having a plurality of power supply systems, a level shift circuit for exchanging signals of different power supply systems has low current consumption and responsiveness. Provide a high level shift circuit. [Structure] A level shift circuit having a characteristic that a falling edge is fast but a rising edge is slow, and a high-speed signal selection circuit internally having a latch circuit and a selection circuit are combined.
With this configuration, both the first output and the second output of the level shift circuit have a slow rising edge but a fast falling edge, and therefore, a falling signal having a high responsiveness is selected and output by the high speed signal selection circuit. [Effect] A high-speed level shift circuit, which has a low current consumption and a quick response at both falling and rising, is realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit having insulated gate field effect transistors (hereinafter abbreviated as MOSFETs) and having a plurality of power supply systems, which has a high-speed level shift circuit for exchanging signals of different power supply systems. It is related to the technology to operate.

[0002]

2. Description of the Related Art In an integrated circuit, for example, when driving a display circuit using liquid crystal, a booster circuit may be used to generate a high voltage, and a low voltage constant voltage circuit for obtaining a circuit with low current consumption. In some cases, the circuits operating at different voltages are mixed in the integrated circuit. In general, signals of these circuits are transmitted to and from each other, but when a high voltage circuit is driven by a low voltage circuit signal, a circuit for connecting them is required. This circuit is called a level shift circuit. Main characteristics of the level shift circuit are current consumption and high-speed response characteristics, and from this viewpoint, the level shift circuit has been gradually improved. 7 to 9 show examples of conventional level shift circuits, which are arranged in the order of oldness. In other words, it is also the history of improvement. FIG. 7 is a circuit of West German Patent Publication 2154877 (DE, A), and FIG. 8 is a circuit of Japanese Patent Publication Sho 57-78227.
FIG. 9 shows a circuit of Japanese Patent Publication No. 57-59690. The problem in the case where the conventional level shift circuit of FIGS. 7 to 9 is not particularly used will be briefly described with reference to FIG.

In FIG. 6, 601 and 603 are P-type MOSs.
FETs 602 and 604 are N-type MOSFETs. The source electrodes of the N-type MOSFETs 602 and 604 are 0
It is connected to the negative electrode, which is the potential. P-type MOSFET 6
The source electrode of 01 is connected to the first positive electrode having the potential E1. The source electrode of the P-type MOSFET 603 is connected to the second positive electrode having the potential E2. Where E1 <E
Set to 2. Input signal 605 is MOSFETs 601, 60
The inverting circuit composed of 2 is driven to become the inverting input signal 606, which is input to the gate of the inverting circuit composed of the MOSFETs 603 and 604. Now, with the above circuit, the output terminal 607 is 0
The potential of the output terminal 607 is 0.
In this case, since the MOSFET 604 is turned on and the MOSFET 603 is turned off, it is better that the potential of the inverting input signal 606 is higher, but the potential of the inverting input signal 606 can be taken only between 0 and E1. Since there is not, even if the potential of the inverted input signal 606 is E1, the MOSFET
If the threshold voltage of 603 is VTH, E2
When the relationship of -E1> VTH is satisfied, the MOSFET 603 is not turned off.
Therefore, the potential of the output terminal 607 does not always become 0 potential, and at the same time, a through current continues to flow from the second positive electrode having the potential E2 to the negative electrode having the potential 0 through the MOSFETs 603 and 604. In other words, normal operation cannot always be guaranteed, and a complementary type M characterized by low current consumption.
The advantages of the OS integrated circuit are greatly impaired.

The level shift circuit is a circuit that has been introduced in order to eliminate the above problems, and the circuit of FIG. 7 is a P-type MOSF.
It is the most basic circuit as a so-called complementary level shift circuit using ET and N-type MOSFETs.

In FIG. 7, 70, 72 and 74 are P type Ms.
OSFETs 71, 73, and 75 are N-type MOSFETs
T. The source electrodes of the N-type MOSFETs 71, 73, and 75 are connected to the negative electrode, which is 0 potential. P-type MOS
The source electrode of the FET 70 is connected to the first positive electrode having the potential E1. The source electrodes of the P-type MOSFETs 72 and 74 are connected to the second positive electrode having the potential E2. A signal is input from the terminal 76, and the signal 77 is a signal obtained by inverting the signal 76. Here, the signal 76 and the signal 77 are 0 to
It operates at a potential between E1. The signal 79 is an output signal of the level shift circuit, and the signal 78 is a signal having an inverted relationship with the signal 79. Here, signal 79 and signal 7
8 operates at a potential between 0 and E2. Now the signal 76 is L
When the potential is 0 (hereinafter abbreviated as negative) signal, signal 7
7 is the E1 potential, signal 79 is the 0 potential, signal 78 is the E2 potential, and MOSFETs 70, 72 and 75 are on,
The MOSFETs 71, 73 and 74 are off. Here, the signal 76 is a high (hereinafter abbreviated as positive) signal E1
When the potential is taken, the MOSFET 73 is turned on and the signal 78 is 0
The signal 77 goes to the potential, and at the same time, the signal 77 causes the MOSFETs 70, 7
Since it goes through the inverting circuit consisting of 1, it becomes 0 potential and MO
The SFET75 is turned off. Since the MOSFET 75 is turned off and the MOSFEET 73 is turned on, the MOSFET 72 is turned off and the MOSFET 74 is turned on, so that the signal 79 goes to the E2 potential and the signal 7 goes.
Since 8 goes to the 0 potential, the MOSFET 72 is further accelerated to the off direction and the MOSFET 74 is accelerated to the on direction. Finally, the signal 76 is the E1 potential, the signal 77 is the 0 potential, and the signal 7 is
9 is E2 potential and signal 78 is 0 potential.
T70, 72, 75 are off, MOSFETs 71, 73,
74 settles on.

Next, when the signal 76 changes to 0 potential again, the MOS
The FET 73 turns off, the signal 77 becomes the E1 potential, and MO
The SFET75 is turned on. Since the MOSFET 75 is turned on, the signal 79 goes to 0 potential. MOSFET 73 is turned off and MOSFET 75 is turned on.
72 goes to the on direction and MOSFET 74 goes to the off direction, whereby the signal 79 goes to the 0 potential and the signal 78 goes to the E2 potential, so that the MOSFET 72 is further turned on and the MOSFET 74 is turned off. After acceleration, the signal 76 is 0 potential, the signal 77 is E1 potential, the signal 79 is 0 potential, and the signal 78 is E2 potential.
ETs 70, 72, 75 are on, MOSFETs 71, 7
3,74 settles off.

The above-described circuit operation is favorably performed when the N-type MOSFETs 71, 73 and 75 having a source potential of 0 are 0.
The gate is controlled by the potential of ~ E1, the source potential of the P-type MOSFET 70 having the E1 potential is controlled by the potential of 0-E1, and the source potential of the P-type MOSFET 7 is the E2 potential.
This is because the gates of 2,74 are controlled by the potential of 0 to E2. The reason why the circuit of FIG. 7 operates normally as compared with the circuit of FIG. 6 is that the gate potentials of the MOSFETs 72 and 74 are 0.
This is because the circuit configuration is controlled by E2. That is, all the MOSFETs are supplied with the gate potential necessary for turning them on and off completely.

The circuit of FIG. 8 is a slight modification of the circuit of FIG. In FIG. 8, MOSFETs 80 to 85 have the same configuration as MOSFETs 70 to 75 in FIG.
The circuit of FIG. 8 differs from the circuit of FIG. 7 in that a resistor 810 is added between the MOSFETs 82 and 83, and a resistor 811 is added between the MOSFETs 84 and 85. The reason why the resistors 810 and 811 are added is that the main purpose is to reduce the shoot-through current that flows when the signal changes and the state transits.

The circuit of FIG. 9 is a further improvement of the circuit of FIG. In FIG. 9, MOSFETs 90 to 95 have the same configurations as the MOSFETs 80 to 85 in FIG. 8 and correspond in order. The circuit of FIG. 9 differs from the circuit of FIG. 8 in that the resistors 810 and 811 in the circuit of FIG.
In the circuit of FIG. 9, P-type MOSFETs 910 and 9
11 has been replaced respectively. In addition, MOSFE
The gate electrode of T910 is connected to the input signal 96, and MO
The gate electrode of the SFET 911 is connected to the inverted input signal 97. Although the resistors 810 and 811 in the circuit of FIG. 8 limit the through current, when the output signal 89 and its inverted output signal 88 are at the E2 potential, they may be delayed rather. In the circuit of FIG. 9, a MOS is used instead of a resistor.
Since it is an FET, it has a high resistance close to OFF when limiting the through current, and it turns on to have a low resistance when the potential E2 is fed to the output signal 99 or the inverted output signal 98. Therefore, the through current is limited and the responsiveness is fast.

The above is an example of the conventional level shift circuit and, in turn, is the history of improvement.

[0011]

The conventional circuit described above has a problem that it is difficult to achieve both higher speed response and suppression of increase in current consumption. For example, in the conventional circuit example shown in FIG. 7,
In FIG. 7, if the conductance constant β of the P-type MOSFETs 72 and 74 is βP, the threshold voltage is VTP, and β of the N-type MOSFETs 73 and 75 is βN, and the threshold voltage is VTN, the input signal 76 becomes positive and E1
In order for the output signal terminal 78 to have a negative 0 potential, the driving capability of the N-type MOSFET 73 needs to exceed the driving capability of the P-type MOSFET 72 during signal switching. Therefore, if both the P-type MOSFET 72 and the N-type MOSFET 73 operate in the saturation region for simplification,

[0012]

[Equation 1]

The relationship of

[0014]

[Equation 2]

The relational expression of is obtained. For example, E1 = 1.5
In the case of V, E2 = 3V, VTP = VTN = 0.5V

[0016]

[Equation 3]

Is obtained. Actually, it requires a margin design, so the value is smaller. Since this relationship is symmetric, the same applies to the relationship between the P-type MOSFET 74 and the N-type MOSFET 75. Since the parasitic electrostatic capacitances have the same value, the responsiveness is determined by the driving ability of the MOSFET, which is seen from the output terminal 79. Regarding the responsiveness, there is a great difference in the responsiveness when the N-type MOSFET 75 is turned on and when the P-type MOSFET 74 is turned on. In other words, the fall is fast and the rise is very slow. At this time, if the capability of the P-type MOSFET is increased in order to increase the rising speed, the capability of the N-type MOSFET must also be increased at the same time, and the short-circuit current at the time of switching of this signal becomes enormous and the current consumption increases. There were challenges. In the case of FIG. 9 which is also a conventional circuit, the condition is slightly relaxed, but since the P-type MOSFET having the source potential of E2 cannot be turned off by the voltage of E1, it essentially has the same problem. is doing.
As described above, the factors that determine the response speed include the above-mentioned parasitic capacitance and the drivability of the MOSFET, but the biggest obstacle in the level shift circuit as a whole is the imbalance between the P-type MOSFET and the N-type MOSFET. is there. Regarding the above-mentioned problems, the submicron era has entered, and the necessity of supporting frequencies of 100 MHz or higher and the number of signals that require level conversion increase with large-scale gates, and heat generation due to power consumption is a major problem. In particular, the circuit of FIG. 9, which is considered to be the best among the conventional circuits, cannot cope with the situation.

Therefore, the present invention solves the above-mentioned problems, and an object of the present invention is to provide a level shift circuit having higher responsiveness without increasing current consumption.

Another object of the present invention is to provide a level shift circuit which requires less current consumption if the response is the same.

[0020]

The high-speed level shift circuit of the present invention comprises: a) a first electric potential E1 having a first polarity, a second electric potential E2 having a first polarity, and a reference electric potential 0 having a second polarity. In a semiconductor integrated circuit having and as power sources, b) Reference potential 0
And an electric potential E1, an input signal terminal operating between the reference electric potential 0 and the electric potential E1, and an inverting circuit for generating an inversion signal of the input signal terminal, and a source electrode connected to a power supply terminal E2. A first conductivity type first insulated gate field effect transistor (hereinafter abbreviated as MOSFET), a first conductivity type second MOSFET, and a second source electrode whose source electrode is connected to a power supply terminal of reference potential 0. Conductive third MOSFE
T and at least a fourth MOSFET of the second conductivity type, the drain electrodes of the first MOSFET and the third MOSFET are connected to each other, and the second MO
It is connected to the gate electrode of the SFET and the connection point is the second
Of the second MOSFET and the fourth MOSFET are connected to each other and to the gate electrode of the first MOSFET, and the connection point is the first output signal. It is a terminal,
The input signal terminal operating between 0 and E1 is the third M
The output terminal of the inverting circuit which is connected to the gate electrode of the OSFET and operates between the 0 and E1 is the fourth MOSFET.
A level shift circuit connected to the gate electrode of c), c) a first output signal terminal and a second output signal terminal of the level shift circuit are input, and a latch circuit and a signal storing the immediately previous state are stored. It has a selection circuit to select,
It is characterized by comprising a high-speed signal selection circuit for selectively outputting a high-speed signal.

[0021]

According to the above configuration of the present invention, both the first output signal terminal and the second output signal terminal of the level shift circuit have a fast fall and a slow rise of the output signal, but they are in an inverse relationship to each other. Since it is a signal, the high-speed signal selection circuit selects and outputs a falling signal having a high responsiveness at the first and second output signal terminals based on the memory of the previous state to output a rising or falling signal. In either case, a high-speed level shift circuit having high-speed response is realized.

[0022]

1 is a circuit diagram showing a first embodiment of the present invention. In FIG. 1, a circuit surrounded by a broken line 101 is a level shift circuit, and a circuit surrounded by a broken line 102 is a high speed signal selection circuit. The left side of the alternate long and short dash line 103 is an E1 system circuit using the positive power source potential E1 as a power source, and the right side is an E2 system circuit using the positive power source potential E2 as a power source. However, there is a relationship of E1 <E2. In the broken line 101, 105 and 106 are P-type MOSFETs and 10
Reference numerals 7 and 108 are N-type MOSFETs. P-type MOSFE
The source electrodes of T105 and 106 are connected to the power supply terminal of the positive potential E2, and the source electrodes of the N-type MOSFETs 107 and 108 are connected to the power supply terminal of the negative potential 0.
The drain electrodes of the P-type MOSFET 105 and the N-type MOSFET 107 are connected to each other and serve as the second output signal terminal 111 as the level shift circuit 101. P-type MOSFET 106 and N-type MOSFET
The drain electrodes of 108 are connected to each other and serve as the first output signal terminal 110 as the level shift circuit 101. The gate electrode of the P-type MOSFET 105 is connected to the first output signal terminal 110, and the P-type MO
The gate electrode of the SFET 106 is the second output signal terminal 11
It is connected to 1. The gate electrode of the N-type MOSFET 107 is the input signal terminal 1 as the level shift circuit 101.
09, and the gate electrode of the N-type MOSFET 108 is connected to the output of an inverting circuit (hereinafter referred to as an inverter circuit) 104 that produces an inverted signal of the input signal terminal 109. The configuration of the level shift circuit 101 described above is exactly the same as the circuit of FIG. 7 described in the conventional circuit, and therefore the operation is also the same. The operation for the clock waveform input to the input signal terminal 109 is shown in (109), (110), (11) of FIG.
It is shown in 1). In the timing chart of FIG. 3, (110) and (111) are the first output signal terminal 1 respectively.
10 and the operation waveforms of the second output signal terminal 111, the falling response is fast, the rising waveform is dull, and the response is slow. This is P as compared with the N-type MOSFETs 107 and 108 as described in the problem of the conventional circuit.
This is because it is necessary to design the driving capability of the type MOSFETs 105 and 106 to be weak.

In broken line 102, 112 is an AND-NOR circuit (AND / AND-NOR circuit), 113, 114, 116 and 117 are inverter circuits, and 115 is a NOR circuit (NOR circuit). 11
Reference numeral 8 is a latch circuit (LATCH circuit). The first output signal terminal 110 of the level shift circuit 101 is AND / AN
The second output signal terminal 111 is connected to the first gate of the first AND of the D / NOR circuit 112, and the second output signal terminal 111 is connected to the inverter circuit 114.
The second AND of the AND-AND-NOR circuit 112
Connected to the first gate of the. AND / AND / NO
The output of the R circuit 112 is connected to the gate of the inverter circuit 113, the output of the inverter circuit 113 serves as the output terminal 119 as the high-speed signal selection circuit 102, and is also connected to the data input (D) of the latch circuit 118. ..
The master (M) output of the latch circuit 118 is AND / AN
It is connected to the second gate of the first AND of the D / NOR circuit 112, and is also connected to the AND / AND via the inverter circuit 117.
It is connected to the second gate of the second AND of the NOR circuit 112. The first output signal terminal 110 and the second output signal terminal 111 are respectively connected to the first gate and the second gate of the NOR circuit 115, and the output of the NOR circuit 115 passes through the inverter circuit 116 and the clocked gate of the latch circuit 118 ( CL). The latch circuit 118
FIG. 2 shows a specific circuit configuration example of the above. 20 in FIG.
1, 203 are clocked gate inverters,
1 transmits a signal when the clock signal (CL) is positive, 20
3 carries a signal when the clock signal is negative. 202 is an inverter circuit. The data (D) signal is input to the gate 204 of the clocked gate inverter circuit 201, and the output 205 is connected to the gate of the inverter circuit 202,
The output 206 of the inverter circuit 202 is connected to the gate of the clocked gate inverter circuit 203, and the output of the clocked gate inverter circuit 203 is connected to the output 205 of the clocked gate inverter circuit 201.
At this time, the output 206 of the inverter circuit 202 serves as a master (M) output signal as a latch circuit. At this time, when the clock (CL) signal is positive, the data (D) signal is input, and when the clock signal is negative, the previous state data is held between the inverter circuit 202 and the clocked gate inverter circuit 203.

The operation of the high speed signal selection circuit 102 at this time will be described below. As described above, the level shift circuit 1
As for the waveforms of the first output signal 110 and the second output signal 111 of 01, the falling response is fast and the rising is slow as shown in (110) and (111) of FIG. To quickly respond to the clock input signal waveform (109) (11
If the signals of 0) and (111) that have a fast response are used, the E2 clock signal is
This means that the output signal of the system was converted with good response. It can be seen from the timing chart of FIG. 3 that the signal of (111) responds quickly when the previous state of the clock change is negative, and the signal of (110) responds quickly when the state is positive. Therefore, the previous state is memorized and accordingly (110),
It is sufficient to distribute the signal of (111). The latch circuit 118 stores the previous state, and the latch circuit 118 distributes the M signal of the latch circuit 118 and the inverter circuit 1.
AND AND AN is 17 and is selectively combined
The D / NOR circuit 112. The NOR circuit 115 and the inverter circuit 116 adjust the timing of fetching data from the latch circuit 118. This is because if the signal of M of the latch circuit 118 and the selection distribution signal of the inverter circuit 117 are changed to the surplus of the change of the signal of the output terminal 119, a malfunction occurs.

As described above, the signals at the first output terminal 110 and the second output terminal 111 of the level shift circuit 101 both have a fast falling edge and a slow rising edge. A signal that responds at high speed to both the falling edge and the rising edge is obtained from the output terminal 119. The above situation is shown in the timing chart of FIG. From the above, it is understood that the high-speed level shift circuit of the present invention in which the level shift circuit 101 and the high-speed signal selection circuit 102 are combined can convert the level of the E1 system signal to the E2 system signal at high speed. Although the embodiment of the present invention has been described with reference to the circuit of FIG. 1, the present invention is not limited to the circuit of FIG. For example, the circuit shown in FIG. 4 shows another example of the level shift circuit 101 shown in FIG. 1, and the inverter circuit 404 and the MOSFET 40 shown in FIG.
5, 406, 407, and 408 are the inverter circuit 104 and MOSFETs 105, 106, and 1 in FIG. 1, respectively.
07 and 108 in order, and the P-type MOSF of FIG.
ETs 413 and 414 are newly added. In FIG. 4, P-type MOSFETs 413 and 414 are respectively inserted between the power source E2 and P-type MOSFETs 405 and 406, the gate electrode of the MOSFET 413 is connected to the input signal terminal 409, and the MOSFET 414 gate electrode inverts the signal of the input signal terminal 409. It is connected to the output of the inverter circuit 404. The above-described circuit of FIG. 4 operates essentially the same as the circuit of FIG. 9 shown in the conventional circuit example except that the order of MOSFETs is changed.

As the level shift circuit section, not only the circuit shown in FIG. 4 but also the circuits shown in FIG. 8 and FIG. Further, in FIG. 1, the high-speed signal selection circuit 102 is also a simple selection circuit in essence, so that not only this circuit but also many equivalent circuits exist. For example, a circuit as shown in FIG. 5 may be used.

In the above level conversion, the negative electrode is 0.
With respect to the electric potential, the case where the E1 and E2 are the two positive power sources has been described. A similar circuit can be made.

[0028]

As described above, according to the present invention, two signals of the level shift circuit having an output signal with a fast fall and a slow rise are selected by the high speed signal selection circuit and the faster one is output. Therefore, there is an effect that it is possible to provide a high-speed level shift circuit having a high-speed response at both the falling edge and the rising edge.

Further, at this time, since the conventional level shift circuit is used, there is an effect that the response can be improved while keeping the low current consumption.

Further, if the responsiveness is made constant, there is an effect that a level shift circuit with lower current consumption can be provided.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific configuration example of a latch circuit used in the circuit diagram of FIG. 1 of the present invention.

FIG. 3 is a timing chart showing the operation of the circuit of FIG. 1 of the present invention.

FIG. 4 is a circuit diagram showing another configuration example of the level shift circuit used in the circuit of the present invention.

FIG. 5 is a circuit diagram showing another configuration example of a high-speed signal selection circuit used in the circuit of the present invention.

FIG. 6 is a circuit diagram showing a case where signals of different power supply systems are transmitted without using a level shift circuit.

FIG. 7 is a circuit diagram showing a first example of a conventional level shift circuit.

FIG. 8 is a circuit diagram showing a second example of a conventional level shift circuit.

FIG. 9 is a circuit diagram showing a third example of a conventional level shift circuit.

[Explanation of symbols]

70, 72, 74, 80, 82, 84, 90, 92, 9
4, 105, 106, 405, 406, 413, 41
4, 601, 603, 910, 911 ... P-type MOS
FETs 71, 73, 75, 81, 83, 85, 91, 93, 9
5, 107, 108, 407, 408, 602, 604
... N-type MOSFETs 76, 78, 79, 86, 88, 89, 96, 98, 9
9, 109, 110, 111, 119, 409, 41
0, 411, 510, 511, 519, 605, 607
・ ・ ・ Terminal 101 ・ ・ ・ Level shift circuit 102 ・ ・ ・ High-speed signal selection circuit 103 ・ ・ ・ Boundary line between E1 and E2 power supplies 104, 113, 114, 116, 117, 202, 4
04, 514, 517, 520 ... Inverter circuit 112, 512 ... And and NOR circuit 115 ... NOR circuit 118, 518 ... Latch circuit 201, 203 ... Clocked gate inverter circuit 204・ ・ ・ D signal of the latch circuit 205 ・ ・ ・ M inverted signal of the latch circuit 206 ・ ・ ・ M signal of the latch circuit 515 ・ ・ ・ Nand circuit 810, 811 ・ ・ ・ Resistance

Claims (1)

[Claims] 1. A) a first electric potential E1 of a first polarity and a first electric potential
A semiconductor integrated circuit having as a power source a second potential E2 of the second polarity and a reference potential 0 of the second polarity, b) an input signal terminal operating between the reference potential 0 and the potential E1, and a reference potential 0 And an inverting circuit for generating an inverting signal of the input signal terminal which operates between the voltage E1 and the potential E1, and a source electrode E
A first conductivity type first insulated gate field effect transistor (hereinafter abbreviated as MOSFET) connected to the second power supply terminal, a first conductivity type second MOSFET, and a power supply whose source electrode is a reference potential 0. A third MOSFET of a second conductivity type and a fourth MOSFET of a second conductivity type connected to the terminals
T and at least a first MOSFET and a third M
The drain electrodes of the OSFETs are connected to each other and to the gate electrode of the second MOSFET,
And the connection point is the second output signal terminal,
Drain electrodes of the second MOSFET and the fourth MOSFET are connected to each other and to the gate electrode of the first MOSFET, and the connection point serves as the first output signal terminal. Between the input signal terminal operating between the third MOSFET and the gate electrode of the third MOSFET, and the output terminal of the inverting circuit operating between the 0 and E1 is connected to the gate electrode of the fourth MOSFET. A level shift circuit, and c) a first output signal terminal of the level shift circuit and a second
Of the high-speed signal selecting circuit for selecting and outputting a high-speed signal. High-speed level shift circuit.