JPH0537891A - Electronic still camera multi-screen control circuit and method thereof - Google Patents

Abstract

PURPOSE: To display plural screens on a screen display part and to save the retrieval time of plural picture data recorded in the main memory of an electronic still camera. CONSTITUTION: The electronic still camera contatins a multiplex screen control circuit 10 which is controlled by a micro computer 9 corresponding to a screen generation request inputted from a screen selection part 8 and which shows respective screen states. When a retrieval mode is not designated, the camera operates at the operation mode of a general system. When the retrieval mode is designated, output from a reproduction buffer memory 5 to a video display part 7 is inhibited and the micro computer 9 controls the multiplex screen control part 10 by an instruction from the screen selection part 8, picture data of a main memory 4 is read and it is recorded in the reproduction buffer memory 5. Then, it is outputted from the reproduction buffer memory 5 to the video display part 7 after recording terminates. The instruction of the screen selection part 8 is waited for after output. When a termination signal is received during waiting, the multiplex screen in the middle of display is erased, the screen during display is reproduced before a retrieval process is executed and a system restores to the normal mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit and method for reading out image data recorded in a main memory and displaying it on an image display unit in an electronic still camera.
In particular, the present invention relates to a multi-screen control circuit and method for displaying a plurality of images recorded in a main memory one by one through an image display unit or displaying and retrieving a plurality of images at the same time.

[0002]

2. Description of the Related Art Generally, C is used in electronic still cameras.
An image signal photoelectrically converted by a photoelectric conversion element such as a CD is converted into digital image data by an analog / digital converter and recorded on a recording medium in frame units. The image data recorded on the recording medium may be erased for later recording or may be recorded and stored on another recording medium. At this time, the former is the buffer memory and the latter is the main memory. Usually, the storage capacity of the main memory is set larger than that of the buffer memory so that a large number of image data can be recorded / stored. The plurality of image data recorded in the main memory are processed by a data processing means such as a microcomputer and can be provided for other purposes of the user, such as copying, transmission and reproduction. When trying to confirm the contents of the image data recorded in the main memory, the image data recorded in the main memory is copied to another buffer memory (playback is used as the buffer memory), and the data in the playback buffer memory is ordered. After reading the data, it is converted into an analog signal through a digital / analog converter, and then displayed as a composite resolution signal on a display device such as a monitor attached to the electronic still camera.

FIG. 1 shows a recording screen display circuit of a conventional electronic camera. The image signal generated by the video input unit 1 having a photoelectric conversion element such as CCD is converted into digital image data by the analog / digital converter 2 and recorded in the buffer memory 3 in frame units. Buffer memory 3
The image data recorded in (1) can be erased for later recording or can be recorded and stored in the main memory 4. The main memory 4 can record a plurality of image data, and in order to efficiently manage the recorded image data, one image data is limited and recorded in an area called a page. The recording area of one page is the same as or larger than the recording area required for recording one image data, and different pages mean that different image data are recorded. That is, it is possible to manage by dividing each page regardless of the contents of the image data recorded by the microcomputer. FIG. 2 shows the addressing relationship with the image data in the main memory 4 of FIG. Here, it is assumed that the size of one frame is 256 bytes × 256 bytes and the number of pages is 16. The image data in a given page is specified by dividing it into horizontal and vertical components, so the horizontal component corresponds to the horizontal address of the image data and the vertical component corresponds to the vertical address of the image data. It will be equivalent. 512 when increasing the resolution of the display screen or using the capacity of one field in the non-sequential scanning method
Byte × 512 bytes can also be used. In this case, if the main memory having the same storage capacity is used, the number of pages used is four. The image data recorded in each area of the main memory 4 can be read out and confirmed through the image display unit 7, and can be erased or moved to another area in the main memory 4 to record another image. Is. The control of the main memory 4 is performed by the microcomputer 9. In order to confirm the recorded image data through the image display unit 7, one of various pages in the main memory 4 is selected, and the image data in the page is read and recorded in the reproduction buffer memory 5.
The image data recorded in the reproduction buffer memory 5 is read according to the horizontal and vertical periods suitable for displaying on the image display unit 7, and converted into analog data by the digital / analog converter 6. The video signal converted into analog data is displayed on the image display unit 7. In this case, since the image data recorded in the main memory 4 is read in page units and recorded in the reproduction memory 5, the user must repeat the above operation as many times as necessary to confirm a large number of images. There was the inconvenience of having to specify the area.

[0004]

SUMMARY OF THE INVENTION An object of the present invention is to provide an apparatus capable of designating one or a plurality of image data recorded in a main memory and simultaneously displaying the designated image data on an image display section. is there.

Another object of the present invention is to provide a method of designating one or a plurality of image data recorded in the main memory and simultaneously displaying the designated image data on the screen display unit.

[0006]

In order to achieve the above-mentioned object, the apparatus of the present invention interprets the screen selection input by the screen selection means capable of receiving the selection request of the user and the image display. A microcomputer for performing a control operation for displaying one or a plurality of frames of image data through the unit, and a multiple screen control means for realizing each screen state under the control of the microcomputer. To do.

In the control of such a multi-screen reproducing circuit, if the search mode is not designated, the operation is performed in a general operation mode, and if the search mode is designated, the output from the reproduction buffer memory to the image display section is prohibited. Process, a reproducing process in which the microcomputer controls the multiple screen control unit in response to a command from the screen selecting unit to read the image data of the main memory and records it in the reproducing buffer memory, and a reproducing buffer after the recording process is completed. The output process for restarting the output from the memory to the image display unit, the standby process for performing the output process and waiting for the command of the screen selection unit, and the screen currently displayed when the end signal is received in the standby process. And a return process of returning the screen displayed before performing the search process and returning to the normal mode.

[0008]

Therefore, according to the present invention, it is possible to display a plurality of screens on the screen display portion, and it is possible to save time for searching a plurality of image data recorded in the main memory of the electronic still camera.

[0009]

The present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 3, the multi-screen display circuit according to the present invention includes a video input unit 1 for generating an analog video signal from an object to be imaged and an A / D conversion for converting the analog video signal into digital video data. Device 2, a buffer memory 3 for recording the digital video data on a frame-by-frame basis, a main memory 4 for recording / storing the image data of the buffer memory 3, and an image read from the main memory 4. A reproduction buffer memory 5 capable of storing data in frame units, a D / A converter 6 for converting digital video data read from the reproduction buffer memory 5 into an analog video signal, and the analog video signal as a screen A screen selection for selecting the image display unit 7 to be displayed on the screen and a screen to be displayed by the user on the image display unit 7. 8, a microcomputer 9 for interpreting a screen selection request input through the screen selection unit 8 and performing a predetermined control operation, and a read address for controlling the microcomputer 9 to generate respective screen states. The multi-screen controller 10 for generating The screen selection unit 8 is for inputting a user's command regarding the search mode operation, and includes a unit for designating the search mode and a unit for designating a page of the screen to be reproduced. Microcomputer 9
Designates the page address of the image data recorded in the main memory 4 for performing the control operation for receiving the command from the screen selection unit 8 and providing the reproduction buffer memory 5 with the reproduction screen. 10 operations are controlled. The multi-screen controller 10 includes a multiplexer, a plurality of address generators, horizontal and vertical counters, and flip-flops for generating a read address within a page designated by the microcomputer 9 under the control of the microcomputer 9.

FIG. 4 is a block diagram of the multiple image control unit 10 according to the present invention, wherein a plurality of N screen address generating units 141, 142, 143, 14 for generating multiple screen display addresses are provided.
, ..., 14N and the multiplexer 1 for selectively outputting the output of the N screen address generator and applying it to the main memory 4.
3, a horizontal / vertical counter 12 for generating horizontal / vertical addresses of the reproduction buffer memory 5, a horizontal / vertical overflow detector 15 for detecting overflow of the horizontal / vertical counter 12, and a flip-flop 11 for controlling a clock input to the horizontal / vertical counter. It is configured to include.
Here, the horizontal / vertical counter 12 is the reproduction buffer memory 5
The addressing operation of the reproduction buffer memory 5 is controlled at the same time as the addressing operation of the image data of the main memory 4 is controlled.

FIG. 5 shows an example of the N screen address generator. Each of the N screen address generators 141, 142,
, 14N are arranged so that the horizontal address generator 14N can count in the horizontal and vertical directions by a predetermined interval.
H, vertical address generator 14NV, and OR gate 14N
It is composed of O. The horizontal address generator 14NH is connected to the first counter 14NH-2 that provides an even multiple of the input clock signal, the second counter 14NH-3 that provides an integer multiple of the same, and the first counter connected to the first counter. The output values of the first adder 14NH-1 and the first adder 14NH-4, which add the output values of the first counter 14NH-2 and the second counter 14NH-3, A horizontal overflow detector 14NH-5 is provided to monitor and detect whether or not an overflow has occurred.

The vertical address generator 14NV has a third counter 14NV-2 which provides an even multiple of the input clock signal and a fourth counter 1 which provides an integer multiple of the same.
4NV-3 and the second multiplier 14 connected to the third counter
The output values of the second adder 14NV-4 and the second adder 14NV-4, which add the output values of the NV-1 and the third counter 14NV-2 and the output value of the fourth counter 14NV-3, are monitored. A vertical overflow detector 14NV-5 for detecting whether or not an overflow has occurred is provided.

This is because the OR gate 14NO logically operates the output of the horizontal overflow detector 14NH-5 and the output of the vertical overflow detector 14NV-5.

On the other hand, in displaying a plurality of images on the image display section 7, it is necessary to compress and represent the image data in the main memory 4. In the present invention, a method of skipping and reading the image data recorded in the main memory 4 in the horizontal or vertical direction by a predetermined interval determined by the number of screens is used as the image data compression method. It should have a generator. Further, in order to provide a plurality of divided screens in the horizontal or vertical direction, each of the horizontal and vertical address generators performs counting by an integral multiple (1, 2, 3, ..., N) with respect to the input clock. Should. The present invention is provided with a counter that counts an even multiple and a counter that counts an integral multiple of the input clock. By adding the output values of the counter that counts to an even multiple and the counter that counts to an integral multiple, it is possible to receive a count value of a certain multiple. The method of counting the value of even multiples is achieved by multiplying the clock input using an even multiplier and supplying it to the counter.

The reading operation from the main memory 4 when searching the four image data shown in FIG. 12D will be described. First, the first horizontal line of the first image data is skipped every other pixel by the image data compression method and is read in the horizontal direction. After the reading of the first horizontal line of the first image data is completed, the second horizontal line is read. The reading of the first horizontal line of image data is performed in the same way. The read image data of the horizontal line is recorded in the horizontal line of the first frame of the reproduction buffer memory. When recording on the first horizontal line of the reproduction buffer memory 5 is completed, the vertical address of the reproduction buffer memory 5 is increased by one. The horizontal lines of the first and second image data on the main memory 4 are skipped by one line in the vertical direction, and the read operation for the third horizontal line of the first and second image data is performed in the same manner as described above. . Each time the image data to be read from the main memory 4 changes, the microcomputer 9 specifies each page address, so it is necessary to detect that the horizontal and vertical reading of each image data has been completed. Whether or not the reading of the horizontal or vertical direction component of the image data is completed is monitored by monitoring the respective address values applied from the horizontal address generating section 144H or the vertical address generating section 144V of the 4-screen address generating section 144 to the address bus of the main memory 4. The most significant bit (M
If the falling edge of SB) is detected, it is possible to determine whether or not the reading of the horizontal or vertical line is completed. The overflow detection operation is performed by the horizontal overflow detection unit 144.
H-5 or vertical overflow detector 144V-5. The detected overflow signal is detected by the microcomputer 9, and the microcomputer 9 detects the overflow signal and then applies the page address of the image data to be read next to the address bus of the main memory 4. On the other hand, the D flip-flop 11 connected to the input portion of the horizontal / vertical counter through the OR gate 144O so that the horizontal / vertical counter 12 of the reproduction buffer memory 5 is stopped while the microcomputer 9 applies the page address.
Input with the disable signal of. The microcomputer 9 applies the page address of the second screen to the address bus of the main memory 4 and then outputs a start signal to clear the D flip-flops of the overflow detectors 144H-5 and 144V-5. On the other hand, the start signal from the microcomputer 9 is D
Flip-flop 11 is also cleared and horizontal and vertical counter 1
The D flip-flop 1 for which the clock input to 2 is prohibited is enabled, the clock is supplied again, and the operation of the horizontal / vertical counter 12 is restarted. At the same time, the horizontal and vertical address generators 144H, 144H of the screen 4 address generator 144,
The operation of 144V is restarted. On the other hand, if the vertical overflow signal is generated, it means that the reading of the image data in the designated page area has been completed. Therefore, the microcomputer 9 applies the page address of the next image data, and the subsequent operation is as described above. Is the same as. Horizontal and vertical counter 1
The overflow signal generated by the overflow detection unit 15 connected to the most significant bit (MSB) of the address signal output by 2 is used as an end signal, and the operation of the 4-screen address generation unit ends and the recording in the reproduction buffer memory 5 ends. It is supplied to the microcomputer 9 as a signal indicating that it has been done.

FIG. 6 shows an example of the flowchart of the present invention. If the search mode is designated by the screen selection unit 8 while operating in the normal mode, the search mode will be executed. First, it is checked whether the instruction of the screen selection unit 8 is an instruction to specify the end of search (step 600). If it is not a command for designating the end of search, it is checked whether the screen creating operation was performed in the previous search mode (step 610). If the image data designated by the previous search command is being recorded in the buffer memory for reproduction by the multiple screen control routine, it is necessary to stop this and record a newly designated multiple screen (step 620). The signal applied from the screen selection unit 8 to the microcomputer 9 in the search mode is a signal indicating the page number to be displayed or the end of the search mode. The page number that must be displayed on the microcomputer 9 is changed to a page address that can be supported and stored (6
30 steps). When the page address of the image data to be displayed is prepared, the output to the image display unit 7 is stopped (step 670). Carry out a multi-screen control routine. The multi-screen controller 10 is controlled to record the display screen in the reproduction buffer memory (step 680). Image display section 7
Then, the image recorded in the reproduction buffer memory is displayed on the image display unit 7 (step 690). On the other hand, if it is a command to specify the end of search, it is checked whether or not the multiple screen control unit 10 has performed recording in the reproduction buffer memory (step 640). If the multi-screen control unit 10 has performed the recording in the buffer memory for reproduction at step 640, this is stopped (step 650) to display the screen that was displayed before the reproduction screen. A page address is provided (step 660), and a reproducing operation is performed as described above (steps 670-690).

FIG. 7 shows an example of the search screen display routine in FIG. The number of images to be displayed is determined, and the process is branched to the N screen control routine corresponding to each image (steps 700-790).

FIG. 8 shows an example of the one-screen display routine shown in FIG. First, the multi-screen controller sets an operation display flag for displaying that the reproduction buffer memory is recording (step 800). This operation display flag is used when the microcomputer 9 checks whether or not the multi-screen control unit 10 is operating. The page address of the designated image data is applied to the address bus of the main memory 4 (step 810). In order to initialize the operation of the horizontal / vertical counter 12, the horizontal / vertical counter 12 is reset (step 820). The horizontal / vertical counter 12 is operated to start reading from the main memory 4 and recording operation to the reproduction buffer memory 5 (step 830).
The end signal from the horizontal stage counter 12 is inspected and waits until the recording is completed (step 840). When the recording operation is completed, the operation display flag is reset and the one-screen control routine is finished (steps 850-860).

FIG. 9 shows an example of the two-screen control routine shown in FIG. In the case of a two-screen display, the image data in the vertical direction must be compressed by recording the reproduction buffer memory area in upper and lower parts.
The 1/2 compression of the image data in the vertical direction is performed by a method of skipping every other horizontal line in the vertical direction from the main memory 4 and reading it. At this time, in the vertical address generation approval / disapproval 142 NV of the two-screen address generation unit, a value twice as large as the vertical address value specified from the horizontal / vertical counter 12 to the reproduction buffer memory 5 is used as the vertical address of the image data in the main memory 4. Will be applied. Whether or not recording is completed on the upper one screen can be known by detecting the falling edge of the most significant bit from the vertical address generator 142V of the two-screen address generator. Vertical address generator 1
When an overflow occurs from 42V, the microcomputer 9 applies the page address of the second image data to the address of the main memory 4 to perform the reading and recording operation for the second image data.

First, the multiple screen control unit sets a flag indicating that recording is being performed in the reproduction buffer memory 5 (step 900). This operation display flag is used when the microcomputer 9 checks whether or not the multi-screen control unit 10 is operating. The page address of the designated image data is applied to the address bus of the main memory 4 (step 910). In order to initialize the operation of the horizontal / vertical counter 12, the horizontal / vertical counter 12 is cleared (step 920). The horizontal / vertical counter 12 is operated to start the reading operation from the main memory 4 and the recording operation to the reproduction buffer memory 5 (step 930). The vertical overflow signal is inspected and waits until the recording of the first image data is completed (step 940). When the recording operation of the first image data is completed, the page address of the second screen is applied to the main memory 4 address bus (step 950). The operation of the horizontal / vertical counter 12 is restarted, and the reading operation from the main memory 4 and the recording operation in the reproduction buffer memory 5 are restarted (step 960). The end signal from the horizontal / vertical counter 12 is inspected and the completion of recording in the reproduction buffer memory 5 is waited (step 970). When the recording operation is completed, the operation display flag is reset and the two-screen display routine is ended (steps 980-990).

10 and 11 show an example of the 4-screen control routine of FIG. In the case of a four-screen display, since the area of the reproduction buffer memory is divided into two parts, that is, vertically and horizontally, the data is compressed in the horizontal and vertical directions. Compressing the image data in the vertical direction is performed by a method of skipping every other pixel on a horizontal line on the main memory 4 and reading it. At this time, the address values generated by the horizontal and vertical address generators of the 4-screen address generator are applied as the read address of the main memory 4. Whether or not recording is completed on the first horizontal line of the first screen can be known by detecting the falling edge of the most significant bit from the horizontal address generation / non-permission 144H of the 4-screen address generation unit 144. 4 screen address generator 14
When an overflow signal is generated from the horizontal address generator 144H of No. 4, the microcomputer 9 applies the page address of the second image data to the address bus of the main memory 4 to read and read the first horizontal line of the second image data. The recording operation will be performed. In the reading of the second image, if an overflow occurs from the horizontal address generator 144H of the 4-screen address generator 144, the microcomputer 9 applies the page address of the first image to the address bus of the main memory 4 and then the first image. Read and write operations for the next horizontal line of data will be performed. The image data is compressed in the vertical direction by reading every other horizontal line from the main memory 4 in the vertical direction. At this time, the vertical address value generated from the vertical address generator 144V of the 4-screen address generator is applied as the read address of the first and second image data of the main memory 4. When the reading and recording operations for the final horizontal lines of the first and second images are completed by the same method as described above, the microcomputer 9 applies the page address of the third image data to the address bus of the main memory 4 and the third address. The reading and recording operations for the fourth image data are performed. Whether or not the recording of the first and second image data has been completed can be known by detecting the falling edge of the most significant bit (MSB) from the vertical address generator 144V of the 4-screen address generation / denial 144. When an overflow signal is generated from the vertical address generating unit 144V of the unit 144, the microcomputer 9 applies the page address of the third image to the address bus of the main memory 4 to perform the reading and recording operation for the third image.

First, the multiple screen controller sets a flag indicating that recording in the reproduction buffer memory is in progress (step 1000). This operation display flag is used when the microcomputer 9 checks whether or not the multi-screen control unit 10 is operating.
The page address of the first image data is applied to the address bus of the main memory 4 (step 1010). In order to initialize the operation of the horizontal / vertical counter 12, the horizontal / vertical counter 1
2 is reset (step 1020). The horizontal / vertical counter 12 is operated to start the reading operation from the main memory 4 and the recording operation in the reproduction buffer memory 5 (step 1030). Four
The screen address generator 144 is monitored for horizontal overflow and waits until the reading and recording of the first horizontal line of the first image data is completed (step 1040). When the recording on the horizontal line of the first image data is completed, the page address of the second screen is applied to the address bus (step 1050) and the horizontal / vertical counter 12 is operated to operate the first horizontal line of the second image data. The line is read and recorded (step 1060). The horizontal overflow is monitored and the completion of recording for the first horizontal line of the second image is waited (step 1070). When the recording of the first horizontal line of the second image data is completed, it is checked whether vertical overflow has occurred (step 1080). If no vertical overflow occurs, the page address of the first image data is applied to the address bus of the main memory 4 (step 1090). The operation of the horizontal / vertical counter 12 is restarted (step 1100), and the operation returns to step 1040 for monitoring the horizontal overflow. The reading and recording operations up to the final horizontal line of the first image data and the second image data are performed by repeating the above steps (1040-1100). If the vertical overflow is detected from step 1080, the page address of the third image data is applied to the address bus (step 1110). The process of reading and recording the third and fourth images is exactly the same as the process of reading and recording the first and second images (1120-11).
90 steps). However, if a vertical overflow occurs after recording the final horizontal line of the fourth image at step 1170, the horizontal / vertical counter is cleared, the operation display flag is reset, and the four-screen control routine ends (1200-1).
Step 210).

FIG. 12 illustrates a screen state displayed on the image display unit according to the present invention.

[0025]

According to the present invention, a plurality of screens can be displayed on the screen display unit, and it is possible to save time for searching a plurality of image data recorded in the main memory of the electronic still camera.

It should also be appreciated that the present invention can be used in devices that store image data in main memory, such as color video printers, as made clear by the description of the invention.

[Brief description of drawings]

FIG. 1 is a recording screen display circuit diagram of a conventional electronic still camera.

FIG. 2 is a diagram showing a screen area division state of the main memory shown in FIG.

FIG. 3 is a block diagram of a multiple screen display circuit according to the present invention.

FIG. 4 is a block diagram of a multi-screen control unit including a main memory, a reproduction buffer memory, and a microcomputer shown in FIG.

FIG. 5 is an example of a multiple screen display address generation unit shown in FIG.

FIG. 6 is an example of a flowchart of a multiple screen control method according to the present invention.

FIG. 7 is an example of a search display routine shown in FIG.

8 is an example of a one-screen display routine shown in FIG.

9 is an example of a two-screen display routine shown in FIG.

10 is a flowchart of an example of the 4-screen display routine shown in FIG.

11 is a flowchart following FIG.

FIG. 12 is a screen state displayed on the screen display unit according to the present invention.

[Explanation of symbols]

1 Video Input Section 2 A / D Converter 3 Buffer Memory 4 Main Memory 5 Playback Buffer Memory 6 D / A Converter 7 Image Display Section 8 Screen Selection Section 9 Microcomputer 10 Multiple Screen Control Section 11 Flip-Flop 12 Horizontal / Vertical Counter 13 Multiplexer 15 Horizontal / vertical overflow detector 14N, 141, 142, 143, 144 Screen address generator

Claims (12)

[Claims] 1. An electronic still camera in which a video signal is digitized and stored in a main memory and an image is displayed by a reproducing means for receiving an image displayed in a search mode or a search end command. A screen selection unit, a microcomputer that receives a command from the screen selection unit and performs a predetermined control, and a read address for one screen or a plurality of image data recorded in the main memory in the search mode under the control of the microcomputer. A multi-screen control circuit for an electronic still camera, characterized in that it includes a multi-screen control unit for generating. 2. The multi-screen control unit includes a horizontal / vertical counter for addressing a reproduction buffer memory, and a horizontal / vertical overflow detection unit for detecting an overflow by inspecting a most significant bit of an output value of the horizontal / vertical counter. A flip-flop for temporarily stopping the horizontal / vertical counter, a plurality of multiple screen address generators for each screen state, and one of the outputs of the multiple screen address generators under the control of the microcomputer. 2. The multiple screen control circuit for an electronic still camera according to claim 1, further comprising a multiplexer for selectively outputting the. 3. A read address designation for one screen or a plurality of image data recorded in the main memory is applied to a page address on the main memory from a microcomputer, and the multiple screen control section applies to the image data recorded on each page. 2. The multiple screen control circuit for an electronic still camera according to claim 1, wherein a read address is designated. 4. The multiple screen address generator provides a count value that is an even multiple of the input clock.
A counter, a second counter for providing an integer multiple count value, and the first counter
A first multiplier connected to the counter; a first adder for adding the output values of the first and second counters; a horizontal address generator having a horizontal overflow detector; A third counter that provides an even multiple count value, a fourth counter that provides an integer multiple count value, a second multiplier connected to the third counter, and a third counter and a fourth counter. A second adder for adding output values, a vertical address generator having a vertical overflow detector, and an OR gate for ORing outputs of the horizontal overflow detector and the vertical overflow detector. 2. The multiple screen control circuit of the electronic still camera described in 2. 5. The flip-flop receives a clock for driving the horizontal / vertical counter and the multiple screen address generator, and supplies a clock to the horizontal / vertical counter and the multiple screen address generator when a horizontal or vertical overflow is detected. 3. The multi-screen control circuit of an electronic still camera according to claim 2, wherein the multi-screen control circuit is configured to interrupt. 6. The flip-flop according to claim 2, wherein the flip-flop is configured to restart the clock supply to the horizontal and vertical counters and the multiple screen address generator in response to the clock supply control signal from the microcomputer. Item 5. A multiple screen control circuit for an electronic still camera according to item 5. 7. The horizontal overflow detection unit or the vertical overflow detection unit is a final unit of one horizontal or vertical line of image data recorded in the main memory from the horizontal address generation unit or the vertical address generation unit of the multiple screen address generation unit. The multiple screen control circuit for a still camera according to claim 4, wherein the multiple screen control circuit is configured to detect a portion. 8. The multiple screen control circuit for an electronic still camera according to claim 5, wherein the horizontal overflow detection unit is configured to clear the first counter and the second counter when a horizontal overflow is detected. . 9. The multiple screen control circuit of the electronic still camera according to claim 5, wherein the vertical overflow detection unit is configured to clear the third counter and the fourth counter when a vertical overflow is detected. . 10. An electronic still camera in which a picked-up video signal is digitized and stored in a memory and an image is displayed by a reproducing means, for inputting an image displayed in a search mode or for inputting a search end command. Screen selecting section, a microcomputer that performs a predetermined control by receiving an instruction from the screen selecting section, and a control for the microcomputer to read one screen recorded in the main memory or a predetermined number of image data in the search mode. In the multiple screen control circuit of the electronic still camera including the multiple screen control unit that generates an address, if the search mode is not specified, it operates in the general system operation mode, and if the search mode is specified, the playback buffer memory is used. The process of prohibiting output to the image display section and controlling the multiple screen control section from the microcomputer according to the command from the screen selection section A reproduction process of reading image data from the main memory and recording it in the reproduction buffer memory, an output process of restarting output from the reproduction buffer memory to the image display unit after the recording process is completed, and the output process described above. A standby process of performing the operation and waiting for the command of the screen selection unit, and a return process of reproducing the screen displayed before performing the search process and returning to the normal mode when the search end signal is received from the standby process. A multi-screen control method for an electronic still camera, including: 11. The page number on the main memory is sequentially specified from the screen selection section, the number of pages input by the microcomputer is counted, and the multiple screen control section is controlled by the value. The multiple screen control method for an electronic still camera according to claim 10. 12. The address of image data to be read out on the main memory is specified by a page address in a microcomputer, and the multiple screen control unit is specified by horizontal and vertical addresses within a page specified by the microcomputer. The multiple screen control method for an electronic still camera according to claim 10, wherein: