JPH0546280A - Backup circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] In memory backup, by setting the battery capacity small, the cost of the device itself is suppressed, and miniaturization of the device is promoted. [Configuration] In a backup circuit including a memory 103 that holds an operating state of the apparatus, adjustment data, etc., and a capacitor 106 and a battery 114 as a power source for holding the memory 103, charging of the capacitor 106 is executed when the power is turned on,
It is characterized in that backup is performed by discharging the capacitor 106 when the power is turned off, and when the capacity of the capacitor 106 reaches a predetermined value, backup is performed by the battery 114.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a backup circuit for a peripheral circuit controlled by a CPU, and more particularly to a backup system for a backup circuit having a capacitor and a battery as a power source for holding a memory.

[0002]

2. Description of the Related Art In recent years, in a device using an MCU (microprocessor), the function of the device has been improved by accumulating the adjustment data of the device, logging data during operation, etc. in a memory. These data must be retained even when the power supply of the device is turned off. As a method, a static RAM in CMOS (complementary metal oxide semiconductor) is backed up by a battery. It is common to hold data.

[0003]

However, when a battery is used in the backup, the battery has a life due to its characteristics, and further, the life varies greatly due to the consumption current of the static RAM of the CMOS as a load. Therefore, it is necessary to design the battery capacity so that it has a capacity value that can compensate for the life of the device.Therefore, it is necessary to use an expensive battery, which increases the cost of the device itself. It was In addition, since a large-capacity large battery is used, it is necessary to secure a space for arranging the battery in the device, and there is also a problem that it hinders downsizing of the device.

The present invention has been made in view of the above points, and it is an object of the present invention to suppress the cost of the device itself by setting the battery capacity small in the backup of the memory and to promote the downsizing of the device. And

[0005]

In order to achieve the above object, the present invention provides a storage means for holding the operating state of the apparatus, adjustment data, etc., and a backup provided with a capacitor and a battery as a power source for holding the storage means. In the circuit, the charging of the capacitor is executed when the power is turned on, backup is performed by discharging the capacitor when the power is turned off, and when the capacity of the capacitor reaches a predetermined value, a backup circuit that backs up by the battery is provided. Is.

Further, it is preferable that the predetermined value is set higher than the holding voltage of the storage means.

[0007]

Operation: Based on the above configuration, the capacitor is charged by the power source O
Since the memory is backed up by discharging the capacitor when the power is off and the battery is backed up when the capacity of the capacitor reaches a predetermined value, it is possible to set a small battery capacity for backup.

That is, when the power of the device is turned on, the electric charge is stored in the large capacity capacitor, and when the power of the device is turned off, the backup operation of the CMOS RAM is performed from the capacitor to discharge the electric charge of the capacitor.
When the capacitor voltage becomes lower than the holding voltage of the RAM, the backup is switched to the battery side to back up the RAM.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of a backup circuit according to the present invention, in which 101 is Vcc.
Part, 102 is a diode, 103 is a memory, 104 is a diode, 105 is a resistor, 106 is a capacitor, 107
Is a power supply monitoring circuit, 108 is a diode, 109 is an operational amplifier, 110 is a monitoring circuit including the operational amplifier 109, 11
Reference numeral 1 is a constant voltage circuit, 112 and 113 are resistors, 114 is a battery, 115 and 116 are transistors, 117 and 118 are constant current sources, and power is applied to the Vcc unit 101 when the device power is turned on, and the diode (D2) 102 Power is applied to the memory (M) 103 via the. Further, the capacitor (C1) 106 is charged through the diode (D4) 104 and the resistor (R1) 105.

At this time, the power supply monitoring circuit 107 determines whether or not the power supply voltage can access the memory (M) 103, and puts the memory (M) 103 in the ENABLE state. This enables access from an MCU (not shown) connected to the memory (M) 103. When the power supply of the device is turned off, the power supply voltage of the Vcc section 101 decreases. Therefore, in the power supply monitoring circuit 107, in order to prevent erroneous access from the MCU, the memory (M) 103
To the DISABLE state.

The power supplied from the diode (D2) 102 to the memory (M) 103 is fully charged by the capacitor (C1) 106 and the resistor (R1) 1
05, memory (M) through diode (D3) 108
Is supplied to 103. At this time, the capacitor (C1) 1
A monitoring circuit 11 for monitoring the voltage of the capacitor (C1) 106 composed of the operational amplifier (OP1) 109 is provided at 06.
0 is added. The monitoring circuit 110 monitors whether or not the power supply voltage supplied from the capacitor (C1) 106 to the memory (M) 103 is compensated for at least the holding voltage of the CMOS RAM.

The circuit symbol V _B in the monitoring circuit 110 is
This is a constant voltage circuit 111 which is negatively biased by using the capacitor (C1) 106 as a power source.
1) When the voltage of 106 drops to the holding voltage of the memory (M) 103, it is slightly higher than the potential of the connection point of the resistor (R1) 105 and the resistor (R2) 112 that is negatively biased by the capacitor (C1) 106. Set to voltage value.

Further, circuits other than the memory (M) 103 which is negatively charged by the capacitor (C1) 106, an operational amplifier (OP1) 109, a constant voltage circuit (V _B ) 111, a resistor (R2) 112 and a resistor (R3). The impedance of 113 is configured by a CMOS (not shown) or the like so that the power consumption of the power supply is about the same as the holding current of the memory (M) 103.

Here, if the voltage of the capacitor (C1) 106 has dropped to near the holding voltage of the memory (M) 103 while the power source of the apparatus has been off for a long time, the constant voltage circuit (V _B ) 111 and resistance (R2) 11
2. The output of the operational amplifier (OP1) 109 becomes “L” level when the potentials of the contacts of the resistors (R3) 113 match, and the memory (M) 103 from the battery (V _BAT ) 114.
To the power supply.

This operation is performed by the operational amplifier (OP1) 109.
The transistor (Q3) 115 is turned off by the output of "L" level. As a result, until now, the transistor (Q3) 115 has been replaced by the transistor (Q2) 11
6, the state in which the base bias voltage of the transistor (Q2) 116 is held at the turn-off potential is released, the transistor (Q2) 116 is turned on, and the memory (M) 103 _{receives the} battery (V _BAT ) 114 It switches to power supply.

The circuit symbols J1 and J2 are batteries (V
A constant current source 117, 118 to be Makezei from _BAT) 114, the constant voltage circuit (V _B) 111 in the same manner as in sufficiently high circuit impedance, sufficient minor load on the battery (V _BAT) 114 load Is configured as.

When the backup circuit of the memory (M) 103 is configured as described above, in the case of an apparatus such as a copying machine that normally turns on / off the power every day, the battery capacity is the stock period from the factory shipment. A long-term vacation (3 months, etc.) may be set, and a relatively inexpensive battery can be selected as a backup circuit of the memory (M) 103.

[0018]

As described above, according to the present invention,
Storage means for holding the operating state of the device, adjustment data, etc.,
In a backup circuit including a capacitor and a battery as a power source for holding the storage unit, the capacitor is charged when the power is turned on, and when the power is turned off, the capacitor is discharged to perform backup, and the capacity of the capacitor reaches a predetermined value. At this time, since the backup is performed by the battery, the cost of the device itself can be suppressed and the device can be downsized by setting the battery capacity to be small in the memory backup.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a backup circuit according to the present invention.

[Explanation of symbols]

 103 Memory 106 Capacitor 107 Power Supply Monitoring Circuit 109 Operational Amplifier 110 Monitoring Circuit 114 Battery

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 7323-5L G11C 11/34 335 B

Claims (2)

[Claims] 1. A backup circuit comprising a storage means for holding an operating state of the apparatus, adjustment data and the like, and a backup circuit provided with a capacitor and a battery as a power supply for holding the storage means, the charging of the capacitor is executed when the power is turned on, and the power is turned off. A backup circuit, wherein backup is sometimes performed by discharging the capacitor, and when the capacity of the capacitor reaches a predetermined value, backup is performed by the battery. 2. The backup circuit according to claim 1, wherein the predetermined value is set higher than a holding voltage of the storage means.