JPH0548052A - Semiconductor device - Google Patents

Abstract

(57) [Summary] [Configuration] In a master-slice semiconductor device,
The basic cell is composed of four transistors of each conductivity type, two of which are connected to the gate electrodes of one transistor, and four transistors are connected to one source / drain region. The structure is shared, and an area for arranging the power supply wiring and a contact hole for connecting to the power supply wiring is provided on the area. [Effect] A power-saving type macro cell and a high drive type macro cell can be configured by using one basic cell without changing the number of transistors used.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a basic cell structure of a CMOS large scale integrated circuit by a master-slice method.

[0002]

2. Description of the Related Art In a conventional master-slice semiconductor device, as shown in FIG. 4, a basic cell is composed of two or more adjacent transistors sharing a source / drain region, and each of them has a conductive structure. The channel widths of the transistors of the same type were the same.

[0003]

With further miniaturization in recent years, master-slice semiconductor devices are required to have higher speed and higher integration. However, as the integration becomes higher, the power consumed in the chip must increase.

However, in the conventional basic cell, the channel width is 1
Since there are only seeds, it is 1 in the macro cell of the same logic.
Only the power consumption of the seeds should be given.

Normally, a basic cell aiming at power saving reduces the channel width, but this causes a decrease in driving capability at the same time, and power saving and high speed cannot be simultaneously satisfied by one kind of basic cell. Met.

The present invention is intended to solve such a problem, and an object of the present invention is to configure a basic cell with four conductivity type transistors, two of which have one gate electrode. The structure is such that the four transistors are connected to one gate terminal lead-out portion, and one source / drain region is shared by four transistors, and a power supply line and a contact hole for connecting to the power supply line are provided on the region. An object of the present invention is to provide a semiconductor device that simultaneously has low power consumption and high speed by providing an area for arrangement.

[0007]

The semiconductor device of the present invention comprises:
A master-slice in which a plurality of input / output cells are arranged to form an external cell area, a plurality of basic cells are arranged to form an internal cell area, and a macro cell is composed of a plurality of the basic cells and a wiring layer composed of a plurality of layers. In a semiconductor device, in the basic cell, a first insulation type field effect transistor of a first conductivity type and a second insulation gate of a first conductivity type.
The gate electrode of the gate type field effect transistor is connected to the first gate terminal lead-out portion, and the first conductivity type third insulated gate type field effect transistor and the first conductivity type in the basic cell are connected. Type fourth insulating gate type field effect transistor has a gate electrode connected to the second gate terminal lead-out portion, and the first conductivity type first, second, third and fourth electrodes. The insulating gate type field effect transistors share one source / drain region, and the second conductive type first insulating gate type field effect transistor and the second insulating type field effect transistor in the basic cell are provided.
The gate electrode of the conductive second insulating gate type field effect transistor is connected to the third gate terminal lead-out portion, and the second conductive third insulating gate of the basic cell is provided. -Type field effect transistor and a fourth insulating gate of the second conductivity type
The gate electrode of the gate type field effect transistor is connected to the fourth gate terminal lead-out portion, and the first, second, third and fourth insulating gate type field effect transistors of the second conductivity type are provided. Respectively share one of the source / drain regions, and on the source / drain regions of the first, second, third and fourth insulation gate type field effect transistors of the first conductivity type. A first power supply wiring is arranged, and a source / drain region under the first power supply wiring has a region in which at least one contact hole can be arranged. 2, third,
A second power supply wiring is disposed on the source / drain region of the fourth insulation gate type field effect transistor,
The source / drain region under the power supply wiring has a region in which at least one contact hole can be arranged.

[0008]

1 is a diagram of an embodiment of a basic cell of a semiconductor device according to the present invention. The P-channel insulation gate type field effect transistors 101, 102, 103 and 104 are the source and
The drain region 107 is shared, and the transistors 101 and 102 are formed by being connected by the same layer as the gate terminal lead-out portion 105, and similarly, the transistors 103 and 104
Are connected in the same layer as the terminal lead-out portion 106. The VDD and VSS power supply wirings made of the first layer wiring are arranged on the four P-channel and N-channel transistors, respectively, and the region 10 for arranging the contact holes is arranged.
By arranging the contact holes at 8, 109, 110, 111, 112 and 113, that area can be used as a source.

The power supply wiring is not limited to the first-layer wiring, but the second-layer wiring is used as the power-supply wiring, and the power-supply wiring and the source region are connected to the first-layer wiring and the contact hole. You can use it to connect. 1B and 1C are respectively AA ′ and B- in FIG.
It is sectional drawing in B '. A field oxide film 120 separates the transistors 101 and 102.

FIG. 2A is a diagram in which a 2-input NAND is constructed by using this basic cell. Reference numeral 201 is a VDD power supply wiring consisting of a first layer wiring, 202 is also a VSS power supply wiring, 203 is a first layer wiring, and 204 is a gate terminal extraction portion or a source / drain region and a first layer wiring. It is a contact hole to be connected.

At this time, the source / drain regions 205, 2
Reference numerals 06, 210, 211, 213, and 214 are respectively connected to the power supply wiring and used as a source.
Is used as a drain, but the source / drain region 208 is not used. Therefore, as the power consumption, the charge / discharge current is reduced by the amount corresponding to the source / drain region 208, and the power consumption as the macro cell can be reduced.

On the other hand, in FIG. 2B, the source / drain region 208 is also used as a drain, so that the source / drain region 208 can be used as a macro cell without impairing the driving ability.

3 (a) and 3 (b) are also examples in which the inverter is constituted by the basic cell according to the present invention. In FIG. 3A, since the source / drain regions 305 and 311 are used as sources and only 304 and 308 are used as drains, the drain area can be reduced and power consumption can be suppressed. However, in FIG. 3B, the source / drain regions 303 and 3 are formed.
09 is also used as a drain to form a macro cell for high driving.

[0014]

As described above, the basic cell is composed of each conductivity type 4 transistor, and the gate electrodes of two transistors of each are connected to one gate terminal lead-out portion, and The two transistors have a structure in which one source / drain region is shared, and a source drain and a region for arranging a contact hole for connecting to the power source line are provided on that region, so that the source drain Only by selecting whether or not to use the area, it is possible to configure the power-saving macro cell and the high-driving macro cell with the same logic and the same basic cell. Therefore, if you want to keep the power consumption of the entire chip low, use a macro cell for power saving.If you do not want to keep the power consumption low, use a high-driving macro cell if you want a high-driving and high-speed configuration. By doing so, a more diversified circuit configuration can be realized with one basic cell.

[Brief description of drawings]

1 is a diagram of a basic cell according to the present invention and a cross-sectional view thereof.

FIG. 2 is a schematic diagram of a basic cell according to the present invention used for power saving.
It is a figure which comprised the input NAND and the high drive 2-input NAND.

FIG. 3 is a diagram in which a power saving inverter and a high drive inverter are configured using the basic cell according to the present invention.

FIG. 4 is a diagram of a conventional 4-transistor and 6-transistor basic cell.

[Explanation of symbols]

101: 1st P channel insulation gate type field effect transistor 102: 2nd P channel insulation gate type field effect transistor 103: 3rd P channel insulation gate type field effect transistor 104: 4th P-channel insulation gate type field effect transistor 105: first gate terminal lead-out portion 106: second gate terminal lead-out portion 107: source / drain region 108-113: contact hole arrangement region 114: VDD power wiring 115: Gate electrode 116: Gate oxide film 117: Diffusion 118: Well 119: Substrate 120: Field oxide film 201: VDD power wiring 202: VSS power wiring 203: Contact hole 204: First layer wiring 205 to 214: Source / drain region 215: Via contact 216: Second layer wiring 301: VDD power supply wiring 302: VSS power supply wiring 303: Contact hole 304: First layer wiring 305 to 314: Source / drain region 315: Via contact 316: Second layer wiring 401: Gate electrode 402: Source Drain region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI Technical indication location H01L 27/092 H03K 19/173 7827-5J 7342-4M H01L 27/08 321 L

Claims (2)

[Claims] 1. A macrocell is formed by arranging a plurality of input / output cells to form an external cell area, arranging a plurality of basic cells to form an internal cell area, and comprising a plurality of the basic cells and a plurality of wiring layers. In the master-slice semiconductor device described above, a gate of the first conductivity type first insulation gate type field effect transistor and the first conductivity type second insulation gate type field effect transistor in the basic cell is provided. The gate electrode is connected to the first gate terminal lead-out portion, and the first conductivity type third insulating gate type field effect transistor and the first conductivity type fourth insulating gate in the basic cell are connected. The gate electrode of the gate type field effect transistor is connected to the second gate terminal lead-out portion, and the first conductivity type first, second, third,
The fourth insulating gate type field effect transistor shares one source / drain region, and the second conductive type first insulating gate type field effect transistor and the second insulating type field effect transistor in the basic cell are provided. The gate electrode of the conductive second insulating gate type field effect transistor is connected to the third gate terminal lead-out portion, and the second conductive third insulating gate of the basic cell is provided. Type field effect transistor and the gate electrode of the second conductivity type fourth insulating gate type field effect transistor are connected to the fourth gate terminal lead-out portion, and the second conductivity type first, A semiconductor device in which each of the second, third and fourth insulating gate type field effect transistors shares one source / drain region. 2. The first, second, third and fourth of the first conductivity type.
A first power supply wiring is disposed on the source / drain region of the insulation gate type field effect transistor, and the source / drain region under the first power supply wiring has at least one contact hole. And a second power source wiring on the source / drain regions of the first, second, third and fourth insulation gate type field effect transistors of the second conductivity type. And a source / drain region under the second power supply wiring has a region in which at least one contact hole can be arranged.