JPH056151A - Drive method for liquid crystal display device - Google Patents

Abstract

PURPOSE:To restrain decrease of voltage applying time on a picture element accompanied with high quality orientation of a liquid crystal display device and increase of consuming electric power of an output buffer accompanied with alternating current drive of liquid crystal original by shifting a clear time for taking away the time and signal of sampling reset. CONSTITUTION:By separately providing a clear signal 23 to take away the output signal of a liquid crystal display panel in a specified time, against the reset signal of sample hold circuits 21, 22 of a drain driver of a liquid crystal display device, voltage application on the liquid crystal display panel is taken away to restrain power consumption of an output buffer in the midst of the term of sampling and reset, and in a remaining time, voltage is applied in a sufficiently long time on the liquid crystal display panel so as to improve the picture quality.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method for an active matrix type liquid crystal display device, and more particularly to a driving method for lengthening an application time of a video signal to the liquid crystal display device.

[0002]

2. Description of the Related Art FIG. 5 shows an active matrix type LC.
FIG. 11 is a block diagram of a conventional liquid crystal display device having a general gate driver (scan side driver) and a drain driver (signal side driver) used in D.

The gate driver 1 is composed of a shift register 2, a latch 3 and an output buffer 4 (there may be no latch).

On the other hand, the drain driver 5 comprises a shift register 6, a sample and hold circuit 7, and an output buffer 4.

A horizontal start signal 9, a clock signal 10, and a reset signal 11 are input to the shift register 6 on the drain side.

A sampling pulse corresponding to the number of horizontal pixels of the liquid crystal panel 8 and a video input signal 12 are applied from the shift register 6 to the sample-hold circuit 7.

A vertical start signal 13 is inputted to the shift register 2 on the gate side.

The operation of the drain driver will be briefly described below.

The shift register 6 operates at a frequency obtained by dividing the approximate number of pixels of the liquid crystal panel 8 by the horizontal effective display period of the signal source, and outputs a sampling pulse for sampling the video input signal 12.

For example, when the operating frequency is NTSC, f = 6 when the number of horizontal pixels of the liquid crystal panel is 640 pixels.
40 / 52μs ≈ 12MHz → 6MHz by dividing the terminal into 2
Becomes

In the case of HDTV, if the number of horizontal pixels of the panel is 1440 pixels, f = 1440 / 25.8 μs≈5
5.8 MHz → Similarly, it becomes about 28 MHz.

The output (sampling pulse) of the shift register controls ON / OFF of the switch as a control signal of the sample hold circuit.

On the other hand, a video input signal is connected to the input of the switch in the sample hold circuit, and the value when the switch is turned on is stored in the hold capacitor of the switch output stage by the sampling pulse.

This sample hold operation is sequentially repeated to store the data for one horizontal scanning period, and then all the data for one horizontal scanning period are simultaneously supplied to the liquid crystal panel by the output buffer.

The time when the output buffer is turned on and the data is supplied to the liquid crystal panel 8 is limited to the horizontal blanking period, and the TFT 1
When 4 is turned on, a voltage is applied to the liquid crystal 15.

As shown in FIG. 6, the input video signal is always sampled during the effective display period 16 of one horizontal scanning period, and the sampled data is output within the horizontal blanking period 17. If this is not done, rewriting of data will occur, and sufficient charging / discharging must be performed in a short time. (Since the liquid crystal panel needs to be driven by alternating current, charging / discharging is necessary when rewriting data. Become).

The shift register reset period 18 is a period obtained by subtracting the shift register operation period from the entire period of the video input signal.

That is, as shown in FIG. 7, the output current (Ic) and the inflow (Idc) are output currents of the driver.
Both operations are required, so the driver output stage impedance
The dance must be lowered, which is a problem that leads to an increase in driver power consumption.

In FIG. 7, when the video signal output from the buffer amplifier has a positive polarity, it is output from the output FET to the TFT1 in the liquid crystal panel.
4, a current 19 flows into the liquid crystal 4, and when the polarity is negative, a current 20 flows from the TFT 14 in the liquid crystal panel into the output FET.

OE is a signal for controlling the output period to the liquid crystal panel, and Vb is a signal serving as a bias voltage for controlling the output current.

Conventionally, the reset signal RS of the shift register
The signal OE for controlling the output period to T and the liquid crystal panel was the same signal.

[0022]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and suppresses an increase in power consumption of a liquid crystal driver, and properly writes data to a liquid crystal to provide a high quality image. The purpose is to get.

[0023]

The above-mentioned problems can be solved by separating the timings of outflow and inflow of the driver output stage and arbitrarily setting the period for applying a signal to the column electrodes of the liquid crystal display panel.

That is, in a driving method of a so-called active matrix type liquid crystal display device in which a switching element is added to each picture element of a display, a function of resetting a shift register for generating a sampling pulse and a sample signal of an input video signal are stored. Has a function of clearing the signal output applied to the column electrodes of the liquid crystal display panel to a certain level, and the reset time of the shift register and the time of clearing the output are respectively set. It can be realized by controlling individually.

[0025]

According to the present invention, the impedance of the driver output stage can be increased, and the charge / discharge to the liquid crystal panel can be controlled regardless of the reset period of the shift register for generating the sampling pulse and the specifications of the video input signal. In addition, it is possible to suppress an increase in current consumption and to perform driving in accordance with the characteristics of the active matrix liquid crystal panel, so that high quality image display can be realized.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a driving circuit having a two-circuit configuration of the sample-hold circuit of the present invention and having a function of clearing a driver output to a certain constant level.

When the sample hold circuit has two circuits, the sample hold is switched every horizontal scanning period, so that the output buffer is turned on and the data is supplied to the liquid crystal panel in one horizontal scanning period. If it is inside, it will not be specifically limited.

This is because during the scanning period of a certain line (n), the first sample-hold circuit 21 sample-holds and the second sample-hold circuit 22 outputs (n-1) -line data. Output.

Next, in the scanning period of the (n + 1) th line, the data of the (n) th line is output from the first sample-hold circuit 21 and the data of the (n + 1) th line is output to the second sample-hold circuit 22. This is because one sample-hold circuit can use all of the next horizontal scanning period for data output after sampling one horizontal scanning period because the operation of sampling and holding data is repeated.

However, if the sample-hold circuit is composed of only two circuits, both the outflow and inflow operations are required as the output current of the driver as in the conventional example, which leads to an increase in the power consumption of the driver.

For this reason, in the circuit example of FIG. 1, the output is cleared to a certain level, and the output current of the driver is made to flow out or is limited to flowing in only.

The sample-hold circuit is composed of a sampling section at the front stage, a hold section at the middle stage, and an output switching section at the rear stage.

The first sample-hold circuit 21 is logically ANDed by the second AND circuit of the second pulse (2H in FIG. 1) which is inverted every horizontal scanning period and the sampling pulse SP from the shift register by the second AND circuit. In the case of H (high), the sampling unit including the inverter and the analog switch samples the video input signal.

On the other hand, the second sample hold circuit 22 is
L is obtained by the logical product of 2H in which 2H is inverted and the sampling pulse SP from the shift register by the first AND circuit.
Since it is (low), it is not sampled.

The video signal sampled by the first sampling circuit 21 is held by a capacitor.

When held by a capacitor,
After the first sample-hold circuit, the second sample (2H (see Fig. 1)
2H) and ¬CL (shown as _CL in FIG. 1) by a third AND circuit and 2H and ¬CL
Due to the AND operation of the fourth AND circuit (indicated by CL in FIG. 1), no signal is sent to the output buffer until the next CL becomes L (low).

On the other hand, the video signals held in the capacitor of the second sample-hold circuit during the previous one horizontal period are 2H (indicated by 2H in FIG. 1) and CL (FIG. 1).
Then, the current CL is L (low) by the logical product of the third AND circuit of () CL and the logical product of the second AND circuit of 2H and ¬ CL (shown by _CL in FIG. 1). At the same time, the video signal is sent to the output buffer and a voltage is applied to the liquid crystal of the liquid crystal panel.

In FIG. 1, the output of the output buffer is set to the ground potential by the clear signal 23.

The potential (connection potential) connected through the analog switch by the clear signal must be smaller than the extreme value of the signal on the negative side of the video signal to be inverted when the liquid crystal panel flows into the connection potential.

On the other hand, when writing into the liquid crystal panel is performed with a flow-in current, the connection potential set by the clear signal is set to be larger than the extreme value of the signal on the positive side of the video signal to be inverted.

As described above, the signal for controlling the period for clearing the output to a certain level is independently provided and separated from the reset signal of the shift register.

That is, the driver output is forcibly set to the GND level by the control signal CL to clear the drain potential of the liquid crystal panel, and the image data is written at a time other than CL.

Therefore, the output clear time can be set irrespective of the effective display period and sampling period of the video signal, so that the driving can be performed in conformity with the characteristics of the active matrix type liquid crystal panel.

For example, considering the driving of the above-mentioned HDTV, conventionally, 25.8 μ of the horizontal scanning period of 29.6 μs is used.
Since s (1440 / 55.8 MHz) was used as the sampling period, the output period (time for writing data to the liquid crystal) was only 3.8 μs, and it was difficult to write correct data.

Alternatively, the impedance of the output stage needs to be made extremely low in order to cope with the data writing in a short time. However, according to the present invention, as described above, other signals and specifications are used. Since the output stage can be controlled completely independently of
Since it suffices to charge and discharge during the horizontal scanning period of 29.6 μs, it is possible to write data with a sufficient margin (for example, about half the horizontal scanning period = 14 μs to clear the remaining data). It is sufficient to write the data in 15 μs).

That is, it is possible to perform driving in conformity with the characteristics of the active matrix liquid crystal panel, and it is possible to realize high quality image display.

In the embodiment of the present invention, the sample hold circuit has two systems, but more sample hold circuits may be provided.

FIG. 2 shows a waveform diagram of the driving method of the liquid crystal display device of the first embodiment of the present invention.

2 to 4 show an embodiment of the present invention,
(A) of each figure shows the waveform of the video input signal 12, (b) of each figure
Is the waveform of the horizontal start signal 9 that sets the start of sampling, (c) of each figure is the waveform of the clock signal 10 that uses the rising and falling timings, (d) of each figure.
Is a waveform of the reset signal 11 for resetting the shift register, (e) of each figure is a sampling period indicating a sample hold period in the first sample hold circuit, (f) of each figure is the second sample A sampling period showing a period for sampling and holding in the hold circuit, (g) of each figure shows the waveform of the clear signal 23 for setting the liquid crystal panel to a constant potential,
(H) of each figure shows an output clear period in which a constant voltage is applied to the liquid crystal, and (i) of each figure shows a writing period in which a video signal is applied to the liquid crystal.

In FIG. 2, the video input signal 12 shown in FIG.
Sampling of the portion A is held in the first sample hold circuit as the sampling A by the horizontal start signal STH and the clock signal CKH, and the signal CL is L.
At the time of (low), the writing A is written in the liquid crystal panel.

Then, the video input signal 1 by the next STH.
The B portion of 2 starts to be sampled, and the reset signal R
By ST, the sampling hold to the second sample hold circuit is stopped and the writing B is written in the liquid crystal panel.

Further, the portion C of the video input signal is held as a video signal in the first sample hold circuit and written as write C in the liquid crystal panel.

When the writing time is longer than the output clearing time as shown in FIG. 2, it is advantageous when it takes time to charge the liquid crystal.

FIG. 3 shows a waveform diagram of the driving method of the liquid crystal display device of the second embodiment of the present invention.

The method of FIG. 3 has the advantage that the reset signal 11 is selected at the same time as the clear signal 23 and the timing can be adjusted with the same start signal, which simplifies the circuit.

If the output clear time is set to be slightly longer than the write time, the response time from when an electric field is applied to when no electric field is applied like TN (twisted nematic) liquid crystal and PD (polymer-dispersed) liquid crystal. Is suitable when the response time from when no electric field is applied to when an electric field is applied takes longer.

Further, in this case, the impedance of the clear circuit section of the driver output stage can be increased.

FIG. 4 shows a waveform diagram of the driving method of the liquid crystal display device of the third embodiment of the present invention.

The reset signal RST shown in FIG. 4 is the clear signal C.
Since it does not overlap with L in terms of time, the flow-out time from the liquid crystal and the reset time of the shift register do not overlap, and there is no interference between both signals.

When the end of sampling of the sample hold circuit and the end of the clear signal are made to substantially coincide with each other, the capacitor portion in the sample hold circuit is not discharged and the portion A of the video input signal is sampled by the sampling hold circuit. There is an advantage that it can be written in the liquid crystal display device immediately after being stored as the video signal A.

[0061]

EFFECTS OF THE INVENTION By the two-system sample-hold circuit,
By arbitrarily controlling the data writing period to the liquid crystal display panel, it becomes possible to drive the liquid crystal display panel in conformity with the characteristics of the active matrix liquid crystal panel and realize high quality image display.

Further, since the impedance of the driver output stage can be increased, the driver and the display module are
Low power consumption.

[Brief description of drawings]

FIG. 1 is a drive circuit diagram of a drain driver of a liquid crystal display device of the present invention.

FIG. 2 is a drive waveform diagram of a liquid crystal display device of the present invention in which the timings of two signals are shifted.

FIG. 3 is a drive waveform diagram of a liquid crystal display device of the present invention in which two signals are simultaneously raised.

FIG. 4 is a drive waveform diagram of a liquid crystal display device in which two signals are separated according to the present invention.

FIG. 5 is a block diagram of a drive circuit of a conventional liquid crystal display device.

FIG. 6 is a drive waveform diagram of a conventional liquid crystal display device.

FIG. 7 is a drive circuit diagram of a drain driver of a conventional liquid crystal display device.

[Explanation of symbols]

1 Gate driver 2 shift registers 3 latch 4 output buffer 5 drain driver 6 shift registers 7 sample hold circuit 8 LCD panel 9 Horizontal start signal 10 clock signals 11 Reset signal 12 Video input signal 13 Vertical start signal 14 TFT 15 LCD 16 Effective display period 17 Horizontal return period 18 Shift register reset period 19 Outflow current 20 Inflow current 21 First Sample Hold Circuit 22 Second sample-hold circuit 23 Clear signal

Claims (5)

[Claims] 1. A so-called active matrix type liquid crystal display device in which a switching element is added to each picture element of a liquid crystal display panel, a circuit having a function of resetting a shift register for generating a sampling pulse, and two circuits. The sample hold circuit and the circuit for clearing the signal output applied to the column electrodes of the liquid crystal display panel to a certain level are provided, and the reset time of the shift register and the output clear time can be individually controlled. Driving method for liquid crystal display device. 2. A so-called active matrix type liquid crystal display device in which a switching element is added to each picture element of a liquid crystal display panel, a circuit having a function of resetting a shift register for generating a sampling pulse, and two circuits. The sample and hold circuit described above, the circuit that clears the signal output applied to the column electrodes of the liquid crystal display panel to a certain level, and the reset time is set shorter than the time for writing the data signal to the picture element when there is no clear signal. And a writing circuit which has a writing time longer than a horizontal blanking period. 3. A so-called active matrix type liquid crystal display device in which a switching element is added to each picture element of a liquid crystal display panel, a circuit having a function of resetting a shift register for generating a sampling pulse, and two circuits. The shift register includes the sample-hold circuit described above, a circuit that clears the signal output applied to the column electrodes of the liquid crystal display panel to a certain level, and a circuit that simultaneously generates a reset signal and a clear signal that ends midway during the sampling time. The method for driving a liquid crystal display device, characterized in that the reset start time and the output clear start time are matched to lengthen the writing time to the picture element. 4. A so-called active matrix type liquid crystal display device in which a switching element is added to each picture element of a liquid crystal display panel, a circuit having a function of resetting a shift register for generating a sampling pulse, and two circuits. The sample-hold circuit described above, a circuit that clears the signal output applied to the column electrodes of the liquid crystal display panel to a certain level, and a circuit that matches the sampling end time with the clear end time are provided. The method for driving a liquid crystal display device is characterized in that the time for clearing is separated from the time for clearing, and writing to the picture element is performed immediately after sampling. 5. A shift register for stopping the output of sampling pulses by a reset signal existing in a specific period, a first AND circuit for individually receiving two inputs per sampling pulse from the shift register, and a second AND circuit. Of the AND circuit, the first AND circuit and the second AND circuit, which are the input components of the respective periodic signals that are inverted within one horizontal period, the inverted periodic signal that is the inverted signal, the inverted periodic signal, and the liquid crystal panel Third AND circuit for inputting an inversion clear signal which is an inversion signal of the clear signal for controlling the outflow time of the current, a fourth AND circuit for inputting the periodic signal and the inversion clear signal, and a second AND circuit And a first sample-hold circuit composed of two sets of inverters and analog switches for receiving the outputs of the third AND circuit and the fourth AND circuit, A second sample and hold circuit consisting of two sets of inverters and analog switches for receiving the outputs of the first and third AND circuits, and a video input signal for the first and second sample and hold circuits. It passes through the sample hold circuit and becomes one input signal of the output buffer,
The clear signal is applied to the two sets of inverter and the analog switch to set both the input signal of the output buffer and the other input signal to the ground potential, and the input signal of the output buffer and the write signal from the output buffer. A method for driving a liquid crystal display device, comprising a circuit for writing in a switching element of a liquid crystal panel.