JPH0564015A - Image encoding device and image decoding device - Google Patents

Abstract

(57) [Abstract] [Object] The present invention relates to an image information compression apparatus and an image decoding apparatus, which can realize encoding with a smaller amount of conversion operation and reduce the amount of code without causing deterioration of a reproduced image. It is an object of the present invention to provide an image encoding device that can be performed and an image decoding device that performs decoding with a smaller amount of calculation. A first storage means 1 for dividing an image to be encoded into a plurality of value ranges and holding the same, a conversion means 3 for converting a set of pixel values in a variable range by a specified conversion method, and a conversion means 3. The second storage unit 5 that holds the conversion result, the comparison unit 7 that compares the degree of approximation between the pixel value set of the range and the pixel value set of the variable range, and the result of the comparison unit 7 show that the degree of approximation is high. A code determining means 9 that outputs a variable as a variable for a designated value range, a control means that controls the first storing means 1, the converting means 3, the second storing means 5, the comparing means 7, and the code determining means 9. And 11 and 13.

Description

Detailed Description of the Invention

[Object of the Invention]

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image information compressing apparatus and an image decoding apparatus, and more particularly, it is possible to realize encoding with a smaller amount of conversion operation and to cause deterioration of a reproduced image with a smaller number of blocks. The present invention relates to an image coding apparatus that can reduce the code amount and that performs coding with a smaller calculation amount, and an image decoding device that performs decoding with a smaller calculation amount.

[0003]

2. Description of the Related Art Image data compression technology has been actively developed, and one of them is the iterative transform coding method (AEJacquin, "Fractal image cod").
ing based on a theory of iterated contractive imag
etransformation ', SPIE Vol.1360 VCIP'90. and Ida, Taketake "Image compression by iterative transform coding", 1991 IEICE Spring National Convention, Lecture No. D-341). This method realizes compression by utilizing the self-similarity of the image, and has the advantage that a code describing the self-similar structure of the image can be obtained and a texture faithful to the original image can be obtained in the reproduced image. .. Further, since the code amount thereof is smaller than the original image data amount, it can be used for image data compression.

A schematic block diagram of this conventional image coding apparatus is shown in FIG.

The image coding apparatus according to the conventional example divides an image to be coded into a plurality of blocks and holds the frame memory 1, and a set of pixel values in an arbitrary area of the frame memory 1 for a conversion method designation signal 53. A converter 3 for converting based on
A comparator 7 for comparing the degree of approximation between a set of pixel values of a designated block in the frame memory 1 and a set of transformed pixel values, and an area having a high degree of approximation from the result of the comparator 7 for the designated block. A code determination circuit 9 that outputs a code as a region, a control unit 11 that controls the frame memory 1, the converter 3, the comparator 7, and the code determination circuit 9, a range designation signal 51, a range designation signal 52, and a conversion method. The signal generating circuit 13 outputs the designation signal 53.

First, the image to be encoded 4 is stored in the frame memory 1.
1 is stored. The image 41 to be encoded is divided into square blocks, and a code 49 is determined for each block. Reference numeral 49 is specifically a rectangular area 1 in the image.
9 and information about a conversion method for appropriately converting the pixel set in the rectangular area 19. This rectangular area 19 is called a conversion range, and the corresponding block 18 is called a conversion range. Then, the domain 19 and the conversion method are determined for each range block so that the result obtained thereby closely approximates the data of the range 18. Therefore,
Most of the operations in the image coding apparatus are spent searching for an ideal domain and conversion method.

To determine the reference numeral 49, the signal generating circuit 1
The range designation signal 51 and the range designation signal 52 are sent from 3 to the frame memory 1. As a result, the range data 43 and the range data 44 are output from the frame memory 1. The domain data 44 is converted into domain data 47 by the converter 3.

FIG. 18 shows an example of the internal structure of the converter 3. In the figure, the range data 44 is first reduced by the pixel number conversion circuit 21 so that the number of pixels becomes equal to the number of pixels in the range. Next, the pixel arrangement conversion circuit 23 replaces the pixels in line symmetry or rotates them by 90 degrees. Finally, the pixel amplitude direction compression circuit 25 suppresses the amplitude at a constant reduction rate. Each conversion method is designated by the conversion method designation signal 53 each time.

Next, the comparator 7 inputs the range data 47 and the range data 43 converted as described above, and evaluates their degree of approximation. As the degree of approximation, the sum of squares of the errors between corresponding pixels is generally used. This evaluation value 4
8 is sent to the code determination circuit 9, and it is determined that the smaller the sum of squares of the error, the higher the degree of approximation.

The controller 11 sequentially and by trial and error designates the domain and the conversion method for one range, evaluates the degree of approximation each time, and searches for the optimum domain and conversion method.

The domain determining signal 52 and the conversion method designating signal 53 at that time are input to the code determining circuit 9, and the information about the domain and the conversion method having the highest degree of approximation up to that point is code 49. Is output as.

The above operation is controlled by the control signals 61 to 66 from the controller 11.

However, in the configuration of this conventional image coding apparatus, each time the domain and the conversion method are specified at the time of search,
The domain data is read from the frame memory 1 and the converter 3
Therefore, it is necessary to perform the conversion, and the calculation amount of this conversion becomes very large. For example, when the number of blocks (the number of range values) is 1024, the number of variable areas is 2048, and the number of conversion methods is 64, the combination of all variable areas and conversion methods is 2048 × 64 = It becomes 131,072 (street). Therefore, since this is repeated for the number of blocks,
The number of times the domain data is processed by the converter 3 is 131072 × 1024 = 134,217,728 per screen.
It also becomes (times). Therefore, the time required to encode one screen becomes enormous.

Further, in the conventional iterative decoding method, the method of dividing blocks of image data on the decoding side has the following problems.

As described above, the image is first divided into a plurality of blocks on the frame memory 1, and then, for each block, an area having an image pattern similar to the image pattern is searched for from another portion of the same image. .. Here, the two image patterns being similar to each other means that the pixel patterns match each other by linear enlargement / reduction conversion in the screen or in the pixel amplitude direction, or simple pixel exchange conversion (rotation or line-symmetric exchange). Say something. The information on the position of the found area (domain) and the conversion method becomes the code for each block. In practice, it is rare to find a transform in which the image patterns match, and a transform that minimizes the error between the block image and the transform is used as a code.

When reproducing an image, first, an appropriate initial image is prepared, and the conversion indicated by the symbol is applied to this initial image. That is, the pixel data is extracted from the domain shown for each block, and the pixel of the block is replaced with the converted data. When the conversion of the entire screen is completed,
The obtained image is transformed again. As the transformation is iteratively repeated in this way, the image converges on the encoded image. Then, the image repeated a certain number of times is used as a reproduction image.

Since the code amount for one screen is proportional to the total number of blocks, the number of blocks should be as small as possible.
That is, if the block is a rectangle of M × N pixels, M and N are preferably as large as possible. However, if the block size is excessively increased, the error between the block image and the conversion at the time of encoding becomes large, and the deterioration of the reproduced image becomes severe. Further, the error becomes large in a flat portion of the image pattern, and becomes larger as the image pattern becomes more complicated.

In the method of Ida of the above-mentioned document, the block size is preset and the entire screen is divided uniformly. In this case, in order to reduce an error in a block having a complicated image pattern, unless the block size is set small (for example, 4 × 4 pixels in the literature), the image quality is deteriorated. However, when the block size is reduced, the number of blocks increases and the code amount does not decrease so much as described above.

On the other hand, in the above-mentioned AEJacquin system, coding is first carried out in a block size of 8 × 8 pixels (parent block), and then four 4 × 4 pixel regions (child blocks) are each subjected to an error from the original image. (See FIG. 19). At this time, the following processing is performed depending on the number of child blocks whose error is larger than a predetermined value.

(A) When the number is 0 ... Only the code in the parent block is used (FIG. 19A). (B) When the number is 1 ... Encoding is also performed in the corresponding child block, and the code in the parent block and the code in one child block are used (FIG. 19 (b)).

(C) When the number is 2 ... Coding is also performed in the corresponding child block, and the code in the parent block and the code in two child blocks are used (FIG. 19 (c)).

(D) When the number is 3 to 4 ... Coding is performed with 4 child blocks and the code of 4 child blocks is used (FIG. 19 (d)).

In this method, two kinds of block sizes, large and small, can be adaptively used, but if the error is still large even with the size of the small block, it cannot be excluded, and the reproduced image is deteriorated. .. Also, to avoid that, the parent block cannot be too large.

Next, when decompressing an image in the image decoding apparatus, first, an appropriate initial image is prepared. The conversion indicated by the code is applied to this initial image. That is, pixel data is extracted from the domain given for each block,
The pixel of the block is replaced with the transformed one. When the conversion of the entire screen is completed, the obtained image is converted again. The image gradually converges to the coded image while the transform is iteratively performed. An image repeated a certain number of times is used as a reproduction image.

As described above, in the conventional image decoding,
Every time iterative conversion, all blocks are converted,
The total number of conversions in block units is the number of iterations × the total number of blocks, making high-speed decoding difficult.

[0026]

As described above, in the conventional image coding apparatus, (1) it is necessary to read the domain data from the frame memory and perform the conversion each time the domain and the conversion method are designated. Yes, the calculation amount of this conversion becomes enormous, and it takes a lot of time for the encoding process. (2) In the block division method of image data, there is a trade-off between image quality and the code amount when determining the block size. Even with the method of adaptively using two types of block sizes, there is a problem that the reproduced image is deteriorated or the code amount is increased.

Also, in the image decoding apparatus, since conversion of all blocks is executed every time iterative conversion is performed, the amount of decoding calculation becomes enormous, and a large amount of time is required for encoding processing. was there.

The present invention solves the above-mentioned problems.
The purpose is to (1) install a database memory that holds domain data after conversion for each domain position and conversion method, so that encoding can be realized with a smaller amount of conversion operation, and (2) image To provide an image coding apparatus that can adaptively set the block size when determining the block size of data and reduce the code amount without deteriorating the reproduced image, and partially in the iterative conversion. An object of the present invention is to provide an image decoding device that does not perform further conversion on a converged block and performs decoding with a smaller amount of calculation.

[0029]

In order to solve the above-mentioned problems, the first feature of the present invention is, as shown in FIG. 1, a first storage for holding an image to be coded by dividing it into a plurality of blocks. Means 1 and conversion means 3 for converting a set of pixel values in an arbitrary area of the first storage means 1 by a specified conversion method
A second storage means 5 for holding the conversion result of the conversion means 3; a set of pixel values of a designated block in the first storage means 1 and the second storage means 5; Comparing means 7 for comparing the degree of approximation with each set of pixel values, and code determining means 9 for outputting a code from the result of the comparing means 7 as an area for the designated block.
And the control means 11 and 13 for controlling the first storage means 1, the conversion means 3, the second storage means 5, the comparison means 7, and the code determination means 9.

The second feature of the present invention is as shown in FIG.
A first storage unit 1 for dividing an image to be encoded into a plurality of blocks and holding the same, and a conversion unit 3 for converting a set of pixel values in an arbitrary area of the first storage unit 1 by a specified conversion method. And the average value is separated from the set of pixel values of the designated block in the first storage means 1, and the set of pixel values of the block obtained by the average value separation and the average value are output and the conversion of the conversion means 3 is performed. An average value separating means 4 for separating and outputting the average value of the results, a second storage means 5 for holding the output of the average value separating means 4, a set of pixel values of the blocks for which the average value has been separated, and the above Comparison means 7 for comparing the degree of approximation with each set of pixel values held in the second storage means 5;
From the result of the comparison means 7, a code determination means 9 which outputs the area having a high degree of approximation as an area for the designated block, the first storage means 1, the conversion means 3, the average value separation means 4, and the second storage. It is provided with control means 11 and 13 for controlling the means 5, the comparison means 7, and the code determination means 9.

The third feature of the present invention is defined in claim 1 or 2.
In the image coding apparatus according to item 1, the control means 11 and 13 specify an arbitrary block in the first storage means 1, and specify all blocks for each possible area in the first storage means 1. The result of conversion by the conversion method is to be held in the second storage means 5.

A fourth feature of the present invention is the image coding apparatus according to claim 1, 2 or 3, wherein the converting means 3 is any of the first storing means 1 as shown in FIG. And a pixel number conversion circuit 21 for reducing the number of pixels in the area to be equal to the number of pixels in a designated block in the first storage means 1, and a pixel arrangement conversion for converting the arrangement of pixels according to a designated conversion method. A circuit 23 and a pixel amplitude direction compression circuit 25 that suppresses the amplitude at a constant reduction rate are provided, and the second storage unit 5 is installed on the output side of the pixel number conversion circuit 21 or the pixel arrangement conversion circuit 23. Is Rukoto.

The fifth feature of the present invention is as shown in FIG.
First storage means 1 for dividing and holding an image to be coded into a plurality of blocks, flatness measurement means 31 for measuring flatness of the blocks of the first storage means 1, and results of the flatness measurement means 31. A first block division means 33 for re-dividing the block division of the first storage means 1 from
Of the block in the first storage unit 1 designated by the first block dividing unit 33, and a conversion unit 3 for transforming a set of pixel values in an arbitrary area of the storage unit 1 by the designated conversion method. A comparing means 7 for comparing the degree of approximation between a set of pixel values and the output of the converting means 3; and a code determining means 9 for outputting a region having a high degree of approximation from the result of the comparing means 7 as an area for the designated block. , The first storage means 1, the flatness measurement means 31, the first block division means 33, the conversion means 3, the comparison means 7, and the code determination means 9.
And a control means 12 for controlling.

According to a sixth aspect of the present invention, in the image coding apparatus according to the fifth aspect, the flatness measuring means 31 obtains an average value of pixel data of each block, and the average value is less than a predetermined value. Sometimes it is determined to be flat, and the first block dividing means 33 integrates adjacent n (n: any positive integer) blocks into one block when it is flat.

The seventh feature of the present invention is, in the image coding apparatus according to claim 5, the flatness measuring means 31 obtains a variance value of the pixel data of each block, and the variance value is less than a predetermined value. Sometimes it is determined to be flat, and the first block division means 33 divides into m (m: any positive integer) blocks when an arbitrary block is not flat.

The eighth feature of the present invention is as shown in FIG.
A first storage unit 1 for dividing an image to be encoded into a plurality of blocks and holding the same, and a conversion unit 3 for converting a set of pixel values in an arbitrary area of the first storage unit 1 by a specified conversion method. And a comparing means 7 for comparing the degree of approximation between the pixel value set of the designated block in the first storage means 1 and the output of the converting means 3, and the degree of approximation is determined from the result of the comparing means 7. Second block division means 35 for re-dividing the block division of the first storage means 1 when the value is larger than
And a code determining means 9 for outputting a code from the result of the comparing means 7 as an area having a high degree of approximation as the area for the designated block, the first storing means 1, the converting means 3, the comparing means 7, and the second block. The control means 1 comprises a dividing means 35 and a control means 12 for controlling the code determining means 9.
2 is that the block is subdivided stepwise from the result of the comparing means 7 until the degree of approximation becomes a predetermined value or less, and the code determining means 9 determines the code.

The ninth feature of the present invention is as follows.
In the image coding apparatus described in 3, 4, 5, 6, 7, or 8, the comparison unit 7 uses the sum of squares of errors, the sum of errors, the maximum value of the errors, or the evaluation value of the approximation degree. It is to use an intermediate value or the like.

The tenth feature of the present invention is as follows.
In the image coding apparatus described in 3, 4, 5, 6, 7, 8 or 9, the code determination means 9 outputs, as a code output, position information of the determined area and information regarding a conversion method, and / or correspondence. It is to output the position information and / or the average value of the blocks to be processed.

The eleventh feature of the present invention is, as shown in FIG. 13 or 14, a fourth storage means 101 for dividing an image into a plurality of blocks and holding the same, a domain position for each block, and a conversion method. A fifth storage unit 103 that holds the second storage unit 103 and a second storage unit 103 that converts a set of pixel values of a designated block in the fourth storage unit 101 by the corresponding conversion method and stores the converted value in the fourth storage unit 101. Conversion means 105 and convergence determination means 107 for determining convergence from the set of pixel values before and after conversion of the block, and the second conversion means 105 is converged by the convergence determination means 107 for each block. It is to repeat the conversion until it is determined.

A twelfth feature of the present invention is to divide the image into a plurality of blocks and hold the fourth storage means 101, and to store a domain position for each block, a conversion method and the number of repetitions of the fifth storage means. Means 103 and second conversion means 105 for converting the set of pixel values of a designated block in the fourth storage means 101 by the corresponding conversion method and storing it in the fourth storage means 101. It is to have.

[0041]

In the image coding apparatus of the first, third, ninth and tenth features of the present invention, first, as shown in FIG. The conversion method designation signal 53 is sequentially supplied, and the domain data 44 in the first storage means 1 is converted by the conversion means 3 to generate the second
A database is created in the storage means 5. Next, the coding, that is, the search for the optimum combination of the domain and the conversion method is started. A range designation signal 51, a range designation signal 52, and a conversion method designation signal 53 are sequentially supplied from the signal generation circuit 13 to each component, and the comparison unit 7 is designated by the first storage unit 1. The range data 43 and the converted range data 47 designated by the second storage means 5 are input.
The comparing means 7 evaluates the degree of approximation of both, and outputs the evaluation value 48 to the code determining means 9, and the code determining means 9 outputs the information of the domain and the conversion method having the highest degree of approximation as a code 49. ..

As a result, prior to the search, the conversion results are stored as a database for all the domains that may be specified during the search, and the domain data read from the database during the search is directly used as range data. It is possible to make a comparison, and as a result, it is possible to reduce the amount of encoding calculation and to perform high-speed encoding.

In the image coding apparatus of the second, third, ninth and tenth features of the present invention, as shown in FIG. 2, first, the control means (signal generating circuit) 13 outputs the range change designation signal 52 and The conversion method designation signal 53 is sequentially supplied, and the domain data 44 of the first storage means 1 is converted by the conversion means 3,
Further, the average value separation means 4 subtracts the average value from each pixel value so that the average value of the data set becomes zero, and a database is created in the second storage means 5. Next, the coding, that is, the search for the optimum combination of the domain and the conversion method is started. At the time of searching, the range data 43 designated by the first storage means 1 and the converted range data 47 designated by the second storage means 5 are input to the comparison means 7, and the degree of approximation between them is evaluated. Then, the evaluation value 48 is output to the code determination means 9. Then, the code determination means 9 outputs the information of the domain and the conversion method having the highest degree of approximation as a code 49.

This makes it possible to obtain the same effect as that of the image coding apparatus of the first feature described above, and to use the average value of each block to reduce the number of iterations when decoding the average value separation type code. Images can be converged by the number of times, and high-speed decoding is possible.

In the image coding apparatus of the fourth feature of the present invention, as shown in FIG. 3, the second storage means 5 is installed on the output side of the pixel number conversion circuit 21 or the pixel arrangement conversion circuit 23. Therefore, although the speed of the encoding process is slower than that of the image encoding device having the first and second characteristics, it can be realized by the second storage unit 5 having a smaller capacity.

In the image coding apparatus of the fifth, sixth, ninth and tenth features of the present invention, first of all, as shown in FIG.
The block dividing means 33 divides one screen into the smallest block size. With respect to pixel data of n adjacent blocks, the flatness measuring circuit 31 obtains an average value of each block, and it is determined whether or not it is flat depending on whether or not the average value is below a predetermined width. When it is determined that the block is flat, the first block dividing unit 33 puts the corresponding n blocks into one block. This process is repeated stepwise to determine block division. Next, the coding, that is, the search for the optimum combination of the domain and the conversion method is started. At the time of searching, the range data 43 designated by the first storage unit 1 and the range data 47 converted by the conversion unit 3 are input to the comparison unit 7, the degree of approximation of both is evaluated, and the evaluation value 48 is obtained.
Is output to the code determination means 9. And the code determination means 9
Then, the information of the domain and the conversion method having the highest degree of approximation and the range position information are output as reference numeral 49.

As a result, the block size of the flat portion can be increased, the number of blocks can be reduced, and as a result, encoding with a smaller amount of calculation and a smaller amount of code can be realized.

In the image coding apparatus of the fifth, seventh, ninth and tenth features of the present invention, first of all, as shown in FIG.
The block dividing means 33 divides one screen into the maximum block size. With respect to the pixel data of any one block, the flatness measurement circuit 31 obtains an average value of each block, and it is determined whether or not it is flat depending on whether or not the average value is below a predetermined width. When it is determined that the block is not flat, the first block dividing unit 33 divides the corresponding block into m blocks. This process is repeated stepwise to determine the final block division. The encoding process is similar to that of the image encoding device having the sixth characteristic.

As a result, the block size of the flat portion can be increased, the number of blocks is reduced as a whole, and as a result, encoding with a smaller amount of calculation and a smaller amount of code can be realized.

In the image coding apparatus of the eighth, ninth and tenth features of the present invention, as shown in FIG. 5, first, the second block dividing means 35 divides one screen into the maximum block size. .. Next, the coding, that is, the search for the optimum combination of the domain and the conversion method is started. At the time of search, the comparison means 7 causes the range data 43 designated by the first storage means 1,
Also, the domain data 47 converted by the conversion means 3 is input, the degree of approximation of both is evaluated, and the evaluation value 48 is output to the code determination means 9. At this time, if the degree of approximation is less than or equal to a predetermined value, the code determining means 9 provides information about the domain and conversion method,
Also, the range position information is output as reference numeral 49, and when the degree of approximation is equal to or greater than a predetermined value, the second block dividing means 35.
Divides the block into m blocks. This process is repeated stepwise until the approximate value becomes less than or equal to the predetermined value.

This makes it possible to increase the block size of the flat portion, reduce the number of blocks, and leave almost no coding error. As a result, it is possible to realize highly accurate encoding with a smaller amount of calculation and a smaller amount of code.

In the image decoding apparatus having the eleventh feature of the present invention, as shown in FIG. 13 or 14, the fifth storage means 10 is used.
Enter the domain position and conversion method for each block into 3
The conversion means 105 converts the set of pixel values of the designated block in the fourth storage means 101 for each block by the corresponding conversion method and stores the converted value in the fourth storage means 101. Here, the convergence determination unit 107 determines the convergence from the set of pixel values before and after the conversion of the block, and repeats the conversion for each block until it is determined to be converged.

As a result, at the time of iterative transformation, a block that has already partially converged and does not need to be transformed is determined, and the corresponding block is not further transformed.
Decoding can be realized with a smaller amount of calculation.

In the image decoding apparatus of the twelfth feature of the present invention, the domain position for each block, the conversion method, and the number of iterations are input to the fifth storage means 103, and the second conversion means 105 is input.
Thus, for each block, the set of pixel values of the designated block in the fourth storage means 101 is converted by the corresponding conversion method by the number of iterations and stored in the fourth storage means 101. ing.

As a result, in the iterative transformation, only the designated number of iterations is performed, and unnecessary transformation is not repeated for blocks that converge in a small number of times, resulting in decoding with a smaller amount of calculation. realizable.

[0056]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of an image coding apparatus according to the first embodiment of the present invention. In FIG. 1, the same parts as those in FIG. 17 (conventional example) are designated by the same reference numerals and the description thereof will be omitted.

In the image coding apparatus of this embodiment, a database memory (second storage means) 5 is inserted between the converter 3 and the comparator 7 in the conventional image coding apparatus shown in FIG. In the database memory 5, the variable area designation signal 5
2 and the conversion method designation signal 53 are supplied.

In this embodiment, a database of domain conversion results is created in the database memory 5 prior to encoding. That is, the domain specifying signal 52 and the conversion method specifying signal 53 are sequentially supplied from the signal generating circuit 13, and the domain data 44 read from the frame memory 1 becomes the domain data 46 converted by the converter 3. , As data in the database memory 5. At this time, the address input of the database memory 5 is the domain designation signal 52 and the conversion method designation signal 53, and the domain data 44 converted into the designated address is stored.

In this way, for all combinations of the domain and the conversion method, when the domain data 46 has been stored in the corresponding addresses, the encoding, that is, the optimum combination of the domain and the conversion method is performed. Start exploring. When searching,
A range specifying signal 51, a range specifying signal 52, and a conversion method specifying signal 53 are sequentially supplied from the signal generating circuit 13 to each component, and the comparator 7 is supplied with the range data 43 specified from the frame memory 1. And the converted domain data 47 at the specified address are supplied from the database memory 5. The comparator 7 evaluates the degree of approximation between the converted range data 47 and the range data 43, and outputs the evaluation value 48 to the code determination circuit 9. Then, in the code determination circuit 9, the domain designation signal 52 and the conversion method designation signal 53 at that time are input, and the domain and the conversion method information having the highest degree of approximation until then are output as a code 49. ..

FIG. 6 shows a circuit diagram corresponding to the block diagram of the image coding apparatus according to the present embodiment of FIG. Using the figure,
A detailed description will be given of how each operation of image input, database creation, encoding, and code output in the image encoding apparatus of this embodiment is controlled by a control signal from the controller 11.

First, the controller 11 sends a signal for designating the writing state to the frame memory 1 by the control signal 61a. In addition, the signal generation circuit 13 is controlled by the control signal 66.
Sends the image input address to the selector 15 via the range designation signal 51. At the same time, if the selector 15 is instructed to select the range specifying signal 51 by the control signal 61b, the address 50 of the frame memory 1 is set to the image input address. With this, the encoded symmetrical image data 41 can be stored in the frame memory 1.

Write end signal 6 from the signal generation circuit 13
Upon receiving 6, the controller 11 starts to create a database. The frame memory 1 is instructed by the control signal 61a to be in the output state, and the signal generation circuit 13 is instructed by the control signal 66 to sequentially output the range designation signal 52 and the conversion method designation signal 53. And selector 1
5 is instructed to select the variable range designation signal 52 by the control signal 61b. Further, the converter 3 is instructed to output the conversion result by the control signal 62, and the database memory 5 is instructed to be in the writing state by the control signal 63. At this time, database memory 5
The address is the domain designation signal 52 and the conversion method designation signal 5.
3, the data of the combination of different domains and conversion methods can be stored without duplication.

Next, the controller 11 receives the signal 66 from the signal generating circuit 13 indicating that the creation of the database has been completed for all combinations of the domain and conversion method, and starts encoding. Indicate the output status to the database memory 5,
The signal generation circuit 13 is instructed to output the first range designation signal 51, the range designation signal 52, and the conversion method designation signal 53, and the converter 3 is instructed to put the output in a high impedance state. At this time, the selector 15 is instructed to select the range designation signal 51. This is the comparator 7
The range data 41 is input from the frame memory 1 and the converted range data 45 is input from the database memory 5. The comparator 7 calculates the degree of approximation of the two at the timing of the control signal 64 from the controller 11 and outputs it to the code determination circuit 9. The sign determination circuit 9 holds the approximation data 48 and the corresponding domain and conversion method.

When the control signal 65 indicates that the above series of processing is completed, the controller 11 instructs the signal generating circuit 13 to perform the same processing for the next domain and conversion method. From this, similar to the above procedure, the degree of approximation of the specified domain and conversion method is input to the code determination circuit 9. The code determination circuit 9 holds the one having a higher degree of approximation than the previously held degree of approximation, and also updates the corresponding domain and conversion method. In this way, the degree of approximation is checked for all combinations of the domain and the conversion method, and the code determination circuit 9 sets the information of the domain and the conversion method having the highest degree of approximation among them as the code 49 of the control signal 65. Output at timing. It is to be noted that, if all the combinations are not searched, the search is terminated when the degree of approximation equal to or more than a preset value is obtained, and the domain and the conversion method at that time are output as a code 49. Can save time.

Similarly, the code 49 is determined for the second and subsequent value ranges, and the encoding is terminated when the codes of all the value ranges are output.

As described above, in the image coding apparatus of this embodiment, the converted domain data 47 is held in the database 5, and at the time of searching, the address designation by the domain designation signal 52 and the conversion method designation signal 53 is carried out. Since it is supplied to the comparator 7 by the comparator 7, compared to the conventional case where the converter 3 performs conversion and supplies each one, the comparator after the domain designation signal 52 and the conversion method designation signal 53 are set. The time until the domain data 47 converted into 7 is supplied is shortened.

In the example used in the description of the prior art section, comparing the number of times conversion data is processed by the converter 3, the number of blocks is 1024, and the number of cases of domain is 2048.
When the number of conversion methods is 64, the converter 3 is used only when creating a database, and therefore 2048 × 64 = 131,072 (times), which is 1/1024 of the conventional case. Of course, the calculation at the time of encoding is other than the conversion of the domain data, but these are the same as those of the conventional image encoding device, and as a result, the amount of calculation per screen can be greatly reduced.

Next, as a modified example of this embodiment, the same effect can be obtained by configuring the database memory 5 inside the converter 3 as shown in FIG. The pixel number conversion circuit 21, the pixel arrangement conversion circuit 23, and the pixel amplitude direction compression circuit 25 that form the converter 3 are the same as those of the conventional one.

In this modification, data obtained by converting the domain data 44 by the pixel number conversion circuit 21 is stored in the database memory 5. When searching,
This pixel number converted data is read from the database memory 5, subjected to pixel arrangement conversion and pixel amplitude direction compression conversion, and then supplied to the comparator 7. Therefore, as in the above-described embodiment, the database is provided after the converter 3. Compared to the case where the memory 5 is arranged, the time from setting of the domain designation signal 52 and the conversion method designation signal 53 until the data arrives at the comparator 7 becomes longer, but the number of pixels is converted as compared with the conventional example. Will be shortened by the amount of. Further, the database memory 5 of this modification has a smaller capacity than that of the above embodiment.

Next, FIG. 2 shows a block diagram of an image coding apparatus according to the second embodiment of the present invention. In the figure, FIG.
The same parts as those of the (conventional example) and FIG. 1 (first example) are designated by the same reference numerals and the description thereof will be omitted.

The image coding apparatus of this embodiment is different from that of the first embodiment in that an average value separator 4 is used.
That is, the average value is separated from the set of pixel values of the specified range 18 in the frame memory 1, the range data 55 obtained by separating the average value and the average value 54 are output, and the average value of the conversion result of the converter 3 is output. Average value separator 4 which separates the average value and outputs the range data 56, the third memory 6 which holds the range data 55 where the average value is separated, and the range data 5 where the average value is separated.
And a database memory 5 for holding the data.

In this embodiment, when the database is created,
The average value of the data 45 converted by the converter 3 is subtracted from each pixel value by the average value separator 4 so that the average value of the data set becomes zero. The domain data 56 separated from the average value is stored in the database memory 5. The average value separator 4 may be provided inside the converter 3.

At the time of search, the data 57, which is obtained by separating the range data 43 designated by the range designating signal 51 by the average value separator 4 and holding it in the third memory 6, is inputted to the comparator 7. By providing the third memory 6 in this way,
Only one average value separation process is required for all combinations of the domain and conversion method.

The comparator 7 uses the range data 5 obtained by separating the average values.
7 and the specified domain data 47 from the database memory 5 are input, the degree of approximation of both is evaluated, and the evaluation value 48
Is output to the code determination circuit 9. Then, the code determination circuit 9
Then, the domain designation signal 52 and the conversion method designation signal 5 at that time
3 is input, and information about the domain and the conversion method that have the highest degree of approximation up to that point, and the average value 54 of the range are output as reference numeral 49.

Since the average value separation type iterative transform coding method of this embodiment can use each block average value at the time of decoding, the image converges with a small number of iterations and high-speed decoding is possible. Becomes

FIG. 7 shows a block diagram of a portion of the average value separator 4 which processes the range data 43. FIG. 7A shows a case where the average value separator 71 and the combiner 72 are simply used. In the combiner 72, the same value (average value) 54 is subtracted from the range data 43 for all pixels in the same block. To do. In this case, a step may occur at the block boundary of the range data 55 obtained by separating the average values, and block-like distortion may appear in the reproduced image, resulting in a problem. As a configuration for avoiding this problem, there are the following modifications.

FIG. 7B is a block diagram of the mean value separator 4 according to the modification of the second embodiment. 7 (a),
Temporary memory 73 for temporarily storing the average value of range data
And a smoothing circuit 74 for smoothing the average value of the range data are newly added.

The average value 54 of the range data is stored in the temporary memory 73.
However, at this stage, the adjacent block average values 54 have stepwise values as shown in FIG. 8A. Using this data, the smoothing circuit 74 makes data for each pixel that is smoothly connected at the block boundary as shown in FIG. 8B. However, even if smoothed, the entire unevenness should be preserved. The data for each pixel is subtracted from the range data 43 by the combiner 72. In this way, block distortion does not occur in the range data 55 after the average value separation.
If the encoding device and the decoding device share the same method of generating pixel data for smooth connection, the block average value 5
It is not necessary to include additional information other than 4 in the code.

In addition, in the first and second embodiments, as shown in FIG. 9, if an extra memory space is provided in the database memory 5 and an appropriate pixel pattern is stored in advance in the database memory 5, it is possible to store these in search. By using the pixel pattern of 1 as a code candidate, the efficiency of encoding can be improved. This is effective when it is not possible to obtain a high degree of approximation even by a combination of the domain and the conversion method.

Further, as the evaluation criterion of the degree of approximation, it is possible to use the sum of the errors, the maximum value of the errors, the intermediate value or the like in addition to the square sum of the errors.

Further, in the iterative coding method, it is usual not to select a parameter that expands in the pixel amplitude direction. Therefore, the variance of the range data is checked in advance, and the converted data of the range is stored in the comparator 7. If the variance is calculated before inputting and it is smaller than the variance of the range and it does not approach the range data unless it is expanded in the pixel amplitude direction, then the range does not need to be evaluated and the range is the sign of the range. If it is judged to be unsuitable for the above, and the search is shifted to the next domain, the amount of calculation at the time of encoding can be further reduced.

Next, FIG. 4 shows a block diagram of an image coding apparatus according to the third embodiment of the present invention.

The image coding apparatus according to the present embodiment divides an image to be coded into a plurality of blocks and holds the frame memory 1 and the flatness of the blocks of the frame memory 1.
From the result of the flatness measurement circuit 31, which measures the average value of the pixel data of each block, the average of the pixel data of adjacent n blocks (n: any positive integer, 4 in FIG. 10) When the value is less than or equal to a predetermined value, it is determined to be flat and integrated into one block, and the frame memory 1
The divided data memory 33 for re-dividing the block division of No. 1 and holding the information, the converter 3 for converting the set of pixel values of an arbitrary area of the frame memory 1 by the specified conversion method, and the divided data memory 33 A comparator 7 for comparing the degree of approximation or an error between the set of pixel values of the designated block in the frame memory 1 and the output of the converter 3;
From the result, the code determination circuit 9 that outputs the code having a high approximation degree (small error) as the area for the designated block, the frame memory 1, the flatness measurement circuit 31, the divided data memory 33, the converter 3, and the comparator 7 , And a controller 12 for controlling the code determination circuit 9.

In the present embodiment, the image to be encoded is first input to the frame memory 1 and block division information is created in the divided data memory 33 prior to encoding. This operation is performed in the following procedure.

First, in the divided data memory 33, as shown in FIG.
The division information with the minimum block size as shown in (a) is held. In this state, the positional information of the four adjacent blocks is sent to the address generating circuit 37, the pixel data of the block specified by the address 50 generated by the address generating circuit 37 is read from the frame memory 1,
It is input to the flatness measuring circuit 31 via the data bus 41. The flatness measuring circuit 31 obtains the average value of each block, and if they are within a predetermined width or less, it is determined to be flat. Conversely, if the average value has a large variation, it is determined to be not flat. The determination result is sent to the divided data memory 33 as flatness information 57.

If it is determined to be flat, the corresponding 4
The contents of the divided data memory 33 are rewritten to combine one block into one block. When it is determined that the data is not flat, the divided data memory 33 is not rewritten. FIG. 10B shows the state after the measurement of the flatness of the entire screen is completed and the divided data memory 33 is updated.

Next, with respect to the blocks grouped as being flat, the flatness is similarly measured in four adjacent blocks, and the contents of the divided data memory 33 are updated. The result is shown in FIG.

Further, the flatness information 57 is also input to the controller 12, and when it cannot be further grouped into a larger block as shown in FIG. 10C, or FIG.
Even in the state where the blocks can be combined into a larger block as shown in (b) and (b), if it is determined that all the candidates to be combined are not flat, the block integration process is terminated and the block division at that time is determined.

Next, encoding is performed with reference to the block division information held in the division data memory 33.

First, the domain position information 52a is output from the controller 12 in order to determine the domain position and the conversion method of conversion with the first block as the range, and the address generation circuit 37 is output.
Then, according to the variable area position information 52a, the frame memory 1
Generates the address 50 of the domain. The domain data 19 is supplied to the converter 3 via the data bus 41, reduced to the same number of pixels as the range data 18 in the converter 3, and further, the pixel amplitude indicated by the conversion method information 53a from the controller 12 is supplied. Directional compression, rotation within the pixel plane, and pixel swapping are performed.

The domain data 47 converted by the converter 3 is input to the comparator 7, and the divided data memory 33 is also supplied.
The range data 18 in the frame memory 1 designated by the address generated based on the position information 51a of the range block from is input via the data bus 41. Comparator 7
Then, the error of the range data 47 with respect to the range data 18 is measured and sent to the code determination circuit 9 as error data 48a.

The controller 12 performs the above-mentioned error evaluation for various variable areas and conversion methods. The variable area position information 52a
And the conversion method information 53a are also input to the code determination circuit 9, and the code determination circuit 9 always holds the domain position information 52a and the conversion method information 53a when the value of the error data 48a becomes smaller. , Where the error is small, that is, when the search for the domain and the conversion method having a high degree of approximation is completed, the domain block position information 51a and the domain range information 52a
And the conversion method information 53a is output as a code 49a under the control of the timing signal 65 from the controller 12. These codes 49a may be further compressed by another method.

As a modified example of this embodiment, an image coding apparatus according to the following method can be considered. That is, in the above method, the block division is decided from the finest block division and the blocks are put together. On the contrary, as shown in FIG. 11, the block division is decided. Starting from the coarsest block division, the flatness measurement circuit 31 checks the distribution of pixel data for each block, and when the dispersion is large, the block is subdivided into a plurality of smaller blocks. In this case, the flatness measuring unit 31 obtains the variance value of the pixel data of each block and outputs it as the flatness information 57, and the divided data memory 33 is not flat when the variance of the pixel data of an arbitrary block is equal to or more than a predetermined value. And m (m: any positive integer, 2 or 4 in FIG. 11)
Divide into blocks.

As described above, in the image coding apparatus of the present embodiment, the degree of flatness of each part of the input image is measured before the coding, and the block size of the flat part is set to be large, and the flat part is not flat. For, set a smaller block size. In this way, in order to keep the error below a certain value, in the case of fixed block size, it is necessary to reduce the size of all blocks according to the non-flat part, whereas in variable block size, The block size can be increased, the number of blocks is reduced, and thus the code amount is also reduced. Also, compared to the conventional variable block size method, it is possible to generate several types of block sizes with a small amount of calculation, and the block size is not changed at the time of encoding. There is no need to perform multiple encodings such as a child block.

Next, FIG. 5 shows a block diagram of an image coding apparatus according to the fourth embodiment of the present invention.

The image coding apparatus according to the present embodiment has a frame memory 1 that divides an image to be coded into a plurality of blocks and holds it, and a conversion method in which a set of pixel values in an arbitrary area of the frame memory 1 is designated. The converter 3 for converting by the following, the comparator 7 for comparing the degree of approximation or the error between the set of pixel values of the block in the designated frame memory 1 and the output of the converter 3, and the degree of approximation from the result of the comparator 7. And a code determination circuit 9 that outputs a high (small error) region as a region for the designated block, and when the result of the comparator 7 indicates that the degree of approximation or the error is larger than a predetermined value, the code determination circuit 9 issues a subdivision instruction. In response to the signal 58, the divided data memory 35 for re-dividing the block division of the frame memory 1, the frame memory 1, the converter 3, the comparator 7, the code determination circuit 9,
And a controller 12 which controls the divided data memory 35 to re-divide the block step by step until the degree of approximation of the result of the comparator 7 becomes less than or equal to a predetermined value and causes the code determining means 9 to determine the code. Has been done.

The present embodiment differs from the third embodiment in that block division is performed simultaneously with encoding.

The divided data memory 35 holding the block divided information first holds the divided information divided into relatively large blocks as shown in FIG. 12A, and the controller 12 uses the third information. By the same procedure as the embodiment of the above, for the range 18 designated by the range block position information 51a from the divided data memory 35, a variable range and a conversion method in which the error 48a is reduced are searched.

When the error 48a becomes smaller than a predetermined value, the code determination circuit 9 determines the domain and conversion method at that time, and the domain block position information 51a together with the domain position information 52a and the conversion method. The information 53a is output as reference numeral 49a under the control of the timing signal 65 from the controller 12. On the other hand, when the error 48a does not become smaller than the predetermined value, the re-division instruction signal 58 is output to the division data memory 35, and the division data memory 35 re-divides the block whose error has not become smaller than the predetermined value. Then, the range block position information 51a is updated.

In FIG. 12, the shaded portions represent blocks whose sign has been determined, and the white background portions represent undetermined blocks. In FIG. 12B, the block whose code has not been determined is further divided into two and the above-mentioned processing is performed, and in FIG.
The image encoding process has been completed. That is, FIG.
From (a) to (b) and (c) in the figure, the sign of each block is determined step by step.

The threshold value used in the error determination performed by the code determination circuit 9 is a squared error per pixel or an absolute value error.

If the block size becomes too small, the number of blocks will increase and the number of codes will increase. Therefore, the minimum value of the block size is set, and the error of the block of that size is larger than the threshold value. There is also a method of determining a domain and a conversion method in which the minimum error is obtained in the search range.

Next, FIG. 13 shows a block diagram of an image decoding apparatus according to the fifth embodiment of the present invention.

The image decoding apparatus of this embodiment inputs a frame memory (fourth storage means) 101 for dividing an image into a plurality of blocks and holding the same, and a code string 49 as shown in FIG. 16 (a). A buffer memory (fifth storage means) 103 for holding the domain position and conversion method for each block, an address generation circuit 117 for addressing the frame memory 101, and a designated block in the frame memory 101 A second converter (second conversion means) 105 for converting a set of pixel values by the corresponding conversion method and storing it in the frame memory 101, and a set of pixel values of the block of the frame memory 101 before conversion are saved. 6th to keep
From the output of the memory 109 and the set of pixel values before and after conversion of the block, that is, the difference between the output 155 of the second converter 105 and the output 156 of the sixth memory 109, and the output 157 of the subtractor 111 It is composed of a controller 113 that makes a determination and controls the conversion of the block to be repeated until it converges, and a display unit 115 that displays the image data in the frame memory 101.

First, when the present invention is used as an image decoder of a TV telephone or a TV conference system, a code line 49 is used by a communication line or, in the case of a digital VTR, from a storage medium.
Is input, and codes for all blocks are stored in the buffer memory 103. Next, the decoding is started, but the initial image of the frame memory 101 is arbitrary, and it is not necessary to set the initial image again.

First, the control signal 159 from the controller 113.
Accordingly, the address generation circuit 117 causes the frame memory 10
The address of 1 is designated and the pixel value of the first block is read. The read pixel value is stored in the sixth memory 109.
Stored in.

Next, the control signal 158 from the controller 113.
By this, the variable area position information 151 is output from the buffer memory 103, the address 152 corresponding to the variable area is generated by the address generation circuit 117, and the frame memory 101 is designated. The pixel value of the addressed domain is the second converter 1
The data is input to the frame 05, subjected to linear enlargement / reduction conversion in the screen or in the pixel amplitude direction and simple pixel exchange conversion, and the converted data 155 is overwritten in the first block in the frame memory 101. Here, the conversion method for the first block is supplied from the buffer memory 103 to the converter 105.

The subtractor 11 takes the difference between the converted data 155 and the unconverted data 156 in the sixth memory, and outputs it to the controller 113. The controller 113 uses this difference 157.
Is smaller than a preset value, the block is stored as a block that has already converged. Similarly, for the second and subsequent blocks, all blocks are converted once for each block, and the first conversion of the entire screen is completed. Then, the second and third conversions will be performed,
From the second time onward, no further rewriting processing is performed on the already converged blocks. Then, when the number of iterations of conversion reaches a preset value or when it is determined that all the blocks have converged, the decoding ends, and the decoded image is output to the display unit 115.

As described above, since the iterative conversion is omitted for the converged block, the total conversion calculation amount can be reduced.

Next, FIG. 14 shows a block diagram of an image decoding apparatus according to the sixth embodiment of the present invention.

The image decoding apparatus of the present embodiment has a configuration almost equivalent to that of the fifth embodiment. In the fifth embodiment, the convergence determination means 107 is the sixth memory 109 and the subtractor. 111 and the controller 113, the present embodiment is different only in that the flat block detection circuit 121 for detecting the flatness of the converted data and the controller 113.

In the present embodiment, the determination as to whether or not convergence has occurred is
Only the converted data is used using 155. The entire decoding algorithm is the same as that of the fifth embodiment, except that the data 155 converted for each block is input to the flat block detection circuit 121 and the determination signal 160 as to whether the block is flat is obtained.

The flat block detection circuit 121 is composed of a maximum value detection circuit 123, a minimum value detection circuit 125, and a subtractor 127, for example, as shown in FIG. 15A, and determines the difference between the maximum value and the minimum value. The signal 160 is output to the controller 113.

In the iterative transform coding method, the flatter part is more likely to converge. That is, there is a tendency that the conversion amount at the time of replacement tends to decrease. Therefore, since iterative conversion may be performed once or twice for a flat block in which the determination signal 160 becomes equal to or less than a predetermined value, the subsequent conversion is omitted as a converged block. However, when the initial image is a flat image, the blocks that converge to a non-flat image also become flat converted data in the first and second conversions, causing erroneous determination. , The first few conversions are always performed for all blocks, and the subsequent convergence blocks are determined.

As another flat block detection circuit 121, there is also a method in which the variance is used as the decision signal 160. The configuration is shown in FIG. First, the average value detection circuit 129 calculates the average value 163 of the input converted image data 155.
And the average value 1 from the image data 155 by the subtractor 131.
Subtract 63. The result 164 is squared by the squaring circuit 133, and the adder 135 obtains the sum of all pixels in the loop portion via the delay 137. This is output as the determination signal 160.

Next, an image decoding apparatus according to the seventh embodiment of the present invention will be described. The image decoding apparatus according to the present embodiment has the same configuration as that of the fifth or sixth embodiment except that the convergence determining unit 107 is removed.

In this embodiment, as shown in FIG.
Since the code 49 includes data of the number of iterations for each block in advance, the code amount increases by the information of the number of iterations as compared with the code of FIG. 16A, but the decoding device detects a converged block. No circuits needed. At the time of decoding, the controller 113 converts only the block having the number of iterations N or more at the N-th iterative transformation, and the frame memory 1
The data of 01 is replaced.

The number of iterations on the side of the encoder is set by the method of setting a small number of blocks having a small approximation error in addition to the method of setting a small number of blocks having small variances or maximum and minimum values as described above. Can also be considered.

If the conversion method includes a reduction ratio in the pixel amplitude direction, the number of iterations may be reduced as the reduction ratio increases. This is because a block having a higher reduction ratio converges faster. According to this method, it is not necessary to additionally add the number of iterations to the code 49.

[0121]

As described above, according to the image coding apparatus of the first, third, ninth, and tenth features of the present invention, all the images that may be specified at the time of searching prior to searching. For the domain, store the conversion result as a database,
Since the domain data read out from the database is directly compared with the range data at the time of search, it is possible to provide an image coding apparatus capable of performing high-speed coding with a smaller amount of calculation.

The second, third, ninth, and first aspects of the present invention
According to the image coding apparatus having the feature of 0, the same effect as that of the image coding apparatus having the first feature can be obtained, and the mean value separation type coding is performed. , The image can be converged in a small number of iterations by using the average value of each block, and high-speed decoding is possible.

Further, according to the image coding apparatus of the fourth feature of the present invention, the second storage means is installed inside the conversion means. Therefore, the image coding apparatus of the first and second characteristics is provided. Although the speeding up of the encoding process is slower than that of the above, it can be realized with a smaller storage capacity.

Further, according to the image coding apparatus of the fifth, sixth, seventh, ninth and tenth features of the present invention, the block size is increased in the flat part and increased in the non-flat part. Since the size is reduced, it is possible to reduce the number of blocks, and as a result, it is possible to provide an image encoding device that can perform encoding with a smaller amount of calculation and a smaller amount of encoding.

According to the image coding apparatus of the eighth, ninth, and tenth features of the present invention, with respect to a portion having a large coding error, the process of re-dividing the block and performing the comparison has a predetermined error. Since the process is repeated until it becomes the following, the block size of the flat part can be increased, the number of blocks is reduced, and almost no coding error remains. As a result, it is possible to provide an image encoding device that can perform high-precision encoding with a smaller amount of calculation and a smaller amount of encoding.

Further, according to the image decoding apparatus of the eleventh feature of the present invention, at the time of iterative transformation, a block which has already partially converged and does not need to be transformed is determined, and the corresponding block is not further transformed. Therefore, it is possible to provide an image decoding device that can perform decoding with a smaller amount of calculation.

According to the twelfth feature of the image decoding apparatus of the present invention, only a specified number of iterations is transformed during iterative transformation, and unnecessary transformation is not repeated for blocks that converge with a small number of iterations. Therefore, it is possible to provide an image decoding device that can perform decoding with a smaller amount of calculation.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an image encoding device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of an image coding apparatus according to a second embodiment of the present invention.

FIG. 3 is an internal configuration diagram of a converter of the image encoding device according to the first embodiment of the present invention.

FIG. 4 is a configuration diagram of an image coding device according to a third embodiment of the present invention.

FIG. 5 is a configuration diagram of an image coding apparatus according to a fourth embodiment of the present invention.

FIG. 6 is a circuit configuration diagram of the image encoding device according to the first embodiment of the present invention.

FIG. 7 is a configuration diagram of a portion that processes range data in an average value separator of the image encoding device according to the second embodiment of the present invention.

FIG. 8 is an operation explanatory diagram of the image encoding device according to the second embodiment of the present invention.

FIG. 9 is a memory map of the image coding apparatus according to the first or second embodiment of the present invention.

FIG. 10 is a diagram illustrating block division of the first storage unit of the image encoding device according to the third embodiment of the present invention.

FIG. 11 is a diagram illustrating block division of the first storage unit of the image encoding device according to the modification of the third embodiment of the present invention.

FIG. 12 is a diagram illustrating block division of the first storage unit of the image encoding device according to the fourth example of the present invention.

FIG. 13 is a configuration diagram of an image decoding apparatus according to a fifth embodiment of the present invention.

FIG. 14 is a configuration diagram of an image decoding device according to a sixth embodiment of the present invention.

FIG. 15 is a configuration diagram of a flat block detection circuit of an image decoding device according to a sixth embodiment of the present invention.

FIG. 16 (a) is a code string of an image decoding device according to the fifth and sixth embodiments of the present invention, and FIG. 16 (b) is a code string of the seventh embodiment of the present invention. It is a figure explaining.

FIG. 17 is a configuration diagram of a conventional image encoding device.

FIG. 18 is a configuration diagram of a converter of a conventional image encoding device.

FIG. 19 is a diagram illustrating block division of a frame memory of a conventional image encoding device.

[Explanation of symbols]

 1 1st storage means (frame memory) 3 conversion means (converter) 4 average value separation means (average value separator) 5 second storage means (database memory) 6 third storage means (third memory) 7 Comparing Means (Comparators) 9 Code Determining Means (Sign Determining Circuits) 11, 12 Control Means (Controller) 13 Control Means (Signal Generating Circuits) 18 Ranges (Blocks) (Range Data) 19 Ranges (Range Data) 21 pixel number conversion circuit 23 pixel arrangement conversion circuit 25 pixel amplitude direction compression circuit 31 flatness measurement means 33 first block division means (divided data memory) 35 second block division means (divided data memory) 37 address generation circuit 41 data Bus 42 Input data 43 Range data 44 Domain data 45, 46, 47 Domain data after conversion 48 Approximate value data 48a Error data 4 Code (information about range and conversion method) 49a Code (information about range, range, and conversion method) 50 Address of frame memory 51 Range specification signal 52 Range specification signal 53 Conversion method specification signal 51a Range block position information 52a Change Range position information 53a Conversion method information 54 Average value data of range 55 Range data separated by average value 56 Range data separated by average value 57 Flatness information 58 Redivision instruction signals 61 to 66 Control signal 71 Average value separator 72 Combiner 73 Temporary memory 74 Smoothing circuit 101 Fourth storage means (frame memory) 103 Fifth storage means (buffer memory) 105 Second conversion means (second converter) 107 Convergence determination means 109 Sixth memory 111, 127, 131 Subtractor 113 Controller 115 Display 117 Address generating circuit 121 Flat block Clock detection circuit 123 maximum value detection circuit 125 minimum value detection circuit 129 average value detection circuit 133 squaring circuit 135 adder 137 delay 151 variable range position information 152 address signal 153 conversion method information 155 converted pixel data 157 difference signal 158 , 159 Control signal 160 Judgment signal

Claims (12)

[Claims] 1. A first storage unit that divides an image to be encoded into a plurality of blocks and holds the block, and a set of pixel values in an arbitrary area of the first storage unit is converted by a designated conversion method. Conversion means, second storage means for holding the conversion result of the conversion means, a set of pixel values of a designated block in the first storage means, and each held in the second storage means Comparing means for comparing the degree of approximation with a set of pixel values; code determining means for outputting a region having a high degree of approximation as a region for the designated block from the result of the comparing means; the first storing means, the converting means And a second storage means, a comparison means, and a control means for controlling the code determination means. 2. A first storage unit that divides an image to be encoded into a plurality of blocks and holds the block, and a set of pixel values in an arbitrary region of the first storage unit is converted by a specified conversion method. Converting means, separating the average value from the set of pixel values of the designated block in the first storage means, outputting the set of pixel values of the separated average value and the average value, and converting the converting means An average value separating means for separating and outputting the average value of the results, a second storage means for holding the output of the average value separating means, a set of pixel values of the blocks subjected to the average value separation, and the second Comparing means for comparing the degree of approximation with each set of pixel values held in the storage means; code determining means for outputting a region having a high degree of approximation as a region for the designated block from the result of the comparing means; First storage means, An image coding apparatus comprising: a conversion unit, an average value separation unit, a second storage unit, a comparison unit, and a control unit that controls the code determination unit. 3. The control means designates an arbitrary block in the first storage means, and converts the conversion results obtained by all conversion methods for each possible area in the first storage means to the second storage area. The image encoding device according to claim 1 or 2, wherein the image encoding device is held in the storage means. 4. The pixel number conversion circuit for reducing the number of pixels in an arbitrary area of the first storage unit to be equal to the number of pixels in a designated block in the first storage unit. A pixel arrangement conversion circuit for converting the arrangement of pixels according to a designated conversion method, and a pixel amplitude direction compression circuit for suppressing the amplitude at a constant reduction rate, wherein the second storage means is the pixel number conversion circuit or The device is installed on the output side of the pixel arrangement conversion circuit.
Alternatively, the image encoding device according to item 3. 5. A first storage means for dividing an image to be encoded into a plurality of blocks and holding the same, a flatness measuring means for measuring flatness of the blocks of the first storage means, and a flatness measuring means of the flatness measuring means. A first block dividing means for re-dividing the block division of the first storing means from the result; and a converting means for converting a set of pixel values in an arbitrary area of the first storing means by a designated converting method. , Comparing means for comparing the degree of approximation between the set of pixel values of the block in the first storage means designated by the first block dividing means and the output of the converting means, and approximating from the result of the comparing means A code determining means for outputting a code with a highly frequent area as an area for the designated block, and controlling the first storage means, flatness measuring means, first block dividing means, converting means, comparing means, and code determining means. An image coding apparatus, comprising: 6. The flatness measuring means obtains an average value of pixel data of each block, determines that the pixel data is flat when the average value is less than a predetermined value, and the first block dividing means makes adjacent n The image coding device according to claim 5, wherein when (n: any positive integer) blocks are flat, the blocks are integrated into one block. 7. The flatness measuring means obtains a variance value of pixel data of each block, judges that the variance is flat when the variance values are equal to or smaller than a predetermined value, and the first block dividing means sets the arbitrary block. 6. The image coding apparatus according to claim 5, wherein when is not flat, the block is divided into m (m: any positive integer) blocks. 8. A first storage unit that divides an image to be encoded into a plurality of blocks and holds the block, and a set of pixel values in an arbitrary area of the first storage unit is converted by a designated conversion method. A conversion unit, a comparison unit that compares the degree of approximation of the set of pixel values of the designated block in the first storage unit and the output of the conversion unit, and the degree of approximation is a predetermined value from the result of the comparison unit. Second block division means for re-dividing the block division of the first storage means when it is larger, and when the approximation degree is less than a predetermined value from the result of the comparison means, the area is coded as an area for the designated block. And a control unit that controls the first storage unit, the conversion unit, the comparison unit, the second block division unit, and the code determination unit, and the control unit is a result of the comparison unit. To the degree of approximation The image coding apparatus is characterized in that the block is subdivided step by step until is less than or equal to a predetermined value, and the code is determined by the code determining means. 9. The comparison means uses the sum of squares of errors, the sum of errors, the maximum value of the errors, the intermediate value, or the like as an evaluation criterion of the degree of approximation. 4,
The image coding device according to 5, 6, 7, or 8. 10. The code determining means outputs, as a code output, position information of a determined region and information about a conversion method, and / or position information of a corresponding block and / or an average value. 2, 3,
The image coding device according to 4, 5, 6, 7, 8 or 9. 11. A fourth storage means for dividing an image into a plurality of blocks and holding the same, a fifth storage means for holding a domain position and a conversion method for each block, and a fourth storage means in the fourth storage means. Second conversion means for converting the set of pixel values of the designated block by the corresponding conversion method and storing it in the fourth storage means, and convergence determination from the set of pixel values before and after the conversion of the block. An image decoding apparatus, comprising: convergence determining means for performing conversion; and the second converting means repeats conversion for each block until convergence is determined by the convergence determining means. 12. A fourth storage means for dividing an image into a plurality of blocks and holding the same, a fifth storage means for holding a domain position for each block, a conversion method and the number of iterations, and
Second conversion means for converting a set of pixel values of a designated block in the storage means according to the corresponding conversion method and storing the converted value in the fourth storage means. ..