JPH0567399A - Semiconductor memory device having burn-in mode confirmation means - Google Patents

Abstract

(57) [Summary] [Object] The present invention is a semiconductor memory having a burn-in mode confirmation means capable of outputting as electrically identifiable information that the internal power supply voltage has become equal to the external power supply voltage during burn-in. The main feature is to provide a device. By outputting the internal power supply voltage and the external power supply voltage from the NC pin 10 to the outside as electrical information by the P-type MOS transistors 11 and 12, there is a difference in electrical information between the stress mode and the stress mode. Determine whether or not there is.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having burn-in mode confirming means, and more particularly, to an internal power supply which can be made equal to an external power supply in a stress mode which is a special mode of a semiconductor memory device having an internal power supply generation circuit. Semiconductor memory device having various burn-in mode confirmation means.

[0002]

2. Description of the Related Art In a conventional semiconductor memory device, the level input from the outside is used as it is as an internal power source. However, due to the miniaturization of transistors accompanying the recent increase in capacity, its reliability and current consumption are reduced. Due to the increase in power consumption, the method of stepping down the internal power supply has been widely proposed.

Generally, in a semiconductor memory device,
Immediately after manufacture, chips are usually included in a certain ratio, which may be defective in a short period of time due to minute defects in manufacturing. Therefore, it is usual for manufacturers to perform continuous operation at high temperature / high voltage for several tens of hours to several days, and to screen chips including the above results by screening in advance. This high voltage continuous operation is called burn-in.

In a semiconductor memory device having a built-in power supply step-down circuit, even if the external power supply voltage is increased, the internal power supply voltage becomes constant and burn-in cannot be performed. Therefore, at the time of burn-in, there is a method of connecting an internal power supply line and an external power supply line with a transfer gate and applying an external power supply voltage to the inside, which is called a stress mode.

FIG. 11 is an electric circuit diagram of an internal power supply voltage down circuit in a conventional semiconductor memory device having a stress mode. Referring to FIG. 11, external power supply extVcc is applied to the drains of P-type MOS transistors 1 and 2, and internal power supply intVcc is applied to the respective sources. The internal power supply intVccc is applied to the level shifter circuit 3 to be leveled down, the leveled down voltage is applied to the differential amplifier circuit 4, and the reference voltage Vr is applied.
ef is compared. The output of the differential amplifier circuit 4 is a P-type MOS
The stress mode signal / SM is applied to the gate of the transistor 1 and the gate of the P-type MOS transistor 2.

Next, the operation of the internal power supply voltage down circuit shown in FIG. 11 will be described. The internal power supply intVcc is level down by the level shifter circuit 3, the voltage thereof is compared with the reference voltage Vref by the differential amplifier circuit 4, and when the level down voltage is lower than the reference voltage Vref, the output of the differential amplifier circuit 4 is It becomes the “L” level, the P-type MOS transistor 1 becomes conductive, and the external power supply extVcc
And the internal power supply intVcc are connected. Internal power supply int
When Vcc becomes higher and the level-lowered voltage becomes higher than the reference voltage Vref, the output of the differential amplifier circuit 4 becomes “H”, the P-type MOS transistor 1 becomes non-conductive, and the external power supply extVcc and the internal power supply intVcc. And are separated. In the stress mode, the burn-in mode signal / SM goes to "L" level, the P-type MOS transistor 2 becomes conductive, and the external power supply extVcc and the internal power supply intVcc are irrespective of whether the internal power supply intVcc is high or not. Are connected.

FIG. 12 is an electric circuit diagram showing another example of the conventional internal power supply step-down circuit having the burn-in mode. In the internal power supply step-down circuit shown in FIG. 12, an N-type MOS transistor 5 is connected in parallel to the P-type MOS transistor 2 shown in FIG.
A signal BIE that is activated at the time of burn-in is applied to the gate of the signal BIE.
It is also applied to the gate of the MOS transistor 2. In the differential amplifier circuit 4, the power supply voltage Vcc is divided by the resistors 7 and 8, the reference voltage Vref is applied to the reference input terminal as a reference input, and the internal power supply intVcc is applied to the comparison input terminal.

In the internal power supply voltage down circuit shown in FIG. 12, the N-type MOS transistor 5 is rendered conductive by the signal BIE activated in the burn-in mode, and the external power supply ex
tVcc and internal power supply intVcc are directly connected.

[0009]

As described above, FIG.
In the semiconductor memory device having the built-in power supply voltage down circuit shown in FIG. 12, the external power supply extVcc and the internal power supply in
Although P-type MOS transistors 1 and 2 are provided to connect to tVcc, it is not possible to determine from the outside of the chip whether or not the voltage has been switched for burn-in during actual burn-in or during testing. There was a problem.

Therefore, a main object of the present invention is to provide a semiconductor having a burn-in mode confirmation means capable of outputting as externally electrically confirmable information that the internal voltage and the external voltage are equal at the time of burn-in or test. A storage device is provided.

[0011]

SUMMARY OF THE INVENTION The present invention is a mode in which the internal power supply voltage and the external power supply voltage are made equal for a continuous operation test for internally stepping down the power supply voltage and selecting chips having defective defects. And a means for electrically confirming from the outside of the semiconductor memory device that the mode has become equal to the internal power supply voltage and the external power supply voltage.

[0012]

The semiconductor memory device having the burn-in mode confirming means according to the present invention outputs the fact that the internal power supply becomes equal to the external power supply when the burn-in mode is entered, so that the correct acceleration can be surely performed at the time of test or actual burn-in. It is possible to confirm whether or not the coefficient burn-in is performed.

[0013]

1 is an electric circuit diagram of an embodiment of the present invention. In FIG. 1, the drain of P-type MOS transistor 11 is connected to external power supply extVcc shown in FIG. 11, and the drain of P-type MOS transistor 12 is similarly connected to internal power supply intVcc shown in FIG. P
Sources of type MOS transistors 11 and 12 are NC pin 1
It is connected to 0 and grounded via a resistor 9.
The control signal A input to the gate of the P-type MOS transistor 11 and the control signal B input to the gate of the P-type MOS transistor 12 may be input externally or may be timing control signals such as address keys. Good.

2 and 3 are timing charts for explaining the operation of FIG. 1, particularly FIG. 2 shows an external power supply level monitor, and FIG. 3 shows an internal power supply monitor.

Next, the operation of the embodiment shown in FIG. 1 will be described. When not in the stress mode, as described in FIG. 11, the external power supply extVcc and the internal power supply int are used.
Not connected to Vcc. As shown in FIG. 2, when the control signal A falls to the “L” level, the P-type MOS transistor 11 becomes conductive and the NC pin 10 receives the external power supply ext.
Vcc is output as it is. On the contrary, as shown in FIG. 3, when the control signal B falls to the "L" level, the P-type MO
The S transistor 12 is turned on, and the internal power supply intVcc is output to the NC pin 10. That is, when the P-type MOS transistors 11 and 12 are turned on in the stress mode, the voltage output to the NC pin 10 is at the level of the external power supply extVcc and the internal power supply intVcc.
There is a difference between the two.

On the other hand, in the stress mode, as described in FIG. 11, the external power supply extVcc and the internal power supply intV are used.
Since cc is connected, there is no difference in the level of the voltage output to the NC pin 10 when the P-type MOS transistors 11 and 12 are turned on. That is, when the stress mode is not set, the voltage output to the NC pin 10 when the P-type MOS transistors 11 and 12 are turned on at the timings shown in FIGS. When the mode is set, the voltage output to the NC pin 10 is similarly measured at the timings of FIG. 2 and FIG. 3, and it is confirmed that there is no difference between them, so that the external power supply extVcc and the internal power supply intVcc are checked in the stress mode. You can see that

FIG. 4 is an electric circuit diagram of another embodiment of the present invention. Referring to FIG. 4, n-type MOS transistor 21
And 23 are connected in series, and the N-type MOS transistor 21
An external power supply extVcc is applied to the drain of, and the source of the N-type MOS transistor 23 is grounded. N type M
The connection point between the source of the OS transistor 21 and the drain of the N-type MOS transistor 23 is connected to the Dout pin 24. The drain of the N-type MOS transistor 22 is connected to the internal power supply intVcc, and the source is the Dout pin 24.
Connected to. The signal RD1 is applied to the gate of the N-type MOS transistor 21 and the N-type MOS transistor 22
A signal RD2 is applied to the gate of, and a signal / RD is applied to the gate of the N-type MOS transistor 23.

FIG. 5 shows the signals RD1 and RD shown in FIG.
It is an electric circuit diagram which generates 2. In FIG. 5, the read data RD is output to the transmission gate 24 as the signal RD1, and the transfer gate 25 outputs the read data RD as the signal RD2. The control signal C is a timing signal such as an address key and is given to one input gate of the transmission gate 24 and one input gate of the transmission gate 25, and further inverted by the inverter 26 to the other gate of the transmission gate 24. While being given, it is inverted by the inverter 27 and given to the other gate of the transmission gate 25.

6 and 7 are timing charts for explaining the operation of the embodiment shown in FIG. 4, particularly FIG. 6 is a timing chart for monitoring the external power supply level, and FIG. 7 is an internal chart. It is a timing diagram when monitoring a power supply level.

Next, the operation of FIGS. 4 and 5 will be described. In FIG. 5, when the control signal C becomes "H" level, the transmission gate 24 becomes conductive and the read data RD becomes the signal R.
It is output as D1. This signal RD1 is N shown in FIG.
Type MOS transistor 21 is made conductive, Dout
A voltage of extVcc-V is output to the pin 24. Here, the voltage V is a value determined by the size of the N-type MOS transistor 21 and the threshold value.

Similarly, when the control signal C becomes "L" level, the transmission gate 25 becomes conductive and the read data RD is output as the signal RD2. This signal RD2 turns on the N-type MOS transistor 22 shown in FIG.
A voltage of intVcc-V is output to the ut pin 24.

In FIG. 4, when the stress mode is not set, as shown in FIG.
Is at the "L" level, / WE is at the "H" level, the read data is output, and the voltage output to the Dout pin 24 is measured when the control signal C is at the "H" level. As shown in FIG. Dout when the control signal C is at "L" level
When the voltage output to the pin 24 is measured and the semiconductor memory devices having the difference are set in the stress mode,
The voltage output to the Dout pin 24 is measured at the timings of FIGS. 6 and 7. Then, by confirming that there is no difference, the external power supply ex
It can be confirmed that tVcc is equal to the internal power supply intVcc.

FIG. 8 is an electric circuit diagram showing still another embodiment of the present invention. The example shown in FIG. 8 is an example of an input first stage circuit of a semiconductor memory device, and is a P-type M
The drain of the OS transistor 31 has an external power supply extV
The internal power supply intVcc is applied to the drain of the P-type MOS transistor 32. P-type MOS
The control signal D is given to the gate of the transistor 31,
A control signal / D is applied to the gate of the P-type MOS transistor 32.
Is given. The control signals D and / D are timing control signals such as address keys. The sources of the P-type MOS transistors 31 and 32 are connected to the node N1.
The external terminal EXT is connected to the gate of the first-stage MOS transistor 33 and the gate of the N-type MOS transistor 34, and the drain of the P-type MOS transistor 33 is the node N.
1, the source is connected to the drain of the N-type MOS transistor 34, and the source of the N-type MOS transistor 34 is grounded.

Next, the operation will be described. Control signal D
Is at the "L" level and the control signal / D goes to the "H" level, the P-type MOS transistor 31 becomes conductive and the node N1 attains the voltage level of the external power supply extVcc. On the contrary, when the control signal D becomes "H" level and the control signal / D becomes "L" level, the P-type MOS transistor 32 becomes conductive and the node N1 becomes the voltage level of the internal power supply intVcc.

On the other hand, when the voltage at the EXT terminal is at the intermediate level, the P-type MOS transistor 33 and the N-type M
Both of the OS transistors 34 are conductive, and the higher voltage of the node N1 is the P-type MOS transistor 33 and the N-type MOS.
The node N2, which is the output of the transistor 34, tends to be at "H" level. That is, the node N1 is connected to the external power supply ex
tVcc voltage or internal power supply intVcc
The threshold voltage of the input first stage differs depending on whether or not That is, when not in the stress mode, the control signal D is at “L” level, the threshold voltage measured when the control signal / D is at “H” level, and the control signal D is at “H” level, When the semiconductor memory device having a difference with the threshold voltage measured when the control signal / D is at "L" level is set in the stress mode, the control signal D is similarly at "L" level, Threshold voltage measured when signal / D is at "H" level and control signal D is at "H"
It is a level, and it is confirmed that the external power supply extVcc and the internal power supply intVcc are equal in the stress mode by confirming that there is no difference between the threshold value measured when the control signal / D is “L” level. can do.

FIG. 9 is an electric circuit diagram showing still another embodiment of the present invention. In addition to the conventional internal power supply voltage generating circuit shown in FIG. 12, the embodiment shown in FIG.
Switch circuit 50, NAND gate 53, and inverter 5
Including 4 and. The switch circuit 50 includes a P-type MOS transistor 51 and an N-type MOS transistor 52, and their drains are connected to an external pin 55 such as an address pin, for example. A signal BIE is applied to one input end of the NAND gate 53, and a check signal CHECK is applied to the other input end. The output of the NAND gate 53 is given to the gate of the P-type MOS transistor 51, inverted by the inverter 54, and given to the gate of the N-type MOS transistor 52.

Next, the operation of the embodiment shown in FIG. 9 will be described. When the signal BIE is activated to "H" level in the burn-in mode, the internal power supply intVcc
Is switched by the switch circuit 9 and the external power source ext
Although at the same level as Vcc, the check signal CHECK set at a specific timing or the like causes the switch circuit 50 to operate, and the internal power supply intVcc is output to the external pin 55 via the switch circuit 50.

The above-mentioned specific timing is, for example, / CAS before / RA in a dynamic RAM.
The timing may be S or the like. Also,
The external pin 55 may be an unused empty pin or any specific address pin or clock pin. External pin 5
The level output to 5 may be determined by a tester or burn-in device to confirm that it is at the same level as the external power supply extVcc.

FIG. 10 is an electric circuit diagram of burn-in mode confirmation means according to another embodiment of the present invention. The embodiment shown in FIG. 10 utilizes a signal BIE activated when the burn-in mode is entered to leak a specific external pin 40. Therefore, N-type MOS transistors 41 to 44 are connected in series between the external pin 40 and the ground, and the signal BIE is applied to the gate of the N-type MOS transistor 44.
Is given. When the signal BIE is activated and becomes "H" level, the N-type MOS transistor 44 becomes conductive and a voltage equal to or higher than the sum of the threshold values of the N-type MOS transistors 41, 42 and 43 is applied to the external pin 40. This causes a leak current. Strictly speaking, the internal voltage level is not checked, but it can be checked that the signal BIE is normally output.

[0030]

As described above, according to the present invention, it is possible to confirm that the external power supply voltage is equal to the internal power supply voltage in the stress mode. You can know exactly what is going on.

[Brief description of drawings]

FIG. 1 is an electric circuit diagram of a stress mode confirmation means according to an embodiment of the present invention.

FIG. 2 is a diagram showing an external power supply voltage measurement timing in FIG.

FIG. 3 is a diagram showing an internal power supply voltage measurement timing in FIG.

FIG. 4 is a circuit diagram of stress mode confirmation means according to another embodiment of the present invention.

5 is an electric circuit diagram showing an input signal control circuit in FIG.

FIG. 6 is a diagram showing external power supply voltage measurement timing in FIG.

FIG. 7 is a diagram showing an internal power supply voltage measurement timing in FIG.

FIG. 8 is an electric circuit diagram of a stress mode confirmation means according to still another embodiment of the present invention.

FIG. 9 is an electric circuit diagram showing an example of an internal power supply voltage down circuit according to another embodiment of the present invention.

FIG. 10 is an electric circuit diagram of burn-in mode confirmation means showing still another embodiment of the present invention.

FIG. 11 is an electric circuit diagram showing an example of a conventional internal power supply voltage step-down circuit.

FIG. 12 is an electric circuit diagram showing an example of a conventional internal power supply voltage down circuit having a burn-in mode.

[Explanation of symbols]

1, 2, 11, 12, 31, 32, 33 P-type MOS transistor 4 Differential amplifier circuit 5, 21, 22, 23, 34, 52 N-type MOS transistor 6, 26, 27, 54 Inverter 53 NAND gate

Claims (1)

[Claims] 1. A semiconductor memory device having a mode in which an internal power supply voltage is made equal to an external power supply voltage for a continuous operation test for internally lowering a power supply voltage and selecting a chip having a defect therein, A means for electrically confirming that the mode has been entered from outside the semiconductor memory device,
Semiconductor memory device having burn-in mode confirmation means.