JPH0580120A - Integrated circuit inspecting method - Google Patents

Abstract

(57) [Summary] [Purpose] To shorten the inspection input sequence length. [Structure] In step 103, a well-known test input is generated in a normal mode according to the original operation of the circuit for the selected failure. In step 105, a logic simulation is performed using the generated test input, and the result is stored in a file. Generate a test input sequence for the sequential circuit while filling in. next,
In step 201, the storage element to be scanned is determined, and in steps 202 to 204, the inspection input (scan pattern) in the scan mode is generated. In step 205, the inspection input in the scan mode generated in step 204 is inserted into the inspection input sequence in the normal mode. In step 206, the state before entering the scan mode is checked from the simulation result of step 105, and the state is checked. Inserted last as scan mode scan input.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit inspection method.

[0002]

2. Description of the Related Art As the scale of integrated circuits increases, the inspection thereof becomes an increasingly difficult problem. As a method for facilitating the inspection, there is a scan path technology that enables the setting and reading of the state from the outside by switching the storage element to the shift register configuration during the inspection. According to this method
Since all the memory elements are replaced with scan memory elements, scan-in / scan-out and combinational circuit portion inspection can be performed, so that the inspection can be greatly simplified.

However, if all the storage elements are scan registers, a large load is imposed in terms of the amount of additional circuits.
There is a partial scan configuration in which a part of the memory element is a scan memory element. See the 1988 International Test Conference document [Hi-KeungTony Ma, Shrinivas Deva for more on partial scan design techniques.
das, A. Richard Newton, and Alberto Sangiovanni-Vi
ncentelli, "An Incomplete Scan Design for Sequenti
al Machines, "Proc. Int. Test Conf., pp.730-734, 1
988.] and references therein.

A conventional method of inspecting an integrated circuit using partial scan will be described below with reference to the drawings. FIG. 5 is a flowchart showing a conventional method for testing an integrated circuit. First, in step 601, inspection input generation for a sequential circuit is performed. In step 602, the cause of the low fault coverage is investigated, in step 603, the problematic storage element is converted into a scan-in structure, and in step 604, the fault aborted when the first test input is generated (step 601) is rescanned. Generate test input using.

The conventional method of testing an integrated circuit will be described in detail with reference to the circuit configuration diagram shown in FIG. In FIG. 2, 301 to 304 are external inputs, 305 are scan inputs, 306 to 309 are external outputs, 310 is scan output, 320 is a combinational circuit portion, 331 to 333 are storage elements that scan, and 334 to 336 do not scan. The element α is a failure in the combinational circuit portion 320.

FIG. 6 is a diagram showing a process of generating a test input for detecting the failure α in the circuit of FIG. In FIG. 6, V _{1 to} V _n are given to external inputs 301 to 304 n
Shows individual test inputs. The inspection inputs V _{1 to} V _n are
(Value of external input 301, value of external input 302, value of external input 303, value of external input 304). After the inspection inputs V _{1 to} V _n of the sequential circuit are applied to the external inputs 301 to 304 to detect a fault other than the fault α, a condition for detecting the fault α is created. Here, the condition for detecting the failure α is (value of external input 301, value of external input 302, value of external input 303, value of external input 304) =
(1,0,1,0) and [(scan storage element 331
, The state value of the scan storage element 332, the state value of the scan storage element 333) (the state value of the storage element 334,
State value of storage element 335, state value of storage element 336)]
= [(1,1,0) (1,0,1)].

First, in order to make the state values of the storage elements 334 to 336 the same as the detection condition ( ₁ , 0, ₁₎ , inspection inputs V ₁ , V ₂ and V ₃ are sequentially applied to the external inputs 301 to 304. Next, switch to scan mode,
When (1, 0, 1, 0) is given to 304 and 0 → 1 → 1 is sequentially given as the scan input 305 to perform scan-in, the influence of the failure α reaches the scan storage element 332.

Subsequently, (0, 0, 1, 1) is applied to the external inputs 301 to 304, and the scan input 3
If 0 → 0 → 0 (theoretical value is an arbitrary value) is sequentially given as 05 and scan out is performed, the influence of the failure α is detected as the scan output 310. In FIG. 6, S
(0) and S (1) indicate values given as the scan input 305.

[0009]

However, in the above-described conventional method for inspecting an integrated circuit, it is not possible to return to the circuit state before scan-in after scan-in is performed and then scan-out. Therefore, the inspection is completed in the normal mode. You have to do the scan mode later, and when you do the scan mode, you use many scans to recreate the state of the storage element when the scan request occurs during the normal mode test. The inspection input sequence length becomes long because the inspection input is spent.

Further, as a method of returning the state of the storage element to be scanned to the state before the scan-out at the time of performing the scan-out, the scan-out terminal and the scan-in terminal are connected on the hardware so that the scan-out is completed. Sometimes there was a way to restore the state of the scan storage element. However, in this method, the state of the scan storage element can be returned to the state before the scan out when only the scan out is performed, but when the scan out is performed subsequent to the scan in, the scan storage element Since the state could not be returned to the state before scan-in, the same problem as described above will occur.

An object of the present invention is to provide an integrated circuit inspection method capable of reducing the inspection input sequence length.

[0012]

SUMMARY OF THE INVENTION In a method of testing an integrated circuit according to the present invention, a first test input sequence of an integrated circuit without scanning is first generated, and then it is difficult to generate a test input without scanning. A third test input in which a second test input of the integrated circuit in which some or all of the storage elements are replaced by a scan configuration is generated, and the second test input is inserted into the first test input sequence. Generate a series. Furthermore, the state of the memory element to be scanned immediately before entering the scan mode when switching from the normal mode in which the first test input sequence is applied to the external input of the integrated circuit to the scan mode in which the second test input is applied to the scan input is simulated. Generating a fourth inspection input for returning the storage element to be scanned when switching from the scan mode to the normal mode to the state immediately before entering the scan mode, which is obtained by simulation, and outputting the fourth inspection input to the third inspection input series. Second in
The fifth test input sequence inserted after the test input of is generated. Then, the fifth test input sequence is applied to an integrated circuit in which some or all of the memory elements are replaced with a scan configuration.

[0013]

According to the structure of the present invention, immediately before entering the scan mode when switching from the normal mode in which the first test input sequence is applied to the external input of the integrated circuit to the scan mode in which the second test input is applied to the scan input. A fourth test input is generated that simulates the state of the storage element to be scanned and returns the storage element to be scanned when the scan mode is switched from the scan mode to the normal mode to the state immediately before entering the scan mode. Since the test input is inserted next to the second test input in the third test input sequence to generate the fifth test input sequence, the circuit state can be efficiently used, and the fifth test input sequence can be efficiently used. The inspection input sequence length can be shortened.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An integrated circuit inspection method according to the present invention will be described with reference to the drawings. FIG. 1A is a flow chart showing a method of inspecting an integrated circuit according to an embodiment of the present invention. First,
In step 101, it is checked whether or not there is an unprocessed failure in the circuit under test, and if there is an unprocessed failure, step 102 is executed.
If not, go to step 108.

At step 102, one unprocessed fault is selected. Next, in step 103, a known test input (first test input) in the normal mode is generated according to the original operation of the circuit for the selected failure. Next step 10
4, the inspection input generation in step 103 is CPU time, 1
It is checked whether or not the test input sequence length required for detecting one fault has exceeded the limit such as the number of backtracks or the number of backtracks. If not, the process proceeds to step 105, where a logic simulation is performed with the generated test input. After writing the result in the file, step 101
Proceed to and process the next failure.

If the inspection input generation in step 103 has been aborted, the process proceeds to step 106 to check whether the aborted fault can be detected by scanning the memory element. Step 101
Proceed to and process the next failure. If it can be detected by scanning, the process proceeds to step 107, and after writing information such as which storage element should be scanned in the aborted fault file, the process proceeds to step 101 to process the next fault.

If there is no unprocessed fault in step 101, the process proceeds to step 108, and it is checked in step 108 whether the detection rate is sufficient. If the detection rate is sufficient, the normal mode generated up to that time is generated. Only the inspection input in (1) is determined as the inspection input, and the inspection input generation ends. If the detection rate is insufficient, the process proceeds to step 109, the storage element to be scanned is determined from the information of the aborted failure file, the scan mode test input is inserted into the normal mode test input sequence, and then the test input generation is performed. finish.

The process of step 109 will be described in more detail with reference to FIG. Figure 1 (b) is Step 1 of Figure 1 (a)
It is a flowchart which shows the method of inserting the inspection input of the 09 scan mode in the inspection input series of the normal mode.
First, in step 201, a storage element to be scanned is determined from a fault that can be detected by scanning in the aborted fault file. Next, in step 202, it is checked whether or not there is a failure in the aborted failure file, and if there is no failure, the inspection input generation ends. If there is a failure in the abort failure file, the process proceeds to step 203, and one failure that can be detected by scanning is extracted from the abort failure file.

Next, the process proceeds to step 204 and step 20
An inspection input (second inspection input) in the scan mode for the failure selected in 3 is generated. If the test input generation fails here, the process proceeds to step 202 to process the next failure. If the inspection input generation is successful, the process proceeds to step 205,
The test input in the scan mode generated in step 204 is inserted into the test input sequence in the normal mode, and step 20
Go to 6.

Next, in step 206, step 105
The state before entering the scan mode is checked from the simulation result of 1., and the state is inserted as the scan mode inspection input (fourth inspection input) at the end, and then step 20
Proceed to 2 to process the next failure. Next, the method of inspecting this integrated circuit will be specifically described.

FIG. 2 is a circuit configuration diagram for specifically explaining the inspection method of this integrated circuit. In FIG. 2, 30
1 to 304 are external input, 305 is scan input, 306
˜309 is an external output, 310 is a scan output, 320 is a combinational circuit part, 331 to 333 are storage elements to be scanned, 334 to 336 are storage elements not to be scanned, and α is a failure in the combinational circuit part 320.

FIG. 3 shows that a failure α is detected in the circuit of FIG.
Shown test conditions and generated test inputs without scanning
It is a figure. In FIG. 3, V₀, M₀Are each broken
External inputs 301 to 30 required to detect α
4 shows the theoretical value of 4 and the state values of the storage elements 331 to 336,
V₁~ V_nIs an external input 3 generated without scanning
N inspection inputs given to 01 to 304, M₁~ M_nHaso
Inspection input V₁~ V_nTo external inputs 301-304
When given to the logic simulation (step 105)
The state values of the storage elements 331 to 336 thus obtained are shown.
You Note that the external input value V₀, V₁~ V_nIs (external
Value of force 301, value of external input 302, value of external input 30
3, the value of the external input 304), the state of the storage element
Value M₀, M ₁~ M_nIs [(state of scan storage element 331
State value, state value of scan storage element 332, scan storage
State value of element 333) (state value of storage element 334, storage
Element 335 state value, storage element 336 state value)]
Is made.

Failure α is due to the pre-processing of step 101.
And the value of external input 301-304 is V ₀(1, 0, 1,
0) and the state values of the storage elements 331 to 336 are
M₀When [(1,1,0) (1,0,1)],
It can be seen that the influence of the failure α reaches the memory element 332.
It Now, in step 104, the inspection input generation is terminated.
Suppose For faults in circuits
When the process (step 104) is completed, n inspection inputs
V₁~ V_nIs generated. Also, a logical simulation
By step 105, the inspection input V₁When you enter
The state values of the memory elements 331 to 336 are M₁[(0,0,
0) (0,0,0)], inspection input V₂Enter to memorize
The state values of the elements 331 to 336 are M₂[(1,1,0)
(1,0,0)], inspection input V₃Enter the memory element
The status value of 331 to 336 is M₃[(0,1,1) (1,
0, 1)], inspection input V_FourIs input, the memory element 331
~ 336 status value is M_Four[(0,1,0) (1,1,
0)].

The values of the external inputs 301-304 and the status values of the scan storage elements 331-333 can be freely set to the required values, but the status values of the storage elements 334-336 should be set to the required values. Have difficulty. Therefore, the inspection inputs V _{1 to} V _n of the sequential circuit are transferred to the external inputs 301 to 304.
Focusing on the state values of the storage elements 334 to 336 in the process of being given to, the state values of the storage elements 334 to 336 when the inspection input V ₃ is input to the external inputs 301 to 304 are (1,
0, 1), which coincides with the state values of the storage elements 334 to 336 required for detecting the failure α.

Therefore, as shown in FIG. 4, after inputting the inspection inputs V _{1 to} V ₃ , the mode is switched to the scan mode, ( ₁ , 0, ₁ , 0) is given to the external inputs 301 to 304, and at the same time, as the scan input 305. When scan-in is performed by sequentially applying 0 → 1 → 1, the state value of the storage elements 331 to 336 is sM ₁ [(0,0,1) (1,0,1)] → sM
₂ [(1,0,0) (1,0,1)] → sM ₃ [(1,
1, 0) (1, 0, 1)]. At this time,
The condition for detecting the failure α is satisfied, and the influence of the failure α reaches the scan storage element 332.

Subsequently, (0, 0, 1, 1) is applied to the external inputs 301 to 304, and the inspection input V
_The circuit state M ₃ [(0,1,1) (1,0,1)] obtained by logically simulating ₃ (0,0,1,1) is scanned in. That is, when scan-out is performed by sequentially applying 1 → 1 → 0 as the scan input 305, the state values of the storage elements 331 to 336 are sM ₄ [(1,1,
1) (1,0,1)] → sM ₅ [(1,1,1) (1,
0,1)] → sM ₆ [(0,1,1) (1,0,1)]
, The value of the external inputs 301 to 304 and the state values of the storage elements 331 to 336 are the values V ₃ and M ₃ (before the scan mode is entered). = SM ₆ ). The scan mode is ended here, and the external inputs 301 to 3
Other faults are detected by applying the test inputs V _{4 to} V _n to 04. In FIG. 4, S (0), S
(1) indicates a value given as the scan input 305.

As described above, according to this embodiment, since the circuit state in the process of giving the test inputs V _{1 to} V _n of the sequential circuit to the external inputs 301 to 304 is obtained from the logic simulation, this circuit state is scanned. It is possible to return to the circuit state immediately before entering the scan mode by turning on, and to insert the scan mode inspection input in the middle of the inspection inputs V _{1 to} V _n (normal mode inspection input series) of the sequential circuit. You can

As described above, since the scan mode inspection input can be freely inserted into the normal mode inspection input sequence,
The inspection inputs V _{1 to} V _n of the sequential circuit are external inputs 301 to 30
4, the storage elements 334 to 33 which are difficult to set in the circuit state M ₀ required to detect the failure α.
The test input sequence length can be shortened by effectively using the state value of 6. Further, the more the number of failures such as the failure α that can be detected by inserting the scan in the middle of the test input of the sequential circuit, the greater the effect of the present invention.

[0029]

According to the first aspect of the present invention, there is provided an integrated circuit inspection method.
Of the storage element to be scanned immediately before entering the scan mode when the scan mode in which the second test input is supplied to the scan input is switched to the scan mode from the normal mode in which the test input sequence is supplied to the external input of the integrated circuit. A fourth test input is generated that returns the storage element to be scanned when switching to the normal mode to the state immediately before entering the scan mode obtained by simulation, and the fourth test input is generated as a second test input in the third test input sequence.
Since the fifth check input sequence is generated by inserting the check input next to, the circuit state can be efficiently used and the fifth check input sequence length can be shortened.

[Brief description of drawings]

FIG. 1 is a flowchart showing an integrated circuit inspection method according to an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram used in the same embodiment and a conventional example.

FIG. 3 is a diagram for explaining a process of generating a test input according to the integrated circuit test method of the embodiment.

FIG. 4 is a diagram for explaining a process of generating a test input according to the integrated circuit test method of the embodiment.

FIG. 5 is a flowchart showing a conventional integrated circuit inspection method.

FIG. 6 is a diagram illustrating a process of generating a test input according to a conventional integrated circuit test method.

[Explanation of symbols]

103 Step of Generating Test Input Sequence in Normal Mode 105 Step of Writing Simulation Results in File 201 Step of Determining Storage Element to Scan 205 Scan Pattern Insertion Step 206 Inspection Input Insertion for Returning Storage Element to State Just Before Entering Scan Mode Step

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[Procedure amendment]

[Submission date] September 18, 1992

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

[Correction content]

[Figure 1]

[Fig. 2]

[Figure 3]

[Figure 4]

[Figure 5]

[Figure 6]

Claims (1)

[Claims] 1. A method of testing an integrated circuit, wherein some or all of the memory elements in the integrated circuit are replaced with a scan configuration, wherein a first test input sequence of the integrated circuit without scanning is first generated, and thereafter. For a fault in which it is difficult to generate a test input without scanning, a second test input of an integrated circuit in which some or all of the storage elements are replaced with a scan configuration is generated, and the second test input is used as the first test input. A third test input sequence inserted in the test input sequence is generated, and a normal mode in which the first test input sequence is given to the external input of the integrated circuit is switched to a scan mode in which the second test input is given to the scan input. The state of the storage element to be scanned immediately before entering the scan mode is simulated, and the storage element to be scanned when switching from the scan mode to the normal mode is selected. A fourth inspection input that returns to the state immediately before entering the scan mode obtained by the simulation is generated, and the fourth inspection input is inserted next to the second inspection input in the third inspection input series. A method for inspecting an integrated circuit, which comprises generating a fifth inspection input sequence and applying the fifth inspection input sequence to an integrated circuit in which some or all of the storage elements are replaced with a scan configuration.