JPH0582516A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0582516A JPH0582516A JP3272096A JP27209691A JPH0582516A JP H0582516 A JPH0582516 A JP H0582516A JP 3272096 A JP3272096 A JP 3272096A JP 27209691 A JP27209691 A JP 27209691A JP H0582516 A JPH0582516 A JP H0582516A
- Authority
- JP
- Japan
- Prior art keywords
- film
- element isolation
- region
- sio
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 239000010408 film Substances 0.000 claims abstract description 137
- 238000002955 isolation Methods 0.000 claims abstract description 37
- 239000010409 thin film Substances 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 abstract description 15
- 241000293849 Cordylanthus Species 0.000 abstract description 8
- 238000005457 optimization Methods 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 12
- 229910052681 coesite Inorganic materials 0.000 abstract 6
- 229910052906 cristobalite Inorganic materials 0.000 abstract 6
- 239000000377 silicon dioxide Substances 0.000 abstract 6
- 235000012239 silicon dioxide Nutrition 0.000 abstract 6
- 229910052682 stishovite Inorganic materials 0.000 abstract 6
- 229910052905 tridymite Inorganic materials 0.000 abstract 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 15
- 238000004519 manufacturing process Methods 0.000 description 14
- 230000003647 oxidation Effects 0.000 description 13
- 238000007254 oxidation reaction Methods 0.000 description 13
- 238000009792 diffusion process Methods 0.000 description 6
- 238000004380 ashing Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000003963 antioxidant agent Substances 0.000 description 2
- 230000003078 antioxidant effect Effects 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本願の発明は、酸化膜、特に選択
酸化法で形成された酸化膜で素子分離が行われている半
導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which element isolation is performed by an oxide film, particularly an oxide film formed by a selective oxidation method.
【０００２】[0002]
【従来の技術】半導体装置における素子分離技術の一つ
に誘電体分離があり、誘電体分離のうちで最もよく用い
られている方式として選択酸化（ＬＯＣＯＳ）法があ
る。この様な選択酸化法で素子分離が行われている従来
の半導体装置では、半導体装置の何れの領域において
も、同一の条件で形成された素子分離用の酸化膜が用い
られていた。2. Description of the Related Art Dielectric isolation is one of the element isolation techniques in a semiconductor device, and the most widely used dielectric isolation method is the selective oxidation (LOCOS) method. In the conventional semiconductor device in which element isolation is performed by such a selective oxidation method, an oxide film for element isolation formed under the same conditions is used in any region of the semiconductor device.
【０００３】ところで、選択酸化法では酸化膜にバーズ
ビークが発生し、酸化膜を厚くするに連れて、素子分離
能力は高くなるが、バーズビークの長さの２倍の値であ
る変換差が大きくなる。逆に、酸化膜を薄くするに連れ
て、変換差は小さくなるが、素子分離能力が低くなる。By the way, in the selective oxidation method, bird's beaks are generated in the oxide film, and as the oxide film becomes thicker, the element isolation capability increases, but the conversion difference, which is a value twice the length of the bird's beak, increases. .. On the contrary, as the oxide film becomes thinner, the conversion difference becomes smaller, but the element isolation ability becomes lower.
【０００４】そして、デザインルールの厳しい領域で
は、酸化膜上の配線と半導体基板との間の容量や寄生Ｍ
ＯＳトランジスタの閾値電圧や狭チャネル効果等の各種
のデバイス特性に与える変換差の影響が大きい。このた
め、素子分離能力の低下をある程度犠牲にして、酸化膜
を薄くしなければならない。In the region where the design rule is strict, the capacitance or parasitic M between the wiring on the oxide film and the semiconductor substrate.
The influence of the conversion difference on various device characteristics such as the threshold voltage of the OS transistor and the narrow channel effect is large. Therefore, the oxide film must be thinned at the sacrifice of the decrease in the element isolation capability.
【０００５】一方、デザインルールの緩い領域では、変
換差が多少大きくても、上述のデバイス特性に対してそ
れ程には影響がない。このため、酸化膜を厚くして、素
子分離能力を高めることができる。On the other hand, in the region where the design rule is loose, even if the conversion difference is somewhat large, the above device characteristics are not so affected. Therefore, the oxide film can be thickened to enhance the element isolation capability.
【０００６】[0006]
【発明が解決しようとする課題】ところが、既述の様
に、従来の半導体装置では、半導体装置の何れの領域に
おいても、同一の条件で形成された素子分離用の酸化膜
が用いられていた。このため、デザインルールの厳しい
領域における条件で酸化膜を形成するとデザインルール
の緩い領域における酸化膜の素子分離能力が犠牲にな
り、逆に、デザインルールの緩い領域における条件で酸
化膜を形成するとデザインルールの厳しい領域における
デバイス特性が犠牲になっていた。つまり、従来の半導
体装置では、デバイス特性の最適化と素子分離能力の向
上とを両立させることができなかった。However, as described above, in the conventional semiconductor device, the oxide film for element isolation formed under the same condition is used in any region of the semiconductor device. .. Therefore, if an oxide film is formed under conditions where the design rule is strict, the element isolation ability of the oxide film in the region where the design rule is loose is sacrificed, and conversely, if the oxide film is formed under conditions where the design rule is loose The device characteristics in the strict rule area were sacrificed. That is, in the conventional semiconductor device, optimization of the device characteristics and improvement of the element isolation capability cannot both be achieved.
【０００７】[0007]
【課題を解決するための手段】請求項１の半導体装置で
は、膜厚ｔ1 が相対的に薄い素子分離用の第１の酸化膜
１４と、膜厚ｔ2 が相対的に厚い素子分離用の第２の酸
化膜１５とが半導体基板１１に設けられている。According to another aspect of the semiconductor device of the present invention, a first oxide film 14 for element isolation having a relatively thin film thickness t 1 and an element isolation film having a relatively thick film thickness t 2 are provided. Second oxide film 15 is provided on the semiconductor substrate 11.
【０００８】請求項２の半導体装置では、半導体基板１
１の表面よりも下方の部分の膜厚ｙ1 が相対的に薄い素
子分離用の第１の酸化膜３３と、前記下方の部分の膜厚
ｙ2 が相対的に厚い素子分離用の第２の酸化膜３４とが
前記半導体基板１１に設けられている。In the semiconductor device of claim 2, the semiconductor substrate 1
The first oxide film 33 for element isolation in which the film thickness y 1 in the portion below the surface of 1 is relatively thin, and the second oxide film 33 in the element isolation for which the film thickness y 2 in the lower portion is relatively thick. Oxide film 34 is provided on the semiconductor substrate 11.
【０００９】[0009]
【作用】請求項１の半導体装置では、素子分離用の第１
及び第２の酸化膜１４、１５を選択酸化法で形成した場
合、バーズビークは第２の酸化膜１５よりも第１の酸化
膜１４の方が短い。一方、素子分離能力は第１の酸化膜
１４よりも第２の酸化膜１５の方が高い。According to the semiconductor device of the present invention, the first device isolation element is used.
When the second oxide films 14 and 15 are formed by the selective oxidation method, the bird's beak of the first oxide film 14 is shorter than that of the second oxide film 15. On the other hand, the element isolation ability of the second oxide film 15 is higher than that of the first oxide film 14.
【００１０】請求項２の半導体装置では、素子分離用の
第１及び第２の酸化膜３３、３４を選択酸化法で形成し
た場合、各々の全体的な膜厚が互いに等しくても、バー
ズビークは第２の酸化膜３４よりも第１の酸化膜３３の
方が短い。一方、素子分離能力は第１の酸化膜３３より
も第２の酸化膜３４の方が高い。According to another aspect of the semiconductor device of the present invention, when the first and second oxide films 33 and 34 for element isolation are formed by the selective oxidation method, bird's beaks are generated even if their respective total film thicknesses are equal to each other. The first oxide film 33 is shorter than the second oxide film 34. On the other hand, the element isolation ability of the second oxide film 34 is higher than that of the first oxide film 33.
【００１１】[0011]
【実施例】以下、本願の発明の第１及び第２実施例を、
図１〜１８を参照しながら説明する。The first and second embodiments of the present invention will be described below.
This will be described with reference to FIGS.
【００１２】図１が第１実施例を示しており、図２〜８
がその製造工程を示している。この第１実施例では、図
１に示す様に、Ｓｉ基板１１のうちで半導体メモリにお
けるメモリセル領域等の様にデザインルールの厳しい領
域１２と周辺回路領域等の様にデザインルールの緩い領
域１３とでは、選択酸化法で形成された素子分離用のＳ
ｉＯ2 膜１４、１５の膜厚ｔ1 、ｔ2 が互いに相違して
いる。即ち、ＳｉＯ2 膜１４の膜厚ｔ1 は３００ｎｍ程
度と相対的に薄く、ＳｉＯ2 膜１５の膜厚ｔ2 は４００
ｎｍ程度と相対的に厚い。FIG. 1 shows a first embodiment, and FIGS.
Shows the manufacturing process. In the first embodiment, as shown in FIG. 1, a region 12 of a Si substrate 11 having a strict design rule such as a memory cell region in a semiconductor memory and a region 13 having a loose design rule such as a peripheral circuit region. And, S for element isolation formed by the selective oxidation method
The thicknesses t 1 and t 2 of the iO 2 films 14 and 15 are different from each other. That is, the film thickness t 1 of the SiO 2 film 14 is relatively thin, about 300 nm, and the film thickness t 2 of the SiO 2 film 15 is 400 nm.
It is relatively thick at about nm.
【００１３】この様な第１実施例を製造するためには、
図２に示す様に、Ｓｉ基板１１をまず拡散炉で酸化し
て、その表面に膜厚が１００Å程度のＳｉＯ2膜１６を
形成する。そして、膜厚が５００〜１０００Å程度の多
結晶Ｓｉ膜１７をＣＶＤ法でＳｉＯ2 膜１６上に形成
し、更に、膜厚が１０００〜２０００Å程度のＳｉＮ膜
２１をＣＶＤ法で多結晶Ｓｉ膜１７上に形成する。In order to manufacture such a first embodiment,
As shown in FIG. 2, the Si substrate 11 is first oxidized in a diffusion furnace to form a SiO 2 film 16 having a film thickness of about 100 Å on its surface. Then, a polycrystalline Si film 17 having a film thickness of about 500 to 1000Å is formed on the SiO 2 film 16 by a CVD method, and a SiN film 21 having a film thickness of about 1000 to 2000Å is formed on the SiO 2 film 16 by a CVD method. Form on top.
【００１４】次に、レジスト２２（図３）をＳｉＮ膜２
１上の全面に塗布し、図３に示す様に、領域１３の素子
分離領域のパターンにレジスト２２をパターニングす
る。そして、レジスト２２をマスクにしたＲＩＥ等によ
って、図４に示す様に、ＳｉＮ膜２１と多結晶Ｓｉ膜１
７の一部とを除去して、開口２３を形成する。その後、
レジスト２２をアッシング等で除去する。Next, the resist 22 (FIG. 3) is formed on the SiN film 2.
1 is applied to the entire surface, and as shown in FIG. 3, a resist 22 is patterned in the pattern of the element isolation region in the region 13. Then, as shown in FIG. 4, the SiN film 21 and the polycrystalline Si film 1 are formed by RIE using the resist 22 as a mask.
A part of 7 is removed to form the opening 23. afterwards,
The resist 22 is removed by ashing or the like.
【００１５】次に、拡散炉で酸化を行って、図５に示す
様に、２００ｎｍ程度の膜厚ｔ3 のＳｉＯ2 膜１５を開
口２３に対応して形成する。この時、領域１２は酸化防
止膜であるＳｉＮ膜２１で覆っているので、領域１２に
はまだＳｉＯ2 膜１４が形成されない。Next, oxidation is performed in a diffusion furnace to form a SiO 2 film 15 having a film thickness t 3 of about 200 nm corresponding to the opening 23, as shown in FIG. At this time, since the region 12 is covered with the SiN film 21 which is an antioxidant film, the SiO 2 film 14 is not yet formed in the region 12.
【００１６】次に、再びレジスト２４（図６）を全面に
塗布し、図６に示す様に、今度は領域１２の素子分離領
域のパターンにレジスト２４をパターニングする。そし
て、レジスト２４をマスクにしたＲＩＥ等によって、図
７に示す様に、ＳｉＮ膜２１と多結晶Ｓｉ膜１７の一部
とを除去して、開口２５を形成する。その後、レジスト
２４をアッシング等で除去する。Next, a resist 24 (FIG. 6) is applied again to the entire surface, and as shown in FIG. 6, this time, the resist 24 is patterned into the pattern of the element isolation region of the region 12. Then, as shown in FIG. 7, the SiN film 21 and part of the polycrystalline Si film 17 are removed by RIE or the like using the resist 24 as a mask to form an opening 25. After that, the resist 24 is removed by ashing or the like.
【００１７】次に、拡散炉で酸化を行って、図８に示す
様に、３００ｎｍ程度の膜厚ｔ1 のＳｉＯ2 膜１４を開
口２５に対応して形成する。この時、既に形成されてい
るＳｉＯ2 膜１５も４００ｎｍ程度の膜厚ｔ2 になる。
その後、ＳｉＮ膜２１、多結晶Ｓｉ膜１７及びＳｉＯ2
膜１６をウェットエッチングまたはドライエッチングで
除去して、図１に示した第１実施例を得る。Next, oxidation is performed in a diffusion furnace to form a SiO 2 film 14 having a film thickness t 1 of about 300 nm corresponding to the opening 25, as shown in FIG. At this time, the already formed SiO 2 film 15 also has a film thickness t 2 of about 400 nm.
Then, the SiN film 21, the polycrystalline Si film 17, and the SiO 2
The film 16 is removed by wet etching or dry etching to obtain the first embodiment shown in FIG.
【００１８】図９〜１２は、第１実施例の別の製造工程
を示している。この製造工程は、上述の図８の工程で、
既に形成されているＳｉＯ2 膜１５の膜厚がｔ3 からｔ
2 へ増加するのが適切でない場合のためのものである。9 to 12 show another manufacturing process of the first embodiment. This manufacturing process is the process shown in FIG.
The thickness of the SiO 2 film 15 already formed is from t 3 to t
In case it is not appropriate to increase to 2 .
【００１９】この製造工程でも、図２〜５までは上述の
製造工程と略同様の工程を実行するが、図５の製造工程
では、ＳｉＯ2 膜１５の膜厚を２００ｎｍ程度であるｔ
3 ではなく、当初から４００ｎｍ程度であるｔ2 にして
おく。その後、図９に示す様に、ＳｉＮ膜２１及び多結
晶Ｓｉ膜１７をウェットエッチングまたはドライエッチ
ングで除去する。In this manufacturing process as well, steps similar to those described above are carried out up to FIGS. 2 to 5, but in the manufacturing process of FIG. 5, the thickness of the SiO 2 film 15 is about 200 nm.
Instead of 3 , set to t 2 which is about 400 nm from the beginning. Then, as shown in FIG. 9, the SiN film 21 and the polycrystalline Si film 17 are removed by wet etching or dry etching.
【００２０】次に、図１０に示す様に、再び多結晶Ｓｉ
膜２６とＳｉＮ膜２７とをＣＶＤ法で順次に全面に形成
し、図１１に示す様に、レジスト２４と同様のパターン
のレジスト３１をＳｉＮ膜２７上に形成する。Next, as shown in FIG. 10, polycrystalline Si is again used.
A film 26 and a SiN film 27 are sequentially formed on the entire surface by a CVD method, and a resist 31 having the same pattern as the resist 24 is formed on the SiN film 27 as shown in FIG.
【００２１】次に、レジスト３１をマスクにしたＲＩＥ
等によって、図１２に示す様に、ＳｉＮ膜２７と多結晶
Ｓｉ膜１６の一部とを除去して、開口３２を形成する。
その後、レジスト３１をアッシング等で除去する。Next, RIE using the resist 31 as a mask
As shown in FIG. 12, the SiN film 27 and a part of the polycrystalline Si film 16 are removed by the above method to form an opening 32.
After that, the resist 31 is removed by ashing or the like.
【００２２】次に、拡散炉で酸化を行って、図１に示し
た様に、３００ｎｍ程度の膜厚ｔ1 のＳｉＯ2 膜１４を
開口３２に対応して形成する。この時、既に形成されて
いるＳｉＯ2 膜１５は酸化防止膜であるＳｉＮ膜２７で
覆っているので、このＳｉＯ2 膜１４の膜厚は４００ｎ
ｍ程度であるｔ2 のままである。その後、ＳｉＮ膜２
７、多結晶Ｓｉ膜２６及びＳｉＯ2 膜１６をウェットエ
ッチングまたはドライエッチングで除去して、図１に示
した第１実施例を得る。Next, oxidation is performed in a diffusion furnace to form a SiO 2 film 14 having a film thickness t 1 of about 300 nm corresponding to the opening 32, as shown in FIG. At this time, since the already formed SiO 2 film 15 is covered with the SiN film 27 which is an antioxidant film, the thickness of the SiO 2 film 14 is 400 n.
It remains t 2 which is about m. After that, the SiN film 2
7. The polycrystalline Si film 26 and the SiO 2 film 16 are removed by wet etching or dry etching to obtain the first embodiment shown in FIG.
【００２３】なお、第１実施例を製造するための上述の
何れの工程においても、ＳｉＯ2 膜１４、１５のバーズ
ビークを短くするために、ＳｉＯ2 膜１６よりも酸素の
拡散係数が小さい多結晶Ｓｉ膜１７、２６をＳｉＯ2 膜
１６とＳｉＮ膜２１、２７との間に用いているが、多結
晶Ｓｉ膜１７、２６は必ずしも必要ではない。In any of the steps described above for manufacturing the first embodiment, in order to shorten the bird's beak of the SiO 2 films 14 and 15, the polycrystalline film having a smaller oxygen diffusion coefficient than the SiO 2 film 16 is used. Although the Si films 17 and 26 are used between the SiO 2 film 16 and the SiN films 21 and 27, the polycrystalline Si films 17 and 26 are not always necessary.
【００２４】図１３は第２実施例を示しており、図１４
〜１８がその製造工程を示している。この第２実施例で
は、図１３に示す様に、デザインルールの厳しい領域１
２とデザインルールの緩い領域１３とでは、選択酸化法
で形成された素子分離用のＳｉＯ2 膜３３、３４の各々
の全体的な膜厚は互いに等しいが、ＳｉＯ2 膜３３のう
ちでＳｉ基板１１の表面よりも下方の部分の膜厚ｙ1 が
ＳｉＯ2 膜３４のうちでＳｉ基板１１の表面よりも下方
の部分の膜厚ｙ2 に比べて薄い。FIG. 13 shows the second embodiment, and FIG.
-18 shows the manufacturing process. In the second embodiment, as shown in FIG.
In the 2 and design rule loose region 13, but the overall thickness of each of SiO 2 films 33 and 34 for device isolation formed by selective oxidation method are equal to each other, Si substrate of SiO 2 film 33 The film thickness y 1 of the portion below the surface of 11 is thinner than the film thickness y 2 of the portion of the SiO 2 film 34 below the surface of the Si substrate 11.
【００２５】この様な第２実施例を製造するためには、
図１４に示す様に、図２の工程と同様にして、ＳｉＮ膜
２１までをＳｉ基板１１上に形成する。そして、レジス
ト３５（図１５）をＳｉＮ膜２１上の全面に塗布し、図
１５に示す様に、領域１２の素子分離領域のパターンに
レジスト３５をパターニングする。In order to manufacture such a second embodiment,
As shown in FIG. 14, up to the SiN film 21 is formed on the Si substrate 11 in the same manner as the process of FIG. Then, a resist 35 (FIG. 15) is applied on the entire surface of the SiN film 21, and the resist 35 is patterned in the pattern of the element isolation region of the region 12 as shown in FIG.
【００２６】次に、レジスト３５をマスクにしたＲＩＥ
等によって、図１６に示す様に、ＳｉＮ膜２１と多結晶
Ｓｉ膜１７の一部とを除去して、開口３６を形成する。
この時の多結晶Ｓｉ膜１７のうちで開口３６下の残りの
部分の膜厚をｔ4 とする。その後、レジスト３５をアッ
シング等で除去する。Next, RIE using the resist 35 as a mask
As shown in FIG. 16, the SiN film 21 and a part of the polycrystalline Si film 17 are removed to form an opening 36.
At this time, the film thickness of the remaining portion of the polycrystalline Si film 17 below the opening 36 is t 4 . After that, the resist 35 is removed by ashing or the like.
【００２７】次に、再びレジスト３７（図１７）を全面
に塗布し、図１７に示す様に、今度は領域１３の素子分
離領域のパターンにレジスト３７をパターニングする。
そして、レジスト３７をマスクにしたＲＩＥ等によっ
て、図１８に示す様に、ＳｉＮ膜２１と多結晶Ｓｉ膜１
７の一部とを除去して、開口３８を形成する。この時の
多結晶Ｓｉ膜１７のうちで開口３８下の残りの部分の膜
厚をｔ5とすると、膜厚ｔ5 は膜厚ｔ4 よりも薄くす
る。その後、レジスト２４をアッシング等で除去する。Next, a resist 37 (FIG. 17) is applied again on the entire surface, and as shown in FIG. 17, this time, the resist 37 is patterned into the pattern of the element isolation region of the region 13.
Then, as shown in FIG. 18, the SiN film 21 and the polycrystalline Si film 1 are formed by RIE using the resist 37 as a mask.
A part of 7 is removed to form an opening 38. If the film thickness of the remaining portion of the polycrystalline Si film 17 below the opening 38 is t 5 at this time, the film thickness t 5 is made smaller than the film thickness t 4 . After that, the resist 24 is removed by ashing or the like.
【００２８】次に、拡散炉で酸化を行い、開口３６、３
８に対応して、図１３に示したＳｉＯ2 膜３３、３４を
形成する。この時、多結晶Ｓｉ膜１７のうちで開口３
６、３８下の残りの部分の膜厚ｔ4 、ｔ5 が互いに相違
しているので、ＳｉＯ2 膜３３、３４のうちでＳｉ基板
１１が酸化されて形成された部分の膜厚ｙ1 、ｙ2 が互
いに相違し、その結果、ＳｉＯ2 膜３３、３４の変換差
も相違する。Next, oxidation is performed in a diffusion furnace to form openings 36, 3
Corresponding to No. 8, the SiO 2 films 33 and 34 shown in FIG. 13 are formed. At this time, the opening 3 in the polycrystalline Si film 17
Since the thicknesses t 4 and t 5 of the remaining portions under 6 and 38 are different from each other, the thickness y 1 of the portion of the SiO 2 films 33 and 34 formed by oxidizing the Si substrate 11, y 2 is different from each other, and as a result, the conversion difference between the SiO 2 films 33 and 34 is also different.
【００２９】その後、ＳｉＮ膜２１、多結晶Ｓｉ膜１７
及びＳｉＯ2 膜１６をウェットエッチングまたはドライ
エッチングで除去して、図１３に示した第２実施例を得
る。以上の様な第２実施例のための製造工程を、第１実
施例のための既述の製造工程と比較すると、選択酸化が
１回でよいので、その分だけ工程が少ない。After that, the SiN film 21 and the polycrystalline Si film 17 are formed.
The SiO 2 film 16 is removed by wet etching or dry etching to obtain the second embodiment shown in FIG. Comparing the above-described manufacturing process for the second embodiment with the manufacturing process described above for the first embodiment, since the selective oxidation only needs to be performed once, the number of processes is reduced accordingly.
【００３０】[0030]
【発明の効果】本願の発明による半導体装置では、バー
ズビークは第２の酸化膜よりも第１の酸化膜の方が短
く、素子分離能力は第１の酸化膜よりも第２の酸化膜の
方が高いので、デザインルールの厳しい領域に第１の酸
化膜を用い、デザインルールの緩い領域に第２の酸化膜
を用いることによって、デバイス特性の最適化と素子分
離能力の向上とを両立させることができる。In the semiconductor device according to the invention of the present application, the bird's beak is shorter in the first oxide film than in the second oxide film, and the element isolation capability is higher in the second oxide film than in the first oxide film. Therefore, by using the first oxide film in the region where the design rule is strict and by using the second oxide film in the region where the design rule is loose, it is possible to achieve both optimization of device characteristics and improvement of element isolation capability. You can
【図１】本願の発明の第１実施例の側断面図である。FIG. 1 is a side sectional view of a first embodiment of the present invention.
【図２】第１実施例を製造するための最初の工程を示す
側断面図である。FIG. 2 is a side sectional view showing a first step for manufacturing the first embodiment.
【図３】図２に続く工程を示す側断面図である。FIG. 3 is a side sectional view showing a step that follows FIG.
【図４】図３に続く工程を示す側断面図である。FIG. 4 is a side sectional view showing a step that follows FIG.
【図５】図４に続く工程を示す側断面図である。5 is a side sectional view showing a step that follows FIG.
【図６】図５に続く工程を示す側断面図である。6 is a side sectional view showing a step that follows FIG.
【図７】図６に続く工程を示す側断面図である。7 is a side sectional view showing a step that follows FIG.
【図８】図７に続く工程を示す側断面図である。8 is a side sectional view showing a step that follows FIG. 7. FIG.
【図９】第１実施例を別の方法で製造するための最初の
工程を示す側断面図である。FIG. 9 is a side sectional view showing a first step for manufacturing the first example by another method.
【図１０】図９に続く工程を示す側断面図である。FIG. 10 is a side sectional view showing a step that follows FIG.
【図１１】図１０に続く工程を示す側断面図である。FIG. 11 is a side sectional view showing a step that follows FIG.
【図１２】図１１に続く工程を示す側断面図である。12 is a side sectional view showing a step that follows FIG. 11. FIG.
【図１３】第２実施例の側断面図である。FIG. 13 is a side sectional view of the second embodiment.
【図１４】第２実施例を製造するための最初の工程を示
す側断面図である。FIG. 14 is a side sectional view showing a first step for manufacturing the second embodiment.
【図１５】図１４に続く工程を示す側断面図である。FIG. 15 is a side sectional view showing a step that follows FIG.
【図１６】図１５に続く工程を示す側断面図である。16 is a side sectional view showing a step that follows FIG.
【図１７】図１６に続く工程を示す側断面図である。FIG. 17 is a side sectional view showing a step that follows FIG.
【図１８】図１７に続く工程を示す側断面図である。FIG. 18 is a sectional side view showing a step that follows FIG.
１１ Ｓｉ基板 １４ ＳｉＯ2 膜 １５ ＳｉＯ2 膜 ３３ ＳｉＯ2 膜 ３４ ＳｉＯ2 膜11 Si substrate 14 SiO 2 film 15 SiO 2 film 33 SiO 2 film 34 SiO 2 film
Claims (2)
化膜と、 膜厚が相対的に厚い素子分離用の第２の酸化膜とが半導
体基板に設けられている半導体装置。1. A semiconductor device in which a semiconductor substrate is provided with a first oxide film for element isolation having a relatively thin film thickness and a second oxide film for element isolation having a relatively thick film thickness. ..
が相対的に薄い素子分離用の第１の酸化膜と、 前記下方の部分の膜厚が相対的に厚い素子分離用の第２
の酸化膜とが前記半導体基板に設けられている半導体装
置。2. An element isolation first oxide film having a relatively thin film thickness in a portion below a surface of a semiconductor substrate, and an element isolation first oxide film having a relatively thick film thickness in a lower portion. Two
A semiconductor device in which the oxide film of 1 is provided on the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3272096A JPH0582516A (en) | 1991-09-24 | 1991-09-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3272096A JPH0582516A (en) | 1991-09-24 | 1991-09-24 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0582516A true JPH0582516A (en) | 1993-04-02 |
Family
ID=17509025
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3272096A Pending JPH0582516A (en) | 1991-09-24 | 1991-09-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0582516A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998008252A1 (en) * | 1996-08-22 | 1998-02-26 | Advanced Micro Devices, Inc. | Method for differential fieldox growth |
-
1991
- 1991-09-24 JP JP3272096A patent/JPH0582516A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998008252A1 (en) * | 1996-08-22 | 1998-02-26 | Advanced Micro Devices, Inc. | Method for differential fieldox growth |
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