JPH0583305A - Msk modulation circuit - Google Patents

Abstract

PURPOSE:To simplify the circuit and to reduce the scale by using a sample data generator so as to digitize I channel and Q channel data and using digital signal processing. CONSTITUTION:Sample data generators 1, 2 generate sampling data resulting from quantizing sinusoidal waves of I channel and Q channel data signals. Then a signal I1 outputted in m-bits is multiplied digitally with an I clock whose frequency is Fs/4 for all the entire m-bits and the product is D/A- converted by a D/A converter 7, and outputted through a low pass filter(LPF) 9. The other output signal Q1 similarly passes through a digital multiplier 6, a D/A converter 8 and an LPF 10 and the result is outputted as an analog quantity. Moreover, an output signal I3 of the LPF 9 is multiplied with a carrier (CAR) at a multiplier 11 and an output signal Q3 of the LPF 10 is multiplied with a multiplier 12 with a signal resulting from delaying the CAR by 90 deg. and each output signal is synthesized by a synthesizer 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an MSK modulator circuit,
In particular, it relates to an MSK modulation circuit used in a digital satellite communication system.

[0002]

2. Description of the Related Art Generally, a four-phase PSK modulation system is widely used as a modulation / demodulation system in satellite communication.
It is well known that the MSK modulation method exhibits superior characteristics in the nonlinear region. First, the MSK modulation method will be described with reference to FIGS.
Now, assuming that the bit rate is Fs, the baseband signal I
The baud rate of ch and Qch is Fs / 2. In FIG. 5, the respective baseband signals are I1 and Q1.
And The clock CLK represents a clock having a frequency of Fs / 2, and the carrier wave CAR has a frequency of F0. Here, this is considered as a cosine wave. In FIG. 4, the clock of frequency Fs / 2 is divided by 2 in the frequency divider 203 to obtain the frequency Fs / 2.
The clock becomes / 4 and the harmonics are removed by the LPF 204 (this is considered as a cosine wave). This output is IC
Set LK to 90 ° shifter 205 to set IchCLK phase to 9
QCLK delayed by 0 degrees is considered as a sine wave. FIG. 5 shows ICLK and QCLK. Returning to FIG. 4, the input baseband signal I1 is multiplied by ICLK in the multiplier 201, and the output is taken as I2. Similarly, the baseband signal Q1 is QC in the multiplier 202.
It is multiplied by LK and its output is designated as Q2 (I2 in FIG. 5).
See Q2). Further, I2 is multiplied by the carrier wave CAR in the multiplier 206 and becomes the output I3. Q2 is a multiplier 20
At 7, the 90-degree shifter 208 multiplies the CAR with the phase delayed by 90 degrees to obtain the output Q3. I3 and Q3 are combined in the combiner 209, and the output becomes an MSK modulated wave. In this MSK modulated wave signal, the angular frequency of the carrier wave signal and the angular frequency of the Ich and Qch clocks are respectively ω
If 0 = 2πF0 and ωs = 2πFs, then it is expressed by equation (1).

I1 cos ωs / 4 · (cos ω0t) + Q1 sin ωs / 4 · (sin ω0t) (1) The conventional MSK modulation circuit has a configuration similar to that of FIG. 4, but normally the MSK modulation circuit of FIG. It is realized by. Here, Ich, Qch, clock CLK, carrier frequency F
0 and the clock frequency Fs are the same as those described above. In FIG. 4, the clock CLK is divided by 2 in the frequency divider 404.
The frequency-divided ICLK from which harmonics have been removed by the LPF 405 and the input carrier CAR are multiplied by the multiplier 401.
And the output is ICAR. CAR is 90
CAR whose phase is delayed by 90 degrees in the degree shifter 403,
QCL with ICLK delayed 90 degrees by 90 degree shifter 406
The multiplier 402 multiplies K and the output is QCAR. The signal I1 input to Ich is multiplied by ICAR in the multiplier 407, and its output is set to I2. The signal Q1 input to Qch is multiplied by QCAR in the multiplier 408, and its output is designated as Q2. I2 and Q2 are synthesizer 4
09, and the MSK modulated wave is output (1)
The same MSK modulated signal as in the equation is obtained.

[0004]

DISCLOSURE OF THE INVENTION The conventional MSK described above
The modulation circuit outputs the result of multiplying the carrier wave and the clock by Ic
Since the h and Qch data pass through the LPF and are multiplied by the sine-wave analog signal, there is a drawback that the circuit is difficult and the circuit scale becomes large.

[0005]

In the MSK modulation circuit of the present invention, the amplitudes of the I-channel and Q-channel sine wave data signals with a baud rate of frequency Fs / 2 and a phase shift of 1/2 bit are respectively determined by a predetermined number of samples. Sample data generators for I and Q channels that are sampled at and converted to digital signals, and a clock of frequency Fs / 2 is set to 1
A frequency divider that divides the frequency by 2 and the output clock of this frequency divider by 2
A first digital multiplier that digitally multiplies one of the branched clocks with the output digital signal of the I-channel sample data generator, and the other clock obtained by bifurcating the output clock of the frequency divider by 90 degrees, A second digital multiplier for digitally multiplying the output digital signal of the Q channel sample data generator is included.

[0006]

The present invention will be described below with reference to the drawings. 1 is a block diagram of an embodiment of the present invention, FIG.
(A), (b) and FIG. 3 are explanatory diagrams of a signal format and waveforms of respective parts in this embodiment.

Here, the Ich and Qch data signals have a baud rate of Fs / 2 and a phase of 1/1 as shown in FIG.
It is a two-series digital signal input with a shift of 2 bits. The clock CLK represents a clock having a frequency Fs / 2, and the carrier CAR represents a carrier cos2πF0t having a frequency F0. In FIG. 1, in the sample data generators 1 and 2, each Ich and Qch data signal is shown in FIG.
A sine wave having a frequency Fs / 4 such as is sampled as follows. If the digital value of the input signal is "1",
Since the analog value corresponds to the portion A in FIG. 2B, the amplitudes corresponding to the respective sampling points when A is sampled n at equal intervals (n ≧ 4) are D1, D2 ... Dn,
The respective amplitudes are quantized into m-bit digital values and sequentially output from D1 to Dn during 2Ts. Further, when the digital value of the input signal is “0”, the analog value corresponds to the portion B in FIG. 2B, and therefore the amplitudes corresponding to the respective sampling points when B is sampled n at equal intervals. D1A, D2A ... DnA, and quantize the respective amplitudes into m-bit digital values to obtain 2Ts.
During this period, D1A to DnA are sequentially output. The output signals from the sample data generators 1 and 2 at this time are respectively I
1 and Q1. The I1 output in m bits is the digital multiplier 5 and each m bit is an IC of frequency Fs / 4.
It is digitally multiplied by LK. The m-bit output signal is digital / analog converted in the D / A CONV 7, passes through the LPF 9 and is output as an analog value. Here, the input signal of the LPF 9 is I2 and the output signal is I3. Similarly, Q1 is also multiplied by QCLK in the digital multiplier 6, digital-to-analog converted by D / ACONV 8, passes through the LPF 10, and is output as an analog value. Here, the input and output signals of the LPF 10 are designated as Q2 and Q3, respectively. However, ICLK is obtained by dividing the clock by the frequency divider 3, and QCLK is obtained by further delaying the phase of ICLK by 90 degrees by a 90 degree shifter. Signals I, Q, ICLK, QCLK, I2, Q2
The relationship between I3 and Q3 is shown in FIG. However, the number of samples of I2 and Q2 is an example of n = 6. I3 is multiplied by CAR in the multiplier 11, Q3 is multiplied by CAR that is 90 degrees out of phase with the multiplier 12, and the multipliers 11, 12
The output signals of 1 are combined in the combiner 14, and the MSK modulated wave is output.

[0008]

As described above, according to the present invention, the Ich and Qch data are digitized by the sample data generator and processed by the digital signal, so that they can be realized by a simple circuit and the circuit scale can be made relatively small. It has the effect of being able to.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is an explanatory diagram of signal formats and waveforms according to the present embodiment.

FIG. 3 is an explanatory diagram of waveforms at various points in this embodiment.

FIG. 4 is a block diagram of a conventional MSK modulation method.

FIG. 5 is a conventional waveform explanatory diagram.

FIG. 6 is a block diagram of a conventional MSK modulation circuit.

[Explanation of symbols]

 1, 2 Sample data generator 3 Frequency divider 4, 13 90 degree shifter 5, 6 Digital multiplier 7, 8 D / A converter 9, 10 Low pass filter (LPF) 11, 12 Multiplier 14 Combiner

Claims (2)

[Claims] 1. A baud rate of frequency Fs / 2 and a phase of 1
Sample data generators for I and Q channels that sample the amplitudes of the I and Q sine wave data signals that are shifted by / 2 bits by a predetermined number of samples, respectively, and a clock of frequency Fs / 2 And a first digital multiplier for digitally multiplying the output digital signal of the I-channel sample data generator by one of the two branched clocks of the output clock of the frequency divider. A second digital multiplier for digitally multiplying the output digital signal of the Q-channel sample data generator by digitally multiplying the other clock obtained by branching the output clock of the divider by 90 degrees. MSK modulation circuit. 2. The I-channel or Q-channel sine wave data signal of frequency Fs / 4 input to the sample data generator is divided into two 2Ts (Ts = 1 / Fs) time periods, and this time period 2. The M according to claim 1, wherein sampling data is stored for each positive amplitude or negative amplitude of the sine wave data signal and digitized during this period.
SK modulation circuit.