JPH0590260A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable a contact hole upper end chamfering process to be carried out through a simple isotropic wet etching operation, where the wet etching operation is accurately controlled in etching volume. CONSTITUTION:Insulating films 2, 3, and 4 of over two types different in etching rate to isotopic wet etching are used as interlayer insulating films of silicon oxide. The insulating film 4 serving as the uppermost layer is set faster than the lower films 3 and 4 in etching rate, and the upper insulating film 4 is selectively etched to remove the corners of a contact hole 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a contact hole.

[0002]

2. Description of the Related Art When a wiring is formed in a semiconductor device, the wiring must be connected to a wiring or an element formed thereunder via an insulating layer. In order to make such a connection, it is a general method to make a hole (contact hole) in the insulating layer and coat a wiring material on the hole to make a contact with a wiring or an element.

In recent years, semiconductor devices have been remarkably miniaturized, and both the device itself and the wiring have been miniaturized, and the contact hole diameter has been reduced. However, the thickness of the element or wiring does not change greatly, and the depth (aspect ratio) of the contact hole tends to increase with respect to its diameter. For this reason, the step coverage at the time of depositing the wiring material becomes a problem.

Further, it has been conventionally known that the angular burrs at the upper end of the hole generated when the contact hole is formed by anisotropic etching deteriorates the step coverage and reduces the reliability of the contact. Therefore, a so-called chamfering process is required to improve the step coverage. In this chamfering process, isotropic etching using wet etching is often used, but it is difficult to control the etching amount and there is a problem in processing accuracy.

On the other hand, at present, CDE (Chemical)
Isotropic etching by dry etcher) or plasma downflow dry etcher is also used in this process, but fluorine radicals as an etchant react with the resist as a mask material to deteriorate the dry etching resistance of the resist. Therefore, it has been reported that there is a problem that the conversion difference becomes large (for example, X. C. Muand Multiani, J. et al.
Electroche. Soc. , 137,2853
(Detailed in (1990)).

[0006]

SUMMARY OF THE INVENTION According to the present invention, the chamfering process of the upper end portion of a contact hole, which has been difficult to control accurately in the past, is performed by using wet etching which is a simple isotropic etching. The purpose is to precisely control the quantity.

[0007]

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device, wherein a contact hole is selectively formed in an interlayer insulating film made of a silicon oxide film provided on a semiconductor substrate. As the interlayer insulating film, two or more kinds of insulating films having different etching rates for isotropic wet etching are used, and the insulating film laminated on the uppermost layer is a film having a higher speed than the etching rate of the lower layer film, It is characterized in that the upper corner of the contact hole is removed by selectively etching the insulating film.

[0008]

The silicon oxide film used as the interlayer film has different etching rates depending on the film forming method and the impurity concentration. Therefore, by selecting the interlayer insulating film, the chamfered amount at the upper end of the contact hole is determined by the film thickness of the interlayer film formed immediately before, so that the controllability of etching is improved. In addition, since wet etching has high selectivity with respect to the resist, the conversion difference of the contact hole size can be reduced.

[0009]

EXAMPLE A silicon oxide film used as an interlayer insulating film has different etching rates depending on its film forming method and impurity concentration. For example, when buffered hydrofluoric acid which is an etchant for wet etching is used for etching, the etching rate is as shown in Table 1. Therefore, in the present invention, by combining these silicon oxide films and selectively etching only the film having a high etching rate, the chamfering amount in the depth direction is controlled with the same accuracy as the uniformity of the deposited film thickness. is there.

[0010]

[Table 1] The P concentration of the BPSG film was 3.5 W% and the B concentration was 4.8 w%.

Next, an embodiment of the present invention will be described with reference to FIG. FIG. 1 shows a sectional view of an embodiment of the present invention.

In this embodiment, a case where the chamfering amount at the upper end of the contact hole is controlled to 2000Å will be described.

First, HTO (High Temperature O) is formed on the silicon substrate 1 by the LPCVD method.
xide) The oxide film 2 is formed.

On top of that, B is formed by the plasma CVD method.
The PSG oxide film 3 is formed. After forming the BPSG oxide film 3, it is flattened by flow, etch back, etc.
TEOS (Tetraethylor) by PCVD method
An oxide film 4 of thosolicate) is deposited to 2000 Å.

After that, a resist 5 is applied and a contact hole is patterned by a photolithography process.

The etching rates of these films by buffered hydrofluoric acid are as shown in Table 1. In this embodiment, the TEOS oxide film 4 having a high etching rate can be selectively etched.

Therefore, the chamfering amount is not affected by a subtle difference such as the concentration or temperature of the solution during etching,
The uniformity of the film thickness of the TEOS oxide film 4 can be controlled with accuracy.

After this, RIE (Reactive Io)
The contact hole 6 is opened by anisotropic etching using an n etching method or the like.

FIG. 2 shows an embodiment in which flattening is performed when there are contact holes between the multi-layered wirings, and the interlayer insulating film of the present invention is provided on the multi-layered wirings 7a and 7b. is there. That is, the HTO oxide film 2 is formed on the silicon substrate 1 by LPCVD so as to surround the first-layer wiring 7a.

B is formed on the oxide film 2 by the plasma CVD method.
The PSG oxide film 3 is formed. After the BPSG oxide film 3 is formed, it is flattened by flow, etch back, or the like. Then, after the wiring 7b of the second layer is provided on the BPSG oxide film 3, the oxide film 4 of TEOS is deposited again by LPCVD so as to surround the wiring 7b of the second layer.

After that, a BPSG oxide film 3 is formed by a plasma CVD method, and the BPSG oxide film 3 is flattened by a flow, an etch back or the like. Then, the TEOS oxide film 4 is deposited again on the BPSG oxide film 3 and the TEOS oxide film 4 by the LPCVD method.

After that, a resist 5 is applied and a contact hole is patterned by a photolithography process.

As described above, the amount of chamfering is not affected by subtle differences such as the concentration and temperature of the solution at the time of etching, and the accuracy of the uniformity of the film thickness of the uppermost TEOS oxide film 4 is obtained. Control is possible.

Thereafter, the contact hole 6 is opened by anisotropic etching using the RIE method or the like.

[0025]

As described above, according to the present invention,
It is possible to accurately control the amount of chamfering at the upper end of the contact hole, which was difficult to control conventionally.

Further, since the interlayer film is deposited again after the flattening step, the process margin for the breakdown voltage between the wirings is widened.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention.

FIG. 2 is a sectional view showing an embodiment in which the present invention is used between multi-layer wirings.

[Explanation of symbols]

 1 Silicon substrate 2 HTO film 3 BPSG film 5 Resist 6 Contact hole 7 Wiring

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device, wherein a contact hole is selectively formed in an interlayer insulating film made of a silicon oxide film provided on a semiconductor substrate, wherein the interlayer insulating film comprises:
Two or more types of insulating films with different etching rates for isotropic wet etching are used, and the insulating film to be stacked on the uppermost layer consists of a film having a higher speed than the etching rate of the lower film, and the upper insulating film is selectively A method for manufacturing a semiconductor device, characterized in that the upper corners of the contact holes are removed by etching.