JPH06120456A - Defect relief method and defect relief system - Google Patents

Abstract

(57) [Summary] [Objective] A semiconductor integrated circuit chip region having a pattern defect included in a master slice type wafer is made available so as to improve a chip yield. [Structure] When information D1 of a pattern defect of each semiconductor integrated circuit chip area included in a wafer is acquired in advance and a desired semiconductor integrated circuit is obtained using the wafer, according to data D3 of a required product type and number. , Which type is to be assigned to which semiconductor integrated circuit chip area of which wafer. At this time, the inspection result data D1 is used to assign a pattern defective basic cell to a product that does not use the pattern defective basic cell for the semiconductor integrated circuit chip region having the pattern defect.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a defect relieving method for improving a chip yield, which is a ratio of the number of non-defective chips to the maximum number of chips that can be taken from one wafer, and a system therefor, for example, a master slice method. The present invention relates to an effective technique for a gate array type semiconductor integrated circuit adopting.

[0002]

2. Description of the Related Art A master slice method in a gate array type semiconductor integrated circuit is a wafer in which basic cells corresponding to logic gates such as NAND gates and NOR gates are formed in a chip area in advance, and wiring of the basic cells is performed. This is a method of obtaining a semiconductor integrated circuit having a desired logic by adding steps later. In such a system, such a wafer can be inspected for pattern defects in advance and then the wafer can be stocked. The result of the pattern inspection at this time can be exclusively used for the determination of the manufacturing lot having many pattern defects. An example of a document describing the master slice method is "LSI Handbook", page 204, issued by Ohm Co., Ltd. on November 30, 1984.

[0003]

However, when the result of the pattern inspection is used only for the determination of the manufacturing lot having many pattern defects and is not reflected in the subsequent wiring process,
With respect to the wafers that have become the master stock, all the wafers are treated as having no difference in yield and the wiring is started. The present inventor has found out the inconvenience caused by this. That is, at present, it is a few-bit missing defect in the memory-LSI and a function defect in the logic LSI that hinders the yield improvement by the probe inspection performed after the wiring process. It is presumed that the majority are caused by pattern defects in the wafer process, and it is necessary to reflect the information of pattern defects in the subsequent process to eliminate waste. Furthermore, when configuring a logic LSI in the master slice format, the number of circuit cells used and their positions differ depending on the type determined by the wiring. Relationship with
It was revealed that the varieties produced a significant difference in the chip yield. Moreover, in the case of the logic LSI, it is practically difficult to repair the defect by the redundant configuration like the memory LSI, so that the yield is remarkably reduced. In any case, it has not been considered to efficiently use the semiconductor integrated circuit chip region having such a pattern defect to improve the chip yield.

An object of the present invention is to make available a semiconductor integrated circuit chip area having a pattern defect at a wafer stage before a wiring process for determining a function so as to improve a chip yield. In other words, it is an object of the present invention to provide a defect relief method and a system therefor capable of improving the chip yield.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, for a wafer having a plurality of semiconductor integrated circuit chip regions in which a desired function is realized by forming a plurality of basic circuits in advance and determining wiring between the basic circuits, A pattern defect in each included semiconductor integrated circuit chip area is inspected, and inspection result data including identification information of the wafer and identification information of a defective basic circuit having a pattern defect is acquired. Then, for the wiring process for the wafer, based on the inspection result data, for the semiconductor integrated circuit chip area where the pattern defect exists, between the basic circuits of the semiconductor integrated circuit of the type that does not use the cell where the pattern defect exists Assign a wiring pattern. This is based on the fact that the types and arrangements of transistors and gates used in semiconductor integrated circuits of different types are different from each other. In this specification, the basic circuit is understood to mean any of a transistor, a gate such as a NAND gate, and a cell having a larger circuit scale than that.

At this time, in order to maximize the chip yield, as a process of allocating the wiring patterns between the basic circuits, data relating to the type and the number of required semiconductor integrated circuits, and the semiconductor integrated circuits of the required type. To obtain the wiring pattern data between the basic circuits to obtain
Comparing the inspection result data and the wiring pattern data,
It is advisable to adopt a data process that determines the wiring pattern data of each semiconductor integrated circuit chip area on the wafer by satisfying the required types and number with the minimum number of wafers. This method is optimal for obtaining a large number of semiconductor integrated circuits in small quantities.

In the above method, when it is assumed that the patterns to be adopted for the respective wafers are different from each other, in order to streamline the wiring pattern forming process, each semiconductor integrated circuit in the wafer is to be processed efficiently. Electron beam drawing data may be generated based on the wiring pattern data of the chip area, and the wiring pattern between the basic circuits may be drawn by the electron beam based on the electron beam drawing data.

[0010]

According to the above means, when the information of the pattern defect of each semiconductor integrated circuit chip area contained in the wafer is acquired in advance and the desired semiconductor integrated circuit is obtained by using the wafer, the required product type and the number Which product is to be assigned to which semiconductor integrated circuit chip area of which wafer. At this time, using the inspection result data, the method of allocating the semiconductor integrated circuit chip area in which the pattern defect exists to the product that does not use the pattern defective basic circuit is the semiconductor integrated circuit chip in which the pattern defect exists. It acts to reduce the waste of the area or the deterioration of the area, thereby improving the chip yield.

In the case of obtaining a large number of semiconductor integrated circuits in a small amount, the necessary types and the respective numbers are taken into consideration, and the required types and the number are satisfied with a minimum number of wafers, and each semiconductor integrated circuit on the wafer is satisfied. The process of allocating the wiring pattern data of the chip area minimizes the situation where the semiconductor integrated circuit chip area where the pattern defect exists is functionally defective as much as possible, and maximizes the chip yield. When such a method is adopted, the electron beam drawing is adopted for forming the wiring pattern between the basic circuits even when the patterns adopted for the respective wafers are different from each other. This streamlines the wiring pattern forming process.

[0012]

FIG. 1 shows a defect relief method according to an embodiment of the present invention. A system for realizing the method shown in the figure comprises a pattern defect inspection apparatus 1, a workstation 2 as data processing means, and an electron beam drawing apparatus 3.

First, the wafer to which the method of this embodiment is applied will be described. This wafer is used as a master stock for obtaining a gate array type semiconductor integrated circuit adopting the master slice method, and is designated by 4 in FIG. The wafer 4 is made of single crystal silicon and has a plurality of semiconductor integrated circuit chip regions CHP1 to CHP4.
5CHP25 is formed. The semiconductor integrated circuit chip regions CHP1 to CHP25 are made identical to each other, a plurality of basic cells are formed in advance, and the wiring between the basic cells is determined to be a semiconductor integrated circuit having a desired logic. It should be an area. The basic cell is an example of a basic circuit.

FIG. 3 representatively shows details of one semiconductor integrated circuit chip region CHP1. In this example, as shown in FIG. 1A, the basic cells 10 are arranged in a plurality of columns, and a wiring region 11 is provided between the columns. A large number of I / O cells 12 for configuring an input / output circuit are arranged in the peripheral portion. The I / O cell 12 can configure a desired circuit such as an input buffer, an output buffer, or an input / output buffer according to a wiring formed later. It should be understood that the I / O cell 12 shown in the figure includes electrode pads such as bonding pads. FIG. 3B shows an example of the basic cell 10 in the CMOS gate array. In the figure, what is shown by p is a p-channel type MOS transistor, and what is shown by n is an n-channel type MOS transistor. In this example, the basic cell itself does not have a logical function, but a basic cell partially having a logical function can be adopted, for example. The basic cell 10 realizes a logical function by arranging one or more desired cells. For example, one basic cell 1 is shown in FIG.
An example is shown where 0 is used to form a two-input NAND gate. A and B are input, X is output, VDD is power supply voltage,
VSS is the ground voltage. Wiring for realizing such a logical function is formed on the wiring region 11 and the column of the basic cells 10.

The wafer 4 as the master stock shown in FIG. 2 is in a state in which the wiring for completely determining the logic of the basic cell 10 and the I / O cell 12 is not yet formed.

The pattern defect inspection apparatus 1 shown in FIG. 1 has semiconductor integrated circuit chip regions CHP1 to CHP included in a wafer 4 as such a master stock.
This is an apparatus for inspecting 25 pattern defects. Such pattern defects are caused by inclusion of foreign matter during the process. The pattern defect inspection method is not particularly limited, but it can be realized by optically comparing patterns in the semiconductor integrated circuit chip regions. In this pattern defect inspection, the inspection result data D1 including the identification information of the inspection target wafer and the identification information of the defective cell having the pattern defect is acquired. For example, the wafer identification information in the inspection result data D1 is a unique number to the wafer,
The identification information of a defective basic cell having a pattern defect is I / O.
Address information for the entire wafer of the cell 12 and the basic cell 10 is used. In FIG. 2, semiconductor integrated circuit chip regions CHP7, CHP8, CHP12, CHP13, CH
The X mark shown on P18 indicates the position of the basic cell where the pattern defect exists.

When obtaining the required types of semiconductor integrated circuits by using the stocked wafers 4 after the pattern defect inspection, the workstation 2 uses the inspection result data D1 for the wiring process for the wafers 4. Based on this, the inter-basic-cell wiring pattern of the semiconductor integrated circuit of the type that does not use the pattern defective basic cell is assigned to the semiconductor integrated circuit chip area where the pattern defect exists.

The method will be described in more detail. First, in addition to the inspection result data D1, data D3 relating to the type and the number of required semiconductor integrated circuits and wiring pattern data D2 between basic cells for obtaining the required type of semiconductor integrated circuits are acquired. In the workstation 2, the inspection result data D1 is compared with the wiring pattern data and D2 (S1), and the required types and the number are satisfied with the minimum number of wafers, and each semiconductor integrated circuit chip area in the wafer is satisfied. The wiring pattern data of is determined.
That is, the most efficient chip array and wafer are determined (S2). For example, the wafer 4-shown in FIG.
When a, 4-b, 4-c are stocked, type A
It is assumed that 20 semiconductor integrated circuits of the above type, three semiconductor integrated circuits of the type B, and two semiconductor integrated circuits of the type C are manufactured. At this time, it is not possible to compare the pattern defect inspection result data D1 of each wafer 4-a, 4-b, 4-c with the wiring pattern data D2 of each type and configure it, for example, for each type. A semiconductor integrated circuit chip area is extracted. According to FIG. 4, the semiconductor integrated circuit chip area 40 without any X mark can correspond to any product type, and one semiconductor integrated circuit chip area 41 with X mark and shaded is It can correspond to the types B and C, and a large number of ×
The marked semiconductor integrated circuit chip region 42 can correspond to only a single product C. Based on this, one wafer 4-a is determined as one that can satisfy the required type and number with the minimum number of wafers, and a chip array on the wafer 4-a, that is, a product type. The array state of the A, B, and C chips is determined.

The data of the chip array and the wiring pattern data of the type corresponding to the array are given to the electron beam drawing apparatus 3. The electron beam drawing apparatus 3 draws a pattern directly on a mask or a wafer as a semiconductor integrated circuit becomes larger and finer. The wiring pattern data created by the logic design and the layout design is converted into drawing data for the electron beam drawing apparatus. Such conversion includes overlap removal for preventing the drawing accuracy from being deteriorated by multiple exposure due to overlapping of figures in the pattern defined by the design pattern data, and enlargement or reduction of the figure defined by the design pattern data. This is to perform dimensional correction for a case where it is desired to draw by drawing, correction of a proximity effect due to scattering of electron beams at the time of drawing, and processing for decomposing the above pattern into a basic figure that can be drawn by an electron beam drawing apparatus. The above data conversion is
Usually done on a large computer. It should be understood that such a computer is included in the electron beam drawing apparatus 3 in this embodiment. As a result, the required wiring pattern data is converted into electron beam drawing data. The electron beam drawing device 3 directly draws a wiring pattern between the basic cells on a resist for electron beam drawing on the wafer, for example, based on the electron beam drawing data and the chip array data. After that, the wiring pattern is completed through the steps similar to the photolithography technology such as development and resist removal, and the known etching technology.

According to the above embodiment, there are the following effects. (1) When the pattern defect information D1 of each semiconductor integrated circuit chip area included in a wafer is acquired in advance and a desired semiconductor integrated circuit is obtained using the wafer, which product type is selected according to the required product type and number To which semiconductor integrated circuit chip area of which wafer is to be assigned. At that time, by using the inspection result data D1, a pattern defective basic cell is selected for the semiconductor integrated circuit chip area having the pattern defect. By adopting the method of allocating to a product that is not used, it is possible to reduce waste or failure of the semiconductor integrated circuit chip region where the pattern defect exists, and thereby improve the chip yield. (2) In the case of obtaining a large number of semiconductor integrated circuits in a small amount, the required types and the respective numbers are taken into consideration, and the required types and the number are satisfied with the minimum number of wafers, and each semiconductor integrated circuit on the wafer is satisfied. By adopting the process of allocating the wiring pattern data of the chip area, it is possible to minimize the situation where the semiconductor integrated circuit chip area where the pattern defect exists is functionally defective, and it is possible to maximize the chip yield. . (3) When the method of (2) above is adopted, even when the patterns adopted for the respective wafers are different from each other, it is possible to form the wiring pattern between the circuit cells. By adopting electron beam drawing, the wiring pattern forming process can be streamlined. (4) It is most suitable for improving the chip yield of a logical LSI in which repair by redundancy is practically difficult.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, in the above-mentioned embodiment, the wiring pattern is directly drawn on the resist on the wafer by electron beam drawing, but a reticle such as a photomask may be formed by a stepper to perform exposure. In this case, several types of reticle application are possible, and they can be allocated to each wafer. When using such a reticle,
In the process of S2 in FIG. 1, the wafer name to be used is determined and is passed to the wiring construction department. Further, the present invention can be applied to those having a redundant configuration. For example, for a semiconductor integrated circuit chip area for a memory having a redundant circuit, a program for repairing a defective bit is performed in the same wiring process as above. This is positioned as an alternative process of a redundant program such as a laser fuse. Further, the method of the present invention is not limited to the MOS type semiconductor integrated circuit, but can be applied to various semiconductor integrated circuits such as bipolar or Bi-CMOS type.

In the above description, the invention made by the present inventor was mainly applied to a semiconductor integrated circuit of a gate array type which is a field of application which is the background of the invention, but the present invention is not limited thereto. Instead, it can be widely applied to the condition that the stocked wafer is used after leaving the predetermined wiring process.

[0024]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) In determining the function of each semiconductor integrated circuit chip area of the wafer by determining the wiring between the basic circuits, the pattern defective basic cell is selected for the semiconductor integrated circuit chip area where the pattern defect exists. By adopting the method of allocating to a product type that does not use, it is possible to reduce waste or failure of the semiconductor integrated circuit chip area where the pattern defect exists, and thus it is possible to improve the chip yield. . (2) In the case of obtaining a large number of semiconductor integrated circuits in a small amount, the required types and the respective numbers are taken into consideration, and the required types and the number are satisfied with the minimum number of wafers, and each semiconductor integrated circuit on the wafer is satisfied. By adopting the process of allocating the wiring pattern data of the chip area, it is possible to minimize the situation where the semiconductor integrated circuit chip area where the pattern defect exists is functionally defective, and it is possible to maximize the chip yield. . (3) By adopting electron beam drawing to form the wiring pattern between the circuit cells, the wiring pattern is formed even when the patterns adopted for the respective wafers are different from each other. The processing can be streamlined. (4) The effect that it is optimal for improving the chip yield of a logical LSI in which repair by redundancy is practically difficult is obtained.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a defect relief method according to an embodiment of the present invention.

FIG. 2 is a plan view of an example of a wafer used as a master stock for obtaining a gate array type semiconductor integrated circuit adopting a master slice method.

FIG. 3 is an explanatory diagram of an example of a semiconductor integrated circuit chip region on a wafer.

FIG. 4 is an explanatory diagram showing a plurality of wafers having different pattern defect states in order to explain a process of determining the most efficient chip array and wafer.

[Explanation of symbols]

 1 pattern defect inspection device 2 workstation 3 electron beam drawing device 4 wafer CHP1 to CHP25 semiconductor integrated circuit chip area D1 inspection result data D2 wiring pattern data by product type D3 data on required product type and its number 10 basic cell 12 I / O cell

Claims (4)

[Claims] 1. A wafer having a plurality of semiconductor integrated circuit chip regions in which a plurality of basic circuits are formed in advance and a desired function is realized by determining wiring between the basic circuits. Inspecting the pattern defects of each semiconductor integrated circuit chip area included, obtaining the inspection result data including the identification information of the wafer and the identification information of the defective basic circuit having the pattern defect, and for the wiring process for the wafer, Allocating a wiring pattern between basic circuits of a semiconductor integrated circuit of a type that does not use a pattern defective basic circuit to a semiconductor integrated circuit chip area where a pattern defect exists based on the inspection result data. And the defect remedy method. 2. The step of allocating the wiring pattern includes a step of obtaining data relating to the types of semiconductor integrated circuits required and the number thereof, and wiring pattern data between basic circuits for obtaining the semiconductor integrated circuits of the required type. And the step of acquiring, comparing the inspection result data and the wiring pattern data,
The defect relieving method according to claim 1, further comprising: determining the wiring pattern data of each semiconductor integrated circuit chip area on the wafer by satisfying the required types and the number of wafers with a minimum number of wafers. 3. A step of generating electron beam drawing data based on wiring pattern data of each semiconductor integrated circuit chip area on a wafer, and an electron beam drawing of a wiring pattern between basic circuits based on the electron beam drawing data. 3. The defect relieving method according to claim 2, further comprising: 4. A wafer having a plurality of semiconductor integrated circuit chip regions in which a plurality of basic circuits are formed in advance and a desired function is realized by determining wiring between the basic circuits. A means for inspecting a pattern defect of each semiconductor integrated circuit chip area included, and acquiring inspection result data including identification information of the wafer and identification information of a defective basic circuit having a pattern defect, and for a wiring process for the wafer, Based on the inspection result data, for the semiconductor integrated circuit chip area in which the pattern defect exists, the basic circuit inter-circuit wiring pattern of the semiconductor integrated circuit of the type that does not use the pattern defective basic circuit is selected, and each semiconductor integrated circuit in the wafer is selected. Data processing means for determining wiring pattern data in the circuit chip area, and Defect repair system.