JPH06139772A - Dynamic ram device - Google Patents

Abstract

PURPOSE:To reduce the backup power consumption by simplifying refresh circuits at the time of a V-RAM backup and to reduce the number of circuit to be backed up. CONSTITUTION:Make V-RAM 2 as a memory with a CAS before RAS refresh system. Make all of the followings as an integrated one body of IC with the V-RAM 2. These are a refresh CAS before RAS two phase clock generating circuit 4 used at the time of a backup, a selector 5 which selects the two phase clocks and a refresh counter 6 which successively incremently generates refresh row addresses by the selected clocks, and make a V-RAM device 1 as a backup refresh circuit 3 incorporated type memory. Thus, the back up circuit is the V-RAM device 1 only, the constitution becomes extremely simple and the backup power consumption becomes less.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic RAM (random access memory) device, and more particularly to a dynamic RAM device having a built-in refresh circuit.

[0002]

2. Description of the Related Art In a dynamic RAM, since the charges charged in its storage cells are gradually discharged over time, each storage cell constituting the RAM is periodically refreshed to store its stored information. It is necessary to prevent disappearance. In the information processing apparatus using such a RAM, when the stored information in the RAM is backed up when the power is cut off, it is necessary to refresh the RAM in the same manner.

FIG. 5 is a block diagram showing a conventional example of a memory backup control circuit using a RAM of this type. In FIG. 5, a dynamic RAM is a video RAM
An example of using (V-RAM) 16 is shown.

The clock generation circuit 9 generates a refresh clock for normal system operation, and the backup clock generation circuit 10 generates a refresh clock for backup. The clock selector 11 is a clock generation circuit 9 during normal system operation and during backup.
The refresh clocks of 10 and 10 are selected.

The refresh counter 12 generates a refresh load address for the V-RAM 16 in response to the refresh clock selected by the clock selector 11. The address buffer 13 takes in and holds the system address (row address and column address) during normal system operation, and takes in and holds the row address from the refresh counter 12 during refresh operation.

The address selector 14 switches between the row address and the column address derived from the address buffer 13 by a RAS / CAS switching signal, and the V-RAM1.
Supply to 6. RAS is a row address strobe signal and CAS is a column address strobe signal. The phase conversion circuit 15 includes both clock generation circuits 9 and 1.
Receiving each clock from 0, an RAS signal for refresh having a predetermined phase relationship is generated.

FIG. 6 is a timing chart of signals at various parts showing the operation of the circuit shown in FIG. Refresh during normal system operation is as follows. The clock selector 11 selects the clock of the clock generation circuit 9 and supplies it to the refresh counter 12, and the address buffer 13
Captures and holds the row address from the refresh counter 12. The refresh clock (FIG. 5A) from the clock generation circuit 9 is also supplied to the phase conversion circuit 15.

In response to this clock, the phase conversion circuit 15 delays this clock by a predetermined time (t0) and inverts RAS.
A signal (FIG. 6B) is generated and supplied to the V-RAM 16. Further, the refresh counter 12 counts up by "1" for each input clock to sequentially generate refresh row addresses (n, n + 1, n + 2, ...) (FIG. 6 (c)). This row address is sent to the V-RAM 16 via the address buffer 13 and the address selector 14.
Is supplied to.

The V-RAM 16 sequentially refreshes each memory cell forming the V-RAM row by row while selecting each RAM address at the fall of the inverted RAS signal from the phase conversion circuit 15.

The phase conversion circuit 15 sets the clock to t0.
The reason why the inverted RAS signal is generated after delaying is that the row address can be taken in and made into a row address in a stable state due to the presence of this delay amount t0.

Next, the refresh operation during backup will be described. At this time, the V-RAM 16 is backed up, but other than that, the backup clock generation circuit 10, clock selector 11, refresh counter 12, address counter 13, address selector 14, and phase conversion circuit 15 are also backed up by a battery (not shown). To be done.

The clock selector 11 selects the clock of the clock generation circuit 10 according to the backup switching signal and supplies it to the refresh counter 12. The address buffer 13 holds the row address from the refresh counter 12.

The refresh operation at this time is the same as the refresh operation during the normal system operation described above. That is, the clock of the clock generation circuit 10 is supplied to the refresh counter 11 to generate the refresh row address as described above, and the phase conversion circuit 1
5 is also supplied to generate an inverted RAS signal. VR
The AM 16 selects each row address at the falling edge of the inverted RAS signal and sequentially refreshes each memory cell for each row.

In this way, the memory is refreshed during normal system operation and battery backup. In this conventional refresh method at the time of backup, it is necessary to back up all the circuit parts of the backup clock generation circuit 10, the clock selector 14, and the phase conversion circuit 15 in addition to the V-RAM 16 by battery backup. Therefore, at the time of battery backup, there is a problem that the power consumption of the battery becomes extremely large, the backup time becomes short, and the amount of hardware increases due to the large number of backup refresh circuits.

To solve this problem, the technique disclosed in Japanese Patent Laid-Open No. 62-293593 has been proposed. FIG. 7 shows the circuit configuration thereof. The V-RAM device 17 includes the refresh counter 1 in addition to the V-RAM 18.
9 is built in. Then, as an external circuit of the V-RAM device 17, a two-phase clock generation circuit 21 for generating a two-phase clock required for refresh at the time of backup, the two-phase clock and a two-phase clock required for refresh at the normal system time. Selector 20 to select
And are added.

As the V-RAM 18, a memory that performs a refresh operation by the CAS before RAS refresh system is used, and therefore the two-phase clock generation circuit 21 generates a two-phase clock having a phase relationship required for this refresh system. It is a thing.

[0017]

With the configuration shown in FIG. 7, the number of circuits for refreshing at the time of backup is reduced, and the power consumption of the battery at the time of backup is reduced to lengthen the backup time. But,
It is still necessary to add an external circuit to the V-RA device 17, and from the battery for backup to the external selector 20 and the two-phase clock generation circuit 21 in addition to the V-RAM device 17. There is a disadvantage that backup power must be supplied and the configuration becomes complicated.

An object of the present invention is to eliminate the external attachment of a memory refresh control circuit during battery backup,
It is an object of the present invention to provide a dynamic RAM device that simplifies the configuration of a circuit device.

[0019]

A dynamic RAM device according to the present invention comprises a dynamic random access memory and a two-phase clock signal for generating a two-phase clock signal having a predetermined phase relationship in response to an external clock signal during memory backup. A generation circuit, a selector for selecting and deriving the two-phase clock signal from the two-phase clock signal generation circuit at the time of the memory backup, and a refresh for the memory in response to the input of the selected and derived two-phase clock signal. A refresh counter for generating an address for use in the memory, the two-phase clock signal generation circuit, the selector, and the refresh counter.

[0020]

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the basic configuration of the present invention. The V-RAM device 1 has a configuration in which a refresh circuit 3 is also incorporated in addition to the V-RAM 2, which is configured as a one-chip IC. To be done.

The refresh circuit 3 has a two-phase clock generation circuit 4, a selector 5 and a refresh counter 6, and the two-phase clock generation circuit 4 responds to a refresh clock signal 7 from the outside and has a constant phase. Generate the relevant two-phase clocks. The selector 5 selectively derives the two-phase clock from the two-phase clock generation circuit 4 and the two-phase clock signal required in the normal system according to the backup switching signal 8.

The refresh counter 6 is the selector 5
One of the two-phase clock signals derived alternatively by is input and derived as the RAS signal of the V-RAM2. The other clock signal from the selector 5 becomes the CAS signal of the V-RAM 2.

Here, the V-RAM 2 is assumed to perform a refresh operation by a two-phase clock signal having a fixed phase relationship, which is a so-called CAS before RAS refresh system.

In such a configuration, during normal system operation, the selector 5 selects the two-phase clock signal during normal system operation and supplies it to the refresh counter 6, and this refresh counter 6 generates a refresh address, and the V-RAM 2 is supplied. Refresh is performed.
Note that no address from the outside is used during refresh.

At the time of memory backup, the V-RAM device 1 with a built-in refresh circuit is backed up by a battery (not shown). At this time, the selector 5 selects the refreshing two-phase clock signal by the two-phase clock generating circuit 4, causes the refresh counter 6 to generate a refreshing address, and refreshes the V-RAM 2.

FIG. 2 is a circuit block diagram of an embodiment of the present invention, and the same portions as those in FIG. 1 are designated by the same reference numerals. In this embodiment, as described above, the V-RAM 2 is a CAS.
A memory that performs refresh by the before RAS refresh method is used. Therefore, the refresh counter 6 counts the inverted RAS signal input from the selector 5 and sequentially generates the refresh row address.

Further, in the case of the CAS before refresh method, the two-phase clock generation circuit 4 uses the inversion RA for refresh as a two-phase clock signal having a constant phase relationship.
An S signal and an inversion CAS signal for refresh whose phase leads that of the S signal are generated. This two-phase clock generation circuit 4
4A shows a concrete example of the above, and FIG. 4B shows an operation timing chart thereof.

As shown in FIG. 4A, an external refresh clock signal (RFSH CK) is applied to the clock input of a D-FF (delayed flip-flop) 41, and its inverted Q output is used as the D input. By that Q
Inverted RAS signal for refresh (inverted RFRA
S) is generated. The Q output and the refresh clock signal are input to a 2-input AND gate 42, and an inverted CAS signal for refresh (inverted RFCAS) is output from the output.
Is output.

The waveform of each part is as shown in FIG. 4B, and the two-phase clock required for the CAS before RAS refresh system can be obtained.

The selector 5 is a RAS selector 51 and a CAS.
The RAS selector 51 includes a selector 52 and selects an inverted RAS signal during normal system operation and an inverted RAS signal for refresh during backup. CAS
The selector 52 selects between the inverted CAS signal during normal system operation and the refreshed inverted CAS signal during backup.

DT which is an input / output pin of V-RAM2
The / OE terminal switches between a data transfer mode and a read mode. When it is at a low level, it indicates a data transfer cycle, and when it is at a high level, it is a read cycle. Further, the WB / WE terminal is in the write per bit mode and the write mode, and in the high level, it is in the write mode.

Further, the SOE terminal is a serial read port output control clock input terminal, and when it is activated low, data is output. Furthermore, S
The C terminal is a serial read port control clock input terminal, and a serial access operation is started by this clock input.

FIG. 3 is an operation timing chart of each part for explaining the operation of the circuit of FIG. First, referring to the timing chart in the left half of FIG. 3, for the read and write operations during normal system operation.

At this time, the signals of the inverted RAS and the inverted CAS have the phase relationship shown in FIGS.
The falling timing t1 of the AS signal has a phase advance with respect to the falling timing t2 of the inverted CAS signal.

The RAS selector 51 of the selector 5 selects this inverted RAS signal and supplies it to the refresh counter 6, and the CAS selector 52 selects this inverted CAS signal and supplies it to the V-RAM 2. Also, FIGS. 3 (c) and 3 (d)
As shown in, the read / write address in which the row address and the column address are time-division multiplexed, and further the data (at the time of writing) are input to the V-RAM 2.

Falling timing t1 of the inverted RAS signal
Then, the V-RAM 2 selects a row address and selects a column address at the falling timing t2 of the inversion CAS signal to enter the access state. As a result, as shown in FIG.
As shown in (e), write data is written in the periods t3 to t6 during writing, and data is read in the periods t4 to t5 during reading.

The refresh operation during normal system operation is shown in the timing chart in the right half of FIG. The refresh operation at this time is performed by the CAS before RAS refresh method. In this case, the two-phase clock from the two-phase clock generation circuit 4 is selected by the selector 5. The relationship between the two-phase clocks is shown in FIG.
As shown in (b), the falling timings t7 and t9 of the inverted CAS signal are the same as the falling timing t8 of the inverted RAS signal.
And has a phase relationship that is more advanced than t10.

Since no read / write operation is performed during this refresh, no address or data is input.

When the V-RAM 2 detects that the inverted RAS signal is low level at the falling timing of the inverted RAS signal, it enters the refresh mode. In the refresh mode, the refresh counter 6 responds to the input inverted RAS signal and counts up by "1" each time to generate a row address to generate V.
Address each row of RAM2 sequentially.

Thereafter, each storage cell is precharged at the high level of the inverted RAS signal, and refresh is sequentially performed for each row at the falling timings t8 and t10.

At the time of the refresh operation during battery backup, the entire V-RAM device 1 with a built-in refresh circuit is backed up by a battery (not shown). At this time, the two-phase clock generation circuit 4 responds to the refresh clock (RFSH CK) from the outside, and
(B) Two-phase clock having a waveform as shown in FIG.
A two-phase clock as shown in (f) and (g) is generated. The phase relationship of the two-phase clock is the same as that at the time of refreshing during normal system operation (right half of FIGS. 3A and 3B).

At this time, the two-phase clock (reverse RFR
AS and RFCAS) have a cycle of RAS and C
It is assumed that the length is selected to be sufficient to satisfy the refresh standard of the video RAM as compared with the synchronization with AS.

The RAS selector 51 of the selector 5 selects the inverted RFRAS signal by the backup switching signal 8 and supplies it to the refresh counter 6, and the CAS selector 5
Is selected by the backup switching signal 8 and supplied to the V-RAM 2.

Hereinafter, the V-RAM 2 is sequentially refreshed row by row in the same manner as the refresh operation during the normal system operation described above.

Although the V-RAM is used as the D-RAM in the above embodiment, it can be widely applied to general dynamic RAM.

[0047]

As described above, according to the present invention, all the backup refresh circuits are integrated into the RAM device and incorporated as a memory IC.
Since it is sufficient to supply the backup battery power only to the unit and no external attachment is required, the circuit configuration can be extremely simplified. In addition, since the circuit configuration is simplified, power consumption during battery backup is reduced and backup time is, of course, longer.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of the present invention.

FIG. 2 is a block diagram showing an embodiment of the present invention.

FIG. 3 is a time chart showing the operation of the embodiment of FIG.

FIG. 4A is a diagram showing a specific example of a two-phase clock generation circuit, and FIG. 4B is an operation waveform diagram thereof.

FIG. 5 is a block diagram showing a conventional V-RAM backup control circuit.

FIG. 6 is an operation time chart of the block of FIG.

FIG. 7 is a block diagram showing another conventional V-RAM backup control circuit.

[Explanation of symbols]

 1 V-RAM device 2 V-RAM 3 refresh circuit 4 2-phase clock generation circuit 5 selector 6 refresh counter 51 RAS selector 52 CAS selector

Claims (3)

[Claims] 1. A dynamic random access memory and a two-phase clock signal having a predetermined phase relationship in response to an external clock signal when the memory is backed up.
Phase clock signal generating circuit, a selector for selecting and deriving the two phase clock signal from the two phase clock signal generating circuit at the time of the memory backup, and the selector in response to the input of the selected and derived two phase clock signal. A dynamic RAM device including a refresh counter for generating a refresh address for a memory, and including the memory, the two-phase clock signal generation circuit, the selector, and the refresh counter. 2. The memory is CAS (column address strobe) before RAS (row address strobe).
The memory is a memory that performs a refresh operation by a refresh method, and the two-phase clock signal generation circuit has a refresh RAS clock signal and a phase leading the refresh RAS clock signal in response to the external clock signal. 2. The dynamic RAM device according to claim 1, wherein the dynamic RAM device is configured to generate an inversion RAS clock for refreshing. 3. The dynamic RAM according to claim 1, wherein the memory is a video RAM.
apparatus.