JPH06131248A - Stored data read controller - Google Patents

Abstract

PURPOSE:To read data out of a memory successively at a certain period. CONSTITUTION:This controller is equipped with a memory controller 1 which specifies row and column addresses successively at the certain period and DRAMs 3 and 4 out of which data can be read at a high speed from addresses of the 1st column in respective rows by specifying both the addresses of the row and column and from the address of the 2nd column by specifying only the column address. Data in addresses of a (2n)th row are delayed by two cycles of a system clock CLK through a register group 9 and led to a multiplexer 10 and after the final data D511 of the (2n)th row is outputted, starting data D512, D513,... of an (2+1)th row are led to the multiplexer 10 without being passed through the register group 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data to be read out first from each row, for which data at the row and column addresses are read out by designating both row and column addresses, and data to be read out from the second row onward in the same row. The present invention relates to a storage data read control device that includes a memory for sequentially reading out data of column addresses only by designating a column address, and reads out storage data from this memory.

[0002]

2. Description of the Related Art Conventionally, there is a system for converting a color television signal such as an NTSC system into high resolution video data and storing it in a field memory, and then reading this video data from the field memory and reproducing it as the color television signal. Are known.

In this system, it is necessary to access the effective video data per horizontal line of the screen from the field memory at high speed and read them continuously, and convert the video data into a color television signal in real time.
For example, if an NTSC color television signal is sampled at a frequency of 4 fsc (4 times the color subcarrier 3.58 MHz), 768 video data are read from the field memory at a constant cycle of 70 ns per horizontal line of the screen. There must be.

Conventionally, a dedicated image memory was used as the field memory, but the dedicated image memory was expensive.

On the other hand, in recent years, 4M bits (512 rows × 51)
A large-capacity general-purpose DRAM (dynamic RAM) of 2 columns × 16 bits) has been commercialized at a relatively low cost. When the field memory is configured by using this DRAM, the video data (luminance data and color difference data) for one field can be stored in one DRAM, which simplifies the structure of the field memory and reduces the cost. Can be achieved.

[0006]

However, in the horizontal direction 1
Since the video data for the lines is 768 as described above, these video data are stored over the row addresses for two lines in the DRAM. On the other hand, in the DRAM, the number of data that can be continuously accessed at high speed is up to the number of column addresses for one row,
That is, the maximum number of data is 512, and when accessing the data of the next row, it takes time to specify the address of the next row.

Therefore, when the video data of one line in the horizontal direction is read, the time until the video data of the first column address of the next row address is read is longer than the time when the video data of another column address is read. Also becomes longer. As a result, discontinuity occurs in the read video data, making it impossible to properly reproduce the color television signal.

The present invention solves the above problems, and an object of the present invention is to provide a storage data read control device capable of continuously reading data from a memory at a constant cycle.

[0009]

In order to achieve the above object, the first aspect of the present invention has addresses of N (≧ 2) rows and M (≧ 2) columns, and data in the same row is read at high speed. Possible memory, read addressing means for designating the row and column addresses of this memory, and j of said memory.
The first path for guiding the read data from the row to the output side, the second path for guiding the read data from the k (≠ j) row of the memory to the output side, and the first path. Delay means for delaying the read data passing through the first path by a preset predetermined time, switching means for connecting one of the first path and the second path to an output side, and the j
Switching control means for controlling the switching means so as to switch from the first path to the second path after the last read data to be read from the row passes through the first path.

[0010]

According to the stored data read control device of the present invention, each read data of the column address of the jth row is read out for a predetermined time, for example, the stored data to be read first in the k (≠ j) th row. Is delayed by the time difference between the time required to read the stored data and the time required to read the second and subsequent stored data, and is guided to the output side through the first path. Then, both the row and column addresses are designated for the storage data to be read first from the address of the k-th row, and the last read data to be read from the j-th row is passed from the first path after passing through the first path. The read data of the kth row address is switched to the second path and guided to the output side through the second path, so that the jth row is read at the same cycle as the output of the read data of each column of the jth row. It is possible to lead the first read data of the k-th row to the output side after the read data last read from is output.

[0011]

1 is a block diagram showing a first embodiment of a storage data read control device of the present invention. The storage data read control device includes a memory controller 1, a selector 2 and a DR.
It has AMs (dynamic RAMs) 3 and 4, a register group 9 (registers 9a and 9b) as a delay means, and a multiplexer 10, as well as registers 5, 6, 8 and 11 and a multiplexer 7. Then, the stored data read control device temporarily stores the video data from the image processing means (not shown) connected to the input side, and reads the stored video data at a constant cycle to correct the synchronization deviation of the color television signal. Also, it functions as an output buffer circuit to a circuit that applies a special effect such as image enlargement / reduction or multi-screen during reproduction.

The image processing means is adapted to convert a signal photoelectrically converted by an image pickup device such as a CCD into video data and output it to a storage data reading control device.
The detailed description of the video data will be described later.

The memory controller 1 sequentially outputs the address signal ADR designating the row and column addresses of the DRAMs 3 and 4 to the DRAMs 3 and 4 at the same cycle as the system clock CLK, and at the same time, the RAS signal and the CAS signal which are address latch timing signals. A signal is output to the DRAMs 3 and 4 to control writing and reading of data to and from the DRAMs 3 and 4. Then, the video data from the image processing means is alternately written to the DRAMs 3 and 4 for each field, and the video data is sequentially read from the DRAMs 3 and 4 on which the video data is not written.

The memory controller 1 also outputs a data latch timing signal h to the registers 5 and 6 to latch the input data to the registers 5 and 6. Further, the memory controller 1 outputs a switching signal i to the multiplexer 10 to switch the multiplexer 10 as described later.

The selector 2, whose output connection is switched by the field identification signal FI, switches the video data input from the preceding image processing means to the DRAMs 3 and 4 for each field and alternately outputs them. . As a result, for example, the even field video data is transferred to the DRAM 3 and the odd field video data is transferred to the DRA.
Written to M4.

The register 5 outputs the video data read from the DRAM 3 to the multiplexer 7 in synchronization with the data latch timing signal h.
Is for outputting the video data read from the DRAM 4 to the multiplexer 7 in synchronization with the data latch timing signal h.

The multiplexer 7 has its input connection switched by the field identification signal FI. By alternately switching the register 5 and the register 6 for each field, the register outputting the video data is registered. It is designed to connect to 8. The register 8 synchronizes the video data from the multiplexer 7 with the system clock CLK and operates the multiplexer 1 described later.
0 and output to the register group 9.

The DRAMs 3 and 4 are, for example, 512 rows × 51.
Each of them is composed of one 4 Mbit general-purpose DRAM of 2 columns × 16 bits, and stores the video data input through the selector 2. That is, DRAMs 3, 4
Then, when the RAS signal from the memory controller 1 falls to the low level, the address signal ADR input from the memory controller 1 is latched as a row address, and the CAS signal from the memory controller 1 falls to the low level. The address signal ADR input at the time point is latched as a column address, and the data of the latched row and column address is accessed (written or read).

In the DRAMs 3 and 4, each time the CAS signal falls from the high level to the low level while the RAS signal is at the low level, the address signals ADR input at the time of the fall of the CAS signal become the RAS. Data is accessed as each column address of the row address when the signal falls.

That is, the DRAMs 3 and 4 need to specify the row address and the column address for the data to be read first in a predetermined row, but when reading the data in the same row as this row address, the column address is read. By designating only the address, the data at the address of the row and column can be read at high speed.

Here, a method of storing video data in the DRAMs 3 and 4 will be described with reference to FIGS. 2, 3 (a) and 3 (b). In the NTSC color television signal, horizontal scanning is interlaced, and the frames of horizontal line numbers 0, 1, 2, ..., 478, 479 shown in FIG. 4 are even horizontal line numbers 0, 2, 4, 4. ..., 478 fields and odd horizontal line numbers 1, 3, 5, ..., 47
And 9 fields.

The image processing means converts the color television signal into, for example, 4 fsc (color subcarrier of 3.58 MHz, 4 fsc).
(2 times) frequency to sample 768 luminance data (Y) per horizontal line of the screen (1 horizontal line), and further sample at 2 fsc frequency to obtain two types of color difference data (RY, B-Y) are generated alternately. The luminance data (Y) and the color difference data (RY, BY) are generated by the image processing means with 8 bits as 1 byte.

Therefore, as the video data for one field, the luminance data (Y) is 768 bytes per horizontal line for 240 lines, and the color difference data (RY, BY) is alternately 384 bytes per horizontal line. 240 lines each are generated.

On the other hand, in the DRAMs 3 and 4, as shown in FIG.
The luminance data (Y) is placed in the upper 8 bits, and the color difference data (RY, B- is placed in the lower 8 bits).
Y) is recorded respectively. In addition, since there are 768 image data lines per horizontal line, DRAM
It is designed to be stored in two lines 3, 4.

That is, the luminance data (Y) is shown in FIG.
As shown in (a) and (b), horizontal pixel numbers 0 to 511
Data D0 to D511 of the horizontal pixel numbers 512 to 767 in the upper 8 bits of the column addresses 0 to 511 of the second nth row of the DRAMs 3 and 4, for example.
Are column addresses 0 to 51 of the 2n + 1th row of the DRAMs 3 and 4.
The upper 8 bits of 1 are sequentially stored. As for the color difference data (RY, BY), as shown in FIGS. 3A and 3B, the color difference data (RY) is in even columns and the color difference data (BY) is in odd columns. ) Are stored in order.

As described above, since the color difference data (RY) and the color difference data (BY) are alternately stored at the adjacent addresses, the color difference data (RY, BY) is output at the output side circuit. To color signals can be easily performed.

Next, the problem in reading the video data stored in the DRAMs 3 and 4 will be described.
As described above, in the DRAMs 3 and 4, once the row address is designated, the data in the same row as the row address can be continuously read by designating only the column address.

However, for example, when shifting from the row address 2n to the next row address 2n + 1, the RAS signal is set to the high level, then the row address 2n + 1 is designated and the RAS signal is lowered to the low level, and then the column is changed. It is necessary to sequentially specify the column address from address 0.

Therefore, it takes time for the RAS signal to return to a high level and for specifying the row address. In this embodiment, after the data D511 of the 511th column of the row address 2n is read out, 0 of the row address 2n + 1 is read.
It takes at least three system clock CLK cycles until the data D512 in the column is read.

Therefore, the data D0 to D of the row address 2n
511 is followed by the data D of the row address 2n + 1 as it is.
When data 512 to D767 are read, data D0 to D511
The read cycle of the data D513 to D767 is one system clock CLK cycle, but only the read cycle of the data D512 of the row address 2n + 1 is three system clock CLK cycle. As a result, when the read video data is converted into a color television signal, the difference in the cycle causes distortion in the image.

In order to deal with this, in the first embodiment,
The data D0 to D511 at the row address 2n are transferred to the register group 9
By 2 system clocks CLK, and the delayed data D0 to D511 are multiplexed by the multiplexer 10
On the other hand, while the data D511 is read out, the multiplexer 10 is switched to switch the registers 9a, 9
Data D of row address 2n + 1 directly without passing through b
Data after 512 is output through the multiplexer 10 so that two cycles of the system clock CLK are canceled from the read cycle of the data D512.

That is, the register 9a delays the video data from the multiplexer 7 by one cycle of the system clock CLK and outputs it to the register 9b.
In b, the video data from the register 9a is further delayed by one cycle of the system clock CLK and output to the multiplexer 10. These registers 9a, 9
By b, the video data from the multiplexer 7 is delayed by two cycles of the system clock CLK and output to the multiplexer 10.

The multiplexer 10 switches between the video data from the register 8 and the video data from the register 9b in response to the switching signal i from the memory controller 1 and outputs it to the register 11. The register 11 outputs the video data from the multiplexer 10 to the output side in synchronization with the system clock CLK.

Next, the row address 2 is read from the DRAM 3 described above.
The operation of accessing the n, 2n + 1 video data will be described with reference to the timing chart of FIG. For convenience of description, reading from the DRAM 3 will be described as an example, but the DRAM 4 operates similarly to the DRAM 3.

For example, the memory controller 1 outputs, for example, a row address 2n in synchronization with the fall of the system clock CLK, and the RAS signal falls from a high level to a low level in order to latch the row address 2n. Then, the column address 0 is output, the CAS signal falls from the high level to the low level, and the DRAM 3
The data D0 at the address of the 2nth row and the 0th column is read from. The data D0 is output to the register 5 and latched at the rising edge of the data latch timing signal h.

Subsequently, the column address is sequentially output from 1 to 511 in the cycle of the system clock CLK while the RAS signal remains low, and the level of the CAS signal is changed from high to low in accordance with the column address. In synchronization with this level change, the data D1 to D511 of the column addresses 1 to 511 of the 2nth row are sequentially read from the DRAM 3 at the cycle of the system clock CLK and output to the register 5.

These data D1 to D511 are sequentially latched at the rising edge of the data latch timing signal h. Then, the data D511 is latched at the rising time point t1 of the data latch timing signal H1 (FIG. 5, h). The high level period T1 of the data latch timing signal H1 is longer than the other high level periods T2 by two cycles of the system clock CLK, and the data signal b from the register 5 has the other output period of the data D511. System clock CL rather than the data output period of
It becomes longer by two K cycles.

The data signal b is guided to the register group 9 via the multiplexer 7 and the register 8, delayed by two cycles of the system clock CLK by the registers 9a and 9b, and output to the multiplexer 10 (FIG. 5, FIG. 5). d).

In the period T1, the RAS signal is
It changes to a high level in synchronization with the rising edge of the system clock CLK1 and falls at the next rising edge of the system clock CLK2. At this time, the system clock C
Row address 2 generated in synchronization with the falling edge of LK1
n + 1 is latched. Then, the CAS signal falls in synchronization with the next rise of the system clock CLK3, and at this time, the column address 0 generated in synchronization with the fall of the system clock CLK2 is latched. As a result, the data D512 at the address of the 2n + 1th row and the 0th column from the DRAM 3 is output to the register 5 after three cycles of the system clock CLK from the output time of the data D511, and is output to the multiplexer 10 via the multiplexer 7 and the register 8. It

On the other hand, the switching signal i to the multiplexer 10
Changes from the high level to the low level in synchronization with the rise of the system clock CLK4 after the data D511 in the delayed data signal d is output (time point t
2). Due to this level change, the multiplexer 10
The passage of the delayed data signal d from the register group 9 is switched to the passage of the delayed data signal c from the register 8 to the data signal c. Therefore, after one cycle of the system clock CLK has passed since the data D511 was output from the multiplexer 10, the data D512 is output (FIG. 5, e). As a result, all the data D0 to D767 are output from the register 11 in the same cycle as the system clock CLK (FIG. 5, f).

Next, a second embodiment of the storage data read control device according to the present invention will be described with reference to FIG. Note that FIG.
In FIG. 1, the same reference numerals as those in FIG. 1 have the same functions. In the second embodiment, instead of the memory controller 1 and the register group 9, the memory controller 100
And a register group 90 are provided. Then, using the horizontal blanking period before the start of image scanning, the data D5 of the first column address 0 in the row address 2n + 1 is stored in the registers 90a and 90b forming the register group 90.
12 and the data D513 of the column address 1 are stored in advance, and these data D512 and D513 are read out after the reading of the data D511 of the row address 2n.

That is, the memory controller 100 is
The data D512 and the data D513 at the row address 2n + 1 are transferred to the DRAM 3 or DR during the horizontal blanking period.
Read from AM4, multiplexer 7 and register 8
A predetermined RAS signal to the DRAM 3 or DRAM 4 in order to be stored in the registers 90a and 90b in advance via
The CAS signal and the address signal ADR are generated and output, and the data latch timing signal h is output to the registers 5 and 6.

Further, the memory controller 100 reads the data D511 at the row address 2n and then performs RAS.
Raise signal to high level, then row address 2n +
1 is designated and column address 2 is designated. As a result, the data D514 is read. Further, the memory controller 100 has the registers 90a and 90 within the period (two cycles of the system clock CLK) from the reading of the data D511 to the reading of the data D514.
The clock enable signal j and the switching signal i are output to the registers 90a and 90b and the multiplexer 10 so that the data D512 and D513 stored in b are sequentially output from the multiplexer 10.

Next, in the second embodiment, the DRAM
The operation of accessing the video data of the row addresses 2n and 2n + 1 from No. 3 will be described with reference to the timing charts of FIGS. For convenience of explanation, reading from the DRAM 3 will be described as an example.
Works the same as.

That is, as shown in FIG. 7, at a predetermined time point t3 of the horizontal blanking period, the system clock CLK is
In synchronization with the falling edge of 11, the memory controller 100
The row address 2n + 1 is output from the DRAM to the DRAM 3 and RA
The S signal falls to the low level in synchronization with the rise of the system clock CLK12, and the row address 2n +
1 is latched. After this, the system clock CLK1
The column address 0 is output in synchronization with the falling edge of 2 and the CA is output in synchronization with the rising edge of the system clock CLK13.
The S signal falls and the data D512 is read from the DRAM 3. Then, the column address 1 is output in synchronization with the fall of the system clock CLK13, the CAS signal falls in synchronization with the rise of the system clock CLK14, and the data D513 is read from the DRAM 3.

These data D512 and D513 are latched by the register 5 and output to the multiplexer 7 at the rising points t4 and t5 of the data latch timing signal h from the memory controller 100, respectively, and are output from the multiplexer 7 to the register 8 via the register 8. Group 90
Is output to. The register group 90 starts operation when the clock enable signal j changes to high level in synchronization with the rising of the system clock CLK14. Then, the data D512 and D513 from the register 8 are shifted in the register group 90 in synchronization with the system clocks CLK15 and 16, and the data D512 is transferred to the register 9
At 0a, the data D513 is latched (stored) in the register 90b.

After that, when the horizontal blanking period ends, as shown in FIG. 8, the memory controller 100 outputs the row address 2n in synchronization with the fall of the system clock CLK21, and further the system clock CLK.
The column address 0 is output in synchronization with the falling edge of 22. Then, the column address 1 is sequentially incremented at the cycle of the system clock CLK. As a result, the data D0, D1, ... Are sequentially read from the DRAM 3.

Then, as shown in FIG. 9, the row address 2
After the data D511 of n is read from the DRAM 3,
R in synchronization with the rising edge of the system clock CLK31
The row address 2n + 1 is synchronized with the fall of the system clock CLK31 when the AS signal rises to the high level.
Is designated, and column address 2 is designated in synchronization with the fall of the system clock CLK32. As a result, after the data D511 is read from the DRAM 3, the data D514 is read from the DRAM 3 after two cycles of the system clock CLK have elapsed.

On the other hand, in synchronization with the rise of the system clock CLK32, the clock enable signal j changes to the high level, the register group 90 restarts its operation, and the data D512 and D513 stored in the register group 90.
Is synchronized with the system clock CLK by multiplexer 1
It is sequentially output to 0. Further, the system clock CL
When the switching signal i rises to a high level in synchronization with the rising of K32, the registers 90a and 90b are
The data D512 and D513 from the multiplexer 10
To the register 11.

As a result, the data D512, D51
3 is output from the multiplexer 10 following the data D511 in synchronization with the system clock CLK. After the output of the data D513 from the register group 90, the switching signal i changes to the low level in synchronization with the rising of the system clock CLK34. At this time, the data D514 is being output from the register 8 to the multiplexer 10, and the data D51 is followed by the data D51.
4 is led from the multiplexer 10 to the register 11.

As described above, during the horizontal blanking period, the data D512 and D513 of the column address 2 of the row address 2n + 1 are read from the DRAMs 3 and 4 in the register group 90 and then stored in advance, and the row addresses 2n from the DRAMs 3 and 4 are stored.
Of the column address 511 designated at the end of the data D511
Data D512 and D513 are registered in synchronism with the system clock CLK during the period of two cycles of the system clock CLK from the reading of the data D514 of the first designated column address 2 of the row address 2n + 1. Since data is read from the group 90, data D0 to D
All 767 can be output from the register 11 in the same cycle.

[0052]

According to the present invention, the read data read from the j-th row is delayed by a predetermined time and guided to the output side, and then k (≠
j) Since the storage data to be read first in the row is guided to the output side, the read data in the jth row and the read data in the kth row can be read continuously at a constant cycle and at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a storage data read control device of the present invention.

FIG. 2 is an image diagram showing a relationship between a DRAM address and data.

3A and 3B are image diagrams showing a data storage state of a DRAM, in which FIG. 3A shows data in a 2n-th row and FIG. 3B shows data in a 2n + 1-th row.

FIG. 4 is an image diagram showing horizontal lines and pixel numbers of an image.

FIG. 5 is a timing chart showing the operation of the first embodiment.

FIG. 6 is a block diagram showing a second embodiment of the storage data read control device.

FIG. 7 is a timing chart showing the operation of the second embodiment, showing the operation in the horizontal blanking period.

FIG. 8 is a timing chart showing the operation of the second embodiment, showing access to the data of the 2n-th row.

FIG. 9 is a timing chart showing the operation of the second embodiment, mainly showing access to the data of the 2n + 1th row.

[Explanation of symbols]

1,100 Memory Controller 2 Selector 3,4 DRAM 5,6,8,9a, 9b, 11,90a, 90b Register 7,10 Multiplexer

Claims (1)

[Claims] 1. A memory having addresses of N (≧ 2) rows and M (≧ 2) columns, in which data in the same row can be read at high speed, and reading for designating a row address and a column address of the memory. Addressing means, a first path for leading read data from the j-th row of the memory to the output side, and a second path for guiding read data from the k (≠ j) row of the memory to the output side. Intervening in the first path, the first path
Delaying means for delaying the read data passing through the path for the predetermined time by a predetermined time, the first path and the second path.
And switching means for connecting one of the paths to the output side, and for switching from the first path to the second path after the last read data to be read from the j-th row has passed through the first path. A storage data read control device comprising: a switching control means for controlling the switching means.