JPH06151648A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH06151648A JPH06151648A JP4297153A JP29715392A JPH06151648A JP H06151648 A JPH06151648 A JP H06151648A JP 4297153 A JP4297153 A JP 4297153A JP 29715392 A JP29715392 A JP 29715392A JP H06151648 A JPH06151648 A JP H06151648A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- resin
- mounting
- sealing body
- sealed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】
【目的】 面実装型半導体装置１において、封止体７と
実装基板８との間に適度なクリアランスを確保する。
【構成】 面実装型半導体装置１において、封止体７の
実装基板８側の下面にスタンドオフ７１を構成する。
(57) [Summary] [Purpose] In the surface-mounted semiconductor device 1, an appropriate clearance is secured between the sealing body 7 and the mounting substrate 8. [Structure] In the surface-mounting type semiconductor device 1, a standoff 71 is formed on the lower surface of the sealing body 7 on the mounting substrate 8 side.
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に関し、特
に、面実装型構造を採用する半導体装置に適用して有効
な技術に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique effectively applied to a semiconductor device adopting a surface mounting type structure.
【０００２】[0002]
【従来の技術】面実装型構造の半導体装置としてＱＦＰ
(Ｑuad Ｆlat Ｐackage)構造を採用する樹脂封止型半導
体装置がある。この種のＱＦＰ構造を採用する樹脂封止
型半導体装置はゲートアレイ、マスタスライス等所謂特
定用途向けのＩＣであって入出力端子数が多い場合、比
較的量産性が要求される場合等に使用される。2. Description of the Related Art QFP is used as a semiconductor device having a surface mount type structure.
There are resin-sealed semiconductor device which employs the (Q uad F lat P ackage) structure. A resin-sealed semiconductor device adopting this type of QFP structure is a so-called IC for a specific application such as a gate array and a master slice, and is used when there are a large number of input / output terminals and when relatively mass producibility is required. To be done.
【０００３】ＱＦＰ構造を採用する樹脂封止型半導体装
置は、論理回路システムを搭載した半導体ペレットの外
部端子と内部リードとの間が電気的に接続され、前記半
導体ペレット及び内部リードが樹脂封止体（樹脂パッケ
ージ）で封止される。また、この樹脂封止型半導体装置
は前記内部リードと一体化された外部リードが樹脂封止
体の外周囲に配列される。前記樹脂封止体の平面形状は
半導体ペレットの平面形状の相似形で構成され、外部リ
ードは樹脂封止体の４つの辺（４つの側面）に夫々の辺
に沿って夫々複数本配列される。つまり、ＱＦＰ構造を
採用する樹脂封止型半導体装置は所謂４方向リード配列
構造で構成される。In a resin-sealed semiconductor device adopting a QFP structure, an external terminal of a semiconductor pellet on which a logic circuit system is mounted and an internal lead are electrically connected, and the semiconductor pellet and the internal lead are resin-sealed. It is sealed with a body (resin package). Further, in this resin-encapsulated semiconductor device, outer leads integrated with the inner leads are arranged around the outer periphery of the resin encapsulant. The planar shape of the resin encapsulant is similar to the planar shape of the semiconductor pellet, and a plurality of external leads are arranged on each of the four sides (four side surfaces) of the resin encapsulant along each side. . That is, the resin-sealed semiconductor device adopting the QFP structure has a so-called four-direction lead arrangement structure.
【０００４】前記ＱＦＰ構造を採用する樹脂封止型半導
体装置はプリント配線基板等の実装基板の実装面に実装
される。この実装は樹脂封止型半導体装置の外部リード
と実装基板の実装面の端子との間を半田で電気的にかつ
機械的に接続することで行われる。実装されたＱＦＰ構
造を採用する樹脂封止型半導体装置は、外部リードによ
って、樹脂封止体の前記実装基板の実装面と対向する下
面と前記実装面との間に適度なクリアランス（隙間）が
設定される。The resin-sealed semiconductor device adopting the QFP structure is mounted on the mounting surface of a mounting board such as a printed wiring board. This mounting is performed by electrically and mechanically connecting the external leads of the resin-sealed semiconductor device and the terminals on the mounting surface of the mounting substrate with solder. In the resin-encapsulated semiconductor device adopting the mounted QFP structure, an appropriate lead is provided by an external lead between the lower surface of the resin-encapsulated body facing the mounting surface of the mounting substrate and the mounting surface. Is set.
【０００５】[0005]
【発明が解決しようとする課題】前述のＱＦＰ構造を採
用する樹脂封止型半導体装置は、半導体ペレットに搭載
される回路システムの論理ゲート数の増加、入出力端子
数の増加、論理ゲート回路の高速化等により、発熱量が
増大する傾向にある。発熱量が増大すれば、回路システ
ムの特性に変化が発生するだけでなく、クラックの発生
等、樹脂封止体が破損する。そこで、ＱＦＰ構造を採用
する樹脂封止型半導体装置の樹脂封止体に熱伝導性が高
い金属性の放熱板を装着する、開発が進められている。The resin-encapsulated semiconductor device adopting the QFP structure described above increases the number of logic gates, the number of input / output terminals, and the number of logic gate circuits in a circuit system mounted on a semiconductor pellet. The heat generation tends to increase due to speeding up and the like. If the amount of heat generation increases, not only will the characteristics of the circuit system change, but also the resin encapsulant will be damaged, such as the occurrence of cracks. Therefore, development is underway to mount a metallic heat dissipation plate having high thermal conductivity on the resin sealing body of the resin sealing type semiconductor device adopting the QFP structure.
【０００６】しかしながら、ＱＦＰ構造を採用する樹脂
封止型半導体装置は、入出力端子数の増加に伴い、外部
リードがファインピッチ化され、外部リード自体の機械
的強度が劣化する傾向にあるにもかかわらず、逆に、樹
脂封止体は放熱板の装着に伴い、樹脂封止体の全体の重
量が増大する傾向にある。このため、ＱＦＰ構造を採用
する樹脂封止型半導体装置を実装基板に実装した場合、
外部リードの機械的強度では樹脂封止体を支えきれず、
適度なクリアランスを確保できないので、樹脂封止体の
下面が実装基板の実装面に接触する。つまり、実装後の
洗浄処理において、実装基板と樹脂封止体との間に残存
するフラックス、半田残渣等の異物が排除できなくなる
ので、樹脂封止型半導体装置の隣接する外部リード間の
短絡、実装基板の端子間や配線間の短絡が誘発される。However, in the resin-sealed semiconductor device adopting the QFP structure, as the number of input / output terminals increases, the external leads have a fine pitch, and the mechanical strength of the external leads themselves tends to deteriorate. In spite of this, conversely, the weight of the resin encapsulant as a whole tends to increase with the mounting of the heat dissipation plate. Therefore, when a resin-sealed semiconductor device adopting the QFP structure is mounted on a mounting board,
The mechanical strength of the external leads cannot support the resin encapsulant,
Since a proper clearance cannot be secured, the lower surface of the resin sealing body contacts the mounting surface of the mounting board. That is, in the cleaning process after mounting, it becomes impossible to remove foreign matters such as flux and solder residue remaining between the mounting substrate and the resin sealing body, so that a short circuit between adjacent external leads of the resin sealing type semiconductor device, A short circuit between terminals of the mounting board or between wirings is induced.
【０００７】本発明の目的は、面実装型構造を採用する
半導体装置において、実装した際に実装基板の実装面と
封止体との間に適度なクリアランスを確保することが可
能な技術を提供することにある。An object of the present invention is to provide a technique capable of ensuring an appropriate clearance between a mounting surface of a mounting substrate and a sealing body when mounted in a semiconductor device adopting a surface mounting type structure. To do.
【０００８】本発明の他の目的は、面実装型構造を採用
する半導体装置において、外部リードの機械的強度を補
強することが可能な技術を提供することにある。Another object of the present invention is to provide a technique capable of reinforcing the mechanical strength of external leads in a semiconductor device adopting a surface mounting type structure.
【０００９】本発明の他の目的は、面実装型構造を採用
する半導体装置において、実装基板の実装後の外部リー
ド間の短絡等を防止することが可能な技術を提供するこ
とにある。Another object of the present invention is to provide a technique capable of preventing a short circuit or the like between external leads after mounting a mounting substrate in a semiconductor device adopting a surface mounting type structure.
【００１０】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面によって明らか
になるであろう。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
【００１１】[0011]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば下
記のとおりである。Among the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
【００１２】半導体ペレットの外部端子に内部リードが
電気的に接続され、前記半導体ペレット及び内部リード
が封止体で封止されるとともに、前記封止体の外部に前
記内部リードに電気的に接続されかつ面実装形状に成型
された外部リードが配列される半導体装置において、実
装の際に実装基板の実装面と対向する、前記封止体の一
表面の一部の領域に、この封止体の前記実装面からの実
装高さを調整するスタンドオフを構成する。Internal leads are electrically connected to the external terminals of the semiconductor pellet, the semiconductor pellet and the internal leads are sealed with a sealing body, and the internal leads are electrically connected to the outside of the sealing body. In a semiconductor device in which external leads molded into a surface mounting shape are arranged, the sealing body is provided in a region of a part of one surface of the sealing body facing the mounting surface of the mounting substrate during mounting. And a standoff for adjusting the mounting height from the mounting surface.
【００１３】[0013]
【作用】上述した手段によれば、以下の作用効果が得ら
れる。 （１）前記半導体装置において、外部リードの機械的強
度に関係なく、封止体の一表面の一部の領域に構成され
たスタンドオフによって、実装した際に封止体の一表面
の他部の領域と実装基板の実装面との間に強制的にクリ
アランス（適度な隙間）を確保できる。 （２）前記作用効果（１）により、前記半導体装置の外
部リードと実装基板の実装面の端子との間を半田で電気
的にかつ機械的に接続し、前記実装基板に半導体装置を
実装した後、前記実装基板の実装面を洗浄した際、前記
実装基板の実装面と半導体装置の封止体の一表面の他部
の領域との間のフラックス、半田残渣などの異物をほぼ
確実に排除できるので、半導体装置の近接外部リード間
の短絡、実装基板の実装面の近接配線間の短絡等を防止
できる。 （３）前記作用効果（１）により、スタンドオフを設け
ることで、外部リードに備える機械的強度を軽減できる
ので、外部リードのファインピッチ化を促進でき、又封
止体に放熱板を備え若しくは電源板を備え、外部リード
に変形を与えないで、封止体の重量を増加できる。According to the above-mentioned means, the following operational effects can be obtained. (1) In the semiconductor device, a standoff formed in a partial region of one surface of the encapsulant irrespective of the mechanical strength of the external leads causes the other part of the one surface of the encapsulant when mounted. It is possible to forcibly secure a clearance (appropriate gap) between the area of (4) and the mounting surface of the mounting board. (2) Due to the action and effect (1), the external leads of the semiconductor device and the terminals on the mounting surface of the mounting substrate are electrically and mechanically connected by soldering, and the semiconductor device is mounted on the mounting substrate. After that, when the mounting surface of the mounting board is washed, foreign substances such as flux and solder residue between the mounting surface of the mounting board and the other area of the one surface of the semiconductor device are almost certainly removed. Therefore, it is possible to prevent a short circuit between the adjacent external leads of the semiconductor device and a short circuit between the adjacent wirings on the mounting surface of the mounting substrate. (3) According to the function and effect (1), by providing the standoff, the mechanical strength of the external leads can be reduced, so that the fine pitch of the external leads can be promoted, and the heat sink is provided in the sealing body. With the power supply plate, the weight of the encapsulant can be increased without deforming the external leads.
【００１４】以下、本発明の構成について、ＱＦＰ構造
を採用する樹脂封止型半導体装置、ＰＧＡ(Ｐin Ｇrid
Ａrray)を採用する半導体装置の夫々に本発明を適用し
た、実施例とともに説明する。The QFP structure of the present invention will be described below.
Resin-sealed semiconductor device that adopts PGA (PinGrid
AThe present invention is applied to each of the semiconductor devices adopting rray).
Also, description will be made with examples.
【００１５】なお、実施例を説明するための全図におい
て、同一機能を有するものは同一符号を付け、その繰り
返しの説明は省略する。In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.
【００１６】[0016]
（実 施 例 １）本実施例１は、ＱＦＰ構造を採用する
樹脂封止型半導体装置に本発明を適用した、本発明の第
１実施例である。(Example 1) Example 1 is a first example of the present invention in which the present invention is applied to a resin-sealed semiconductor device adopting a QFP structure.
【００１７】本発明の実施例１であるＱＦＰ構造を採用
する樹脂封止型半導体装置の構成を図１（要部断面図）
で示す。The configuration of a resin-sealed semiconductor device adopting the QFP structure which is Embodiment 1 of the present invention is shown in FIG.
Indicate.
【００１８】図１に示すように、ＱＦＰ構造を採用する
樹脂封止型半導体装置１は、半導体ペレット２の素子形
成面に配置される外部端子２１、リード５の内部リード
５１の一端の夫々が電気的に接続される。この半導体ペ
レット２及び内部リード５１は樹脂封止体７で封止され
る。前記樹脂封止体７は、平面形状が半導体ペレット２
の平面形状の相似形で形成され、方形状（本実施例にお
いてはほぼ正方形）で構成される。この樹脂封止体７の
方形状の４つの各辺（４つの各側面）の夫々には夫々の
辺に沿って各々複数本の外部リード５２が配列される。
つまり、本実施例のＱＦＰ構造を採用する樹脂封止型半
導体装置１は、４方向リード配列構造で構成され、ガル
ウィング形状で成型された面実装型構造で構成される。
前記外部リード５２は内部リード５１の他端に一体に形
成される（電気的にかつ機械的に接続される）。As shown in FIG. 1, in the resin-sealed semiconductor device 1 employing the QFP structure, the external terminal 21 arranged on the element forming surface of the semiconductor pellet 2 and one end of the internal lead 51 of the lead 5 are respectively. It is electrically connected. The semiconductor pellet 2 and the internal lead 51 are sealed with the resin sealing body 7. The resin sealing body 7 has a semiconductor pellet 2 having a planar shape.
Is formed in a similar shape to the planar shape of the above, and is formed in a square shape (almost square in this embodiment). On each of the four sides (four side faces) of the rectangular shape of the resin sealing body 7, a plurality of external leads 52 are arranged along the respective sides.
That is, the resin-encapsulated semiconductor device 1 adopting the QFP structure of the present embodiment has a four-way lead arrangement structure, and has a surface mounting type structure molded in a gull wing shape.
The outer lead 52 is integrally formed with the other end of the inner lead 51 (electrically and mechanically connected).
【００１９】前記半導体ペレット２は単結晶珪素基板を
主体に構成される。この半導体ペレット２は、樹脂封止
体７に放熱板４を装着するので、素子形成面が図１中下
側表面に配置され、この素子形成面には例えば論理回路
システムが搭載される。半導体ペレット２の外部端子２
１は素子形成面に複数個配置され、この外部端子２１は
回路システムの最上層の結線と同一材料例えばアルミニ
ウム合金又はそれを主層とする積層で構成される。The semiconductor pellet 2 is mainly composed of a single crystal silicon substrate. In this semiconductor pellet 2, since the heat sink 4 is mounted on the resin sealing body 7, the element forming surface is arranged on the lower surface in FIG. 1, and for example, a logic circuit system is mounted on this element forming surface. External terminal 2 of semiconductor pellet 2
A plurality of the elements 1 are arranged on the element forming surface, and the external terminals 21 are made of the same material as the uppermost wiring of the circuit system, for example, an aluminum alloy or a laminated layer having the same as the main layer.
【００２０】前記半導体ペレット２の外部端子２１、内
部リード５１の夫々はワイヤ６を通して電気的に接続さ
れる。ワイヤ６は、例えばＡｕワイヤが使用され、熱圧
着に超音波振動を併用したボンディング法でボンディン
グされる。The external terminal 21 and the internal lead 51 of the semiconductor pellet 2 are electrically connected through the wire 6. As the wire 6, for example, an Au wire is used, and the wire 6 is bonded by a bonding method in which thermocompression is combined with ultrasonic vibration.
【００２１】前記リード５の内部リード５１、外部リー
ド５２の夫々は例えばＦｅ−Ｎｉ合金（例えば、Ｎｉ含
有量は４２又は５０〔％〕）で形成される。このリード
５は例えば０.１〜０.２〔ｍｍ〕程度の板厚で形成され
る。前記リード５の内部リード５１、外部リード５２の
夫々はエッチング加工又は打抜き加工で形成された１枚
のリードフレームから切断されかつ成型される。Each of the inner lead 51 and the outer lead 52 of the lead 5 is formed of, for example, an Fe-Ni alloy (for example, the Ni content is 42 or 50 [%]). The lead 5 is formed with a plate thickness of, for example, about 0.1 to 0.2 [mm]. Each of the inner lead 51 and the outer lead 52 of the lead 5 is cut and molded from one lead frame formed by etching or punching.
【００２２】また、前記リード５は、Ｆｅ−Ｎｉ合金に
変えて、Ｃｕ若しくはＣｕ系合金を使用してもよい。The lead 5 may be made of Cu or a Cu-based alloy instead of the Fe-Ni alloy.
【００２３】前記放熱板４は、樹脂封止体７の内部側と
なる図１中下面に接着層３を介在して半導体ペレット２
を固着し、樹脂封止体７の上部側となる図１中上面が樹
脂封止体７の表面から露出する。放熱板４は半導体ペレ
ット２に搭載された論理回路システムの回路動作で発生
する熱を樹脂封止体７の外部に放出する。放熱板４は熱
伝導率が高い例えばＦｅ−Ｎｉ合金、Ｃｕ、Ｃｕ系合金
のいずれかで形成される。前記接着層３は例えばＡｇペ
ーストが使用される。The heat radiating plate 4 is the semiconductor pellet 2 with the adhesive layer 3 interposed on the lower surface in FIG.
And the upper surface in FIG. 1, which is the upper side of the resin sealing body 7, is exposed from the surface of the resin sealing body 7. The heat radiating plate 4 radiates the heat generated by the circuit operation of the logic circuit system mounted on the semiconductor pellet 2 to the outside of the resin sealing body 7. The heat dissipation plate 4 is formed of, for example, one of Fe—Ni alloy, Cu, and Cu-based alloy having high thermal conductivity. For the adhesive layer 3, for example, Ag paste is used.
【００２４】前記樹脂封止体７は、トランスファモール
ド法で成型され、例えば熱硬化性エポキシ系樹脂が使用
される。熱硬化性エポキシ系樹脂は、通常、フィラー
（酸化珪素粒）、可撓材（例えばシリコーンゴム）等が
添加され、紫外線の吸収、静電気の防止などを目的とし
てカーボン粒も併せて添加される。The resin encapsulant 7 is molded by a transfer molding method and, for example, a thermosetting epoxy resin is used. A filler (silicon oxide particles), a flexible material (for example, silicone rubber) and the like are usually added to the thermosetting epoxy resin, and carbon particles are also added for the purpose of absorbing ultraviolet rays and preventing static electricity.
【００２５】前記樹脂封止体７は、ＱＦＰ構造を採用す
る樹脂封止型半導体装置１の組立プロセスにおいて、放
熱板４に半導体ペレット２を固着するペレットボンディ
ング工程、ワイヤ６をボンディングするワイヤボンディ
ング工程の夫々の後に、トランスファモールド工程によ
り形成される。トランスファモールド工程は、上下両金
型で形成されるキャビティ内に熱硬化性エポキシ系樹脂
を充填し、この熱硬化性エポキシ系樹脂を硬化する工程
である。The resin encapsulation body 7 is a pellet bonding process for fixing the semiconductor pellets 2 to the heat dissipation plate 4 and a wire bonding process for bonding the wires 6 in the assembly process of the resin encapsulation type semiconductor device 1 adopting the QFP structure. After each of the above, a transfer molding process is performed. The transfer molding step is a step of filling a thermosetting epoxy resin in the cavities formed by the upper and lower molds and curing the thermosetting epoxy resin.
【００２６】このＱＦＰ構造を採用する樹脂封止型半導
体装置１は、樹脂封止体７の下面、つまり後述する実装
基板８の実装面と対向する図１中下側の一部の領域にス
タンドオフ（実装高さ調整用突起）７１が構成される。
本実施例において、スタンドオフ７１は、樹脂封止体７
の下面（平面形状は方形状で構成される）であって、４
つの角の夫々の近傍に各々配置され、合計４個配置され
る。このスタンドオフ７１は、樹脂封止体７の下面のほ
んの一部の領域に構成され、樹脂封止体７の下面の大半
を実装時に実装基板８の実装面から離し、樹脂封止体７
と実装基板８との間に適度なクリアランスを確保するこ
とができる。The resin-encapsulated semiconductor device 1 adopting this QFP structure is placed on a lower surface of the resin encapsulation body 7, that is, a part of the lower side in FIG. 1 facing a mounting surface of a mounting substrate 8 described later. The off (mounting height adjusting protrusion) 71 is configured.
In this embodiment, the standoff 71 is the resin sealing body 7.
Of the lower surface (planar shape is rectangular), and
Four corners are arranged in the vicinity of each of the four corners. The standoff 71 is formed in only a part of the lower surface of the resin sealing body 7, and most of the lower surface of the resin sealing body 7 is separated from the mounting surface of the mounting substrate 8 during mounting, and
An appropriate clearance can be secured between the mounting board 8 and the mounting board 8.
【００２７】前記スタンドオフ７１は本実施例において
は樹脂封止体７と一体に構成される（一体に成型され
る）。つまり、スタンドオフ７１は、トランスファモー
ルド工程において、金型のキャビティ内部の形状に若干
の修正を加えるだけで、組立プロセスの変更がなく（組
立プロセスの増加がないので、実質的にはスタンドオフ
７１を形成する工程分、組立プロセス数を減少した状態
で）形成できる。In the present embodiment, the standoff 71 is formed integrally with the resin sealing body 7 (molded integrally). In other words, the standoff 71 does not substantially change the assembly process in the transfer molding process by only slightly modifying the shape inside the cavity of the mold (since there is no increase in the assembly process, the standoff 71 is substantially the same. Can be formed in a state where the number of assembling processes is reduced by the number of steps for forming.
【００２８】なお、前記スタンドオフ７１は、前記樹脂
封止体７の下面であって、４つの辺の夫々の中央部分に
各々配置してもよい。また、スタンドオフ７１は、４個
に限らず、３個、５個若しくはそれ以上の個数を配置し
てもよい。また、スタンドオフ７１は、原則的に樹脂封
止体７を安定に支持することが必要なので、２個の配置
でもよいが、この場合、スタンドオフ７１は、図１中、
紙面に垂直方向に安定な支持を目的として適度な長さを
備える。The standoffs 71 may be arranged on the lower surface of the resin encapsulant 7 at the respective central portions of the four sides. Further, the number of standoffs 71 is not limited to four, and three, five, or more may be arranged. In addition, the standoffs 71 basically need to support the resin sealing body 7 in a stable manner, so that two standoffs may be arranged, but in this case, the standoffs 71 are shown in FIG.
It has an appropriate length for stable support in the direction perpendicular to the paper surface.
【００２９】前記ＱＦＰ構造を採用する樹脂封止型半導
体装置１は、プリント配線基板等の実装基板８に実装さ
れる。この実装は、樹脂封止型半導体装置１の外部リー
ド５２と実装基板８の実装面に配置された端子（図示し
ない）との間を半田で電気的かつ機械的に接続すること
により行われる。The resin-sealed semiconductor device 1 adopting the QFP structure is mounted on a mounting board 8 such as a printed wiring board. This mounting is performed by electrically and mechanically connecting the external lead 52 of the resin-sealed semiconductor device 1 and a terminal (not shown) arranged on the mounting surface of the mounting substrate 8 with solder.
【００３０】このように、半導体ペレット２の外部端子
２１に内部リード５１が電気的に接続され、前記半導体
ペレット２及び内部リード５１が樹脂封止体７で封止さ
れるとともに、前記樹脂封止体７の外部に前記内部リー
ド５１に電気的に接続されかつ面実装形状に成型された
外部リード５２が配列されるＱＦＰ構造を採用する樹脂
封止型半導体装置１において、実装の際に実装基板８の
実装面と対向する、前記樹脂封止体７の一表面の一部の
領域に、この樹脂封止体７の前記実装面からの実装高さ
を調整するスタンドオフ７１を構成する。In this way, the internal lead 51 is electrically connected to the external terminal 21 of the semiconductor pellet 2, the semiconductor pellet 2 and the internal lead 51 are sealed with the resin sealing body 7, and the resin sealing is performed. In the resin-sealed semiconductor device 1 adopting the QFP structure in which the external leads 52 electrically connected to the internal leads 51 and molded in the surface mounting shape are arranged outside the body 7, a mounting substrate at the time of mounting A standoff 71 for adjusting the mounting height of the resin sealing body 7 from the mounting surface is formed in a region of one surface of the resin sealing body 7 that faces the mounting surface of the resin sealing body 7.
【００３１】この構成により、以下の作用効果が得られ
る。（１）前記ＱＦＰ構造を採用する樹脂封止型半導体
装置１において、外部リード５２の機械的強度に関係な
く、樹脂封止体７の一表面の一部の領域に構成されたス
タンドオフ７１によって、実装した際に樹脂封止体７の
一表面の他部の領域と実装基板８の実装面との間に強制
的にクリアランス（適度な隙間）を確保できる。（２）
前記作用効果（１）により、前記ＱＦＰ構造を採用する
樹脂封止型半導体装置１の外部リード５２と実装基板８
の実装面の端子との間を半田で電気的にかつ機械的に接
続し、前記実装基板８に樹脂封止型半導体装置１を実装
した後、前記実装基板８の実装面を洗浄した際、前記実
装基板８の実装面と樹脂封止型半導体装置１の樹脂封止
体７の一表面の他部の領域との間のフラックス、半田残
渣などの異物をほぼ確実に排除できるので、樹脂封止型
半導体装置１の近接外部リード５２間の短絡、実装基板
８の実装面の近接配線間の短絡等を防止できる。（３）
前記作用効果（１）により、スタンドオフ７１を設ける
ことで、外部リード５２に備える機械的強度を軽減でき
るので、外部リード５２のファインピッチ化を促進で
き、又樹脂封止体７に放熱板４を備え（若しくは電源
板）を備え、外部リード５２に変形を与えないで、樹脂
封止体７の重量を増加できる。With this configuration, the following operational effects can be obtained. (1) In the resin-encapsulated semiconductor device 1 that employs the QFP structure, regardless of the mechanical strength of the external lead 52, the standoff 71 formed in a partial region of one surface of the resin encapsulant 7 is used. When mounted, it is possible to forcibly secure a clearance (appropriate gap) between the other surface area of the resin sealing body 7 and the mounting surface of the mounting substrate 8. (2)
Due to the effect (1), the external lead 52 and the mounting substrate 8 of the resin-sealed semiconductor device 1 adopting the QFP structure are provided.
After the resin-sealed semiconductor device 1 is mounted on the mounting board 8 by electrically and mechanically connecting the terminals on the mounting surface of the mounting board 8 with solder, and the mounting surface of the mounting board 8 is washed, Since foreign matter such as flux and solder residue between the mounting surface of the mounting substrate 8 and the other region of the one surface of the resin-sealed body 7 of the resin-sealed semiconductor device 1 can be almost surely removed, the resin-sealed resin is sealed. It is possible to prevent a short circuit between the adjacent external leads 52 of the static semiconductor device 1 and a short circuit between the adjacent wirings on the mounting surface of the mounting substrate 8. (3)
According to the function and effect (1), by providing the standoff 71, the mechanical strength of the external lead 52 can be reduced, so that the fine pitch of the external lead 52 can be promoted, and the heat radiating plate 4 can be attached to the resin sealing body 7. It is possible to increase the weight of the resin encapsulation body 7 by providing the above (or a power supply plate) without deforming the external leads 52.
【００３２】（実 施 例 ２）本実施例２は、前述のＱ
ＦＰ構造を採用する樹脂封止型半導体装置において、ス
タンドオフの変形例を説明する、本発明の第２実施例で
ある。(Embodiment 2) This embodiment 2 is the same as the above-mentioned Q.
It is a second embodiment of the present invention for explaining a modification of the standoff in the resin-sealed semiconductor device adopting the FP structure.
【００３３】本発明の実施例２であるＱＦＰ構造を採用
する樹脂封止型半導体装置の構成を図２（側面図）で示
す。FIG. 2 (side view) shows the structure of a resin-sealed semiconductor device adopting the QFP structure according to the second embodiment of the present invention.
【００３４】本実施例２のＱＦＰ構造を採用する樹脂封
止型半導体装置１は、図２に示すように、樹脂封止体７
の下面の一部の領域に、この樹脂封止体７と異なる材質
で形成されたスタンドオフ９が構成される。このスタン
ドオフ９は、例えば樹脂封止体７と実装基板８との間に
両者の熱膨張係数差に基づき発生する応力を緩和するこ
とを目的として、樹脂封止体７に比べて軟質な材料例え
ばシリコーン樹脂やゴムで形成する。また、このスタン
ドオフ９は、例えば熱放熱板として兼用することを目的
として、金属系材料で形成する。The resin-sealed semiconductor device 1 adopting the QFP structure of the second embodiment has a resin-sealed body 7 as shown in FIG.
A standoff 9 made of a material different from that of the resin sealing body 7 is formed in a part of the lower surface of the. The standoff 9 is made of a softer material than the resin encapsulation body 7 for the purpose of relieving stress generated between the resin encapsulation body 7 and the mounting substrate 8 due to the difference in thermal expansion coefficient between the two. For example, it is formed of silicone resin or rubber. The standoff 9 is made of a metal material for the purpose of also serving as a heat radiating plate.
【００３５】本実施例２であるＱＦＰ構造を採用する樹
脂封止型半導体装置１によれば、基本的に前記実施例１
と同様な効果が得られる。According to the resin-encapsulated semiconductor device 1 adopting the QFP structure according to the second embodiment, basically, the first embodiment described above is used.
The same effect as can be obtained.
【００３６】（実 施 例 ３）本実施例３は、前述のＱ
ＦＰ構造を採用する樹脂封止型半導体装置において、ス
タンドオフの変形例を説明する、本発明の第３実施例で
ある。(Embodiment 3) This embodiment 3 is the same as the above-mentioned Q.
It is a third embodiment of the present invention for explaining a modification of the standoff in the resin-encapsulated semiconductor device adopting the FP structure.
【００３７】本発明の実施例３であるＱＦＰ構造を採用
する樹脂封止型半導体装置の構成を図３（斜視図）で示
す。FIG. 3 (perspective view) shows the structure of a resin-sealed semiconductor device adopting the QFP structure according to the third embodiment of the present invention.
【００３８】本実施例３のＱＦＰ構造を採用する樹脂封
止型半導体装置１は、図３に示すように、樹脂封止体７
の４つの角部に夫々タブ吊りリードを延長し成型するこ
とで形成されたスタンドオフ５３が構成される。The resin-sealed semiconductor device 1 employing the QFP structure of the third embodiment has a resin-sealed body 7 as shown in FIG.
The stand-offs 53 are formed by extending and molding the tab suspension leads at the four corners.
【００３９】本実施例３であるＱＦＰ構造を採用する樹
脂封止型半導体装置１によれば、基本的に前記実施例１
と同様な効果が得られる。According to the resin-encapsulated semiconductor device 1 adopting the QFP structure according to the third embodiment, basically, the first embodiment described above is used.
The same effect as can be obtained.
【００４０】（実 施 例 ４）本実施例４は、ＰＧＡ構
造を採用する半導体装置に本発明を適用した、本発明の
第４実施例である。(Fourth Embodiment) The fourth embodiment is a fourth embodiment of the present invention in which the present invention is applied to a semiconductor device having a PGA structure.
【００４１】本発明の実施例４であるＰＧＡ構造を採用
する半導体装置の構成を図４（側面図）で示す。The configuration of a semiconductor device adopting the PGA structure, which is Embodiment 4 of the present invention, is shown in FIG. 4 (side view).
【００４２】本実施例４のＰＧＡ構造を採用する半導体
装置１０は、図４に示すように、ベース基板１１及び封
止キャップ１２で形成される図示しないキャビティ内に
半導体ペレット２を封止する。前記ベース基板１１は基
本的には樹脂基板、セラミックス基板のいずれであって
もよい。前記ベース基板１１の下面であってその周辺領
域には外部リードとしての外部ピン１５が複数本配列さ
れる。As shown in FIG. 4, the semiconductor device 10 adopting the PGA structure of the fourth embodiment seals the semiconductor pellet 2 in a cavity (not shown) formed by the base substrate 11 and the sealing cap 12. Basically, the base substrate 11 may be either a resin substrate or a ceramic substrate. A plurality of external pins 15 as external leads are arranged on the lower surface of the base substrate 11 and in the peripheral region thereof.
【００４３】このように構成されるＰＧＡ構造を採用す
る半導体装置１０は、外部ピン１５に本来形成されたス
タンドオフ１５１の他に、ベース基板１１の下面の中央
領域にスタンドオフ１７が構成される。この後者のスタ
ンドオフ１７は、実装基板８にＰＧＡ構造を採用する半
導体装置１を安定に支持できる。In the semiconductor device 10 adopting the PGA structure configured as described above, in addition to the standoff 151 originally formed on the external pin 15, the standoff 17 is formed in the central region of the lower surface of the base substrate 11. . The latter standoff 17 can stably support the semiconductor device 1 having the PGA structure on the mounting substrate 8.
【００４４】以上、本発明者によってなされた発明を、
前記実施例に基づき具体的に説明したが、本発明は、前
記実施例に限定されるものではなく、その要旨を逸脱し
ない範囲において種々変更可能であることは勿論であ
る。As described above, the invention made by the present inventor is
Although the specific description has been given based on the above-described embodiments, the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.
【００４５】例えば、本発明は、ＺＩＰ(Ｚig-zag Ｉn-
line Ｐackage)、ＤＩＰ(Ｄuale Ｉn-line Ｐackage)等
のピン挿入型構造を採用する樹脂封止型半導体装置にも
適用できる。For example, according to the present invention, ZIP ( Z ig-zag I n-
line P ackage), it can also be applied to a DIP (D uale I n-line P ackage) resin-sealed semiconductor device which employs a pin insertion type structure or the like.
【００４６】[0046]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
【００４７】面実装型構造を採用する半導体装置におい
て、実装した際に実装基板の実装面と封止体との間に適
度なクリアランスを確保できる。In the semiconductor device adopting the surface mounting type structure, when mounted, an appropriate clearance can be secured between the mounting surface of the mounting substrate and the sealing body.
【００４８】面実装型構造を採用する半導体装置におい
て、外部リードの機械的強度を補強できる。In the semiconductor device adopting the surface mount type structure, the mechanical strength of the external leads can be reinforced.
【００４９】面実装型構造を採用する半導体装置におい
て、実装基板の実装後の外部リード間の短絡等を防止で
きる。In the semiconductor device adopting the surface mounting type structure, it is possible to prevent a short circuit or the like between the external leads after mounting the mounting substrate.
【図１】 本発明の実施例１である樹脂封止型半導体装
置の断面図。FIG. 1 is a cross-sectional view of a resin-sealed semiconductor device that is Embodiment 1 of the present invention.
【図２】 本発明の実施例２である樹脂封止型半導体装
置の側面図。FIG. 2 is a side view of a resin-sealed semiconductor device that is Embodiment 2 of the present invention.
【図３】 本発明の実施例３である樹脂封止型半導体装
置の斜視図。FIG. 3 is a perspective view of a resin-sealed semiconductor device that is Embodiment 3 of the present invention.
【図４】 本発明の実施例４である半導体装置の側面
図。FIG. 4 is a side view of a semiconductor device that is Embodiment 4 of the present invention.
１，１０…半導体装置、２…半導体ペレット、２１…外
部端子、４…放熱板、５…リード、５１，５２，５３…
リード、７…封止体、７１，９，５３，１７…スタンド
オフ、８…実装基板。1, 10 ... Semiconductor device, 2 ... Semiconductor pellet, 21 ... External terminal, 4 ... Heat sink, 5 ... Lead, 51, 52, 53 ...
Leads, 7 ... Sealing body, 71, 9, 53, 17 ... Standoffs, 8 ... Mounting board.
Claims (2)
が電気的に接続され、前記半導体ペレット及び内部リー
ドが封止体で封止されるとともに、前記封止体の外部に
前記内部リードに電気的に接続されかつ面実装形状に成
型された外部リードが配列される半導体装置において、
実装の際に実装基板の実装面と対向する、前記封止体の
一表面の一部の領域に、この封止体の前記実装面からの
実装高さを調整するスタンドオフを構成したことを特徴
とする半導体装置。1. An internal lead is electrically connected to an external terminal of a semiconductor pellet, the semiconductor pellet and the internal lead are sealed with a sealing body, and the internal lead is electrically connected to the outside of the sealing body. In the semiconductor device in which the external leads connected to the
A standoff for adjusting the mounting height of the sealing body from the mounting surface is formed in a part of the one surface of the sealing body that faces the mounting surface of the mounting board during mounting. Characteristic semiconductor device.
は、前記封止体と同一材料でかつ一体に成型されたこと
を特徴とする、又前記封止体と別の材料で構成されかつ
前記封止体の一表面の一部の領域に接着されたことを特
徴とする半導体装置。2. The standoff according to claim 1 is characterized in that it is made of the same material as the sealing body and is integrally molded, and is made of a material different from that of the sealing body. A semiconductor device, wherein the semiconductor device is adhered to a part of a region of one surface of the sealing body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4297153A JPH06151648A (en) | 1992-11-06 | 1992-11-06 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4297153A JPH06151648A (en) | 1992-11-06 | 1992-11-06 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06151648A true JPH06151648A (en) | 1994-05-31 |
Family
ID=17842886
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4297153A Withdrawn JPH06151648A (en) | 1992-11-06 | 1992-11-06 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06151648A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009088352A (en) * | 2007-10-01 | 2009-04-23 | Denso Corp | Production method for electronic circuit device, and electronic circuit device |
| WO2010038717A1 (en) * | 2008-09-30 | 2010-04-08 | パナソニック電工株式会社 | Method for manufacturing functional device, and method for manufacturing semiconductor device provided with functional device |
| JP2010192848A (en) * | 2009-02-20 | 2010-09-02 | Yamaha Corp | Semiconductor package and method of manufacturing the same |
| WO2024070331A1 (en) * | 2022-09-29 | 2024-04-04 | Koa株式会社 | Electronic component |
-
1992
- 1992-11-06 JP JP4297153A patent/JPH06151648A/en not_active Withdrawn
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009088352A (en) * | 2007-10-01 | 2009-04-23 | Denso Corp | Production method for electronic circuit device, and electronic circuit device |
| WO2010038717A1 (en) * | 2008-09-30 | 2010-04-08 | パナソニック電工株式会社 | Method for manufacturing functional device, and method for manufacturing semiconductor device provided with functional device |
| JP2010087280A (en) * | 2008-09-30 | 2010-04-15 | Panasonic Electric Works Co Ltd | Manufacturing method of functional device and manufacturing method of semiconductor device, which uses functional device manufactured by the same |
| JP2010192848A (en) * | 2009-02-20 | 2010-09-02 | Yamaha Corp | Semiconductor package and method of manufacturing the same |
| WO2024070331A1 (en) * | 2022-09-29 | 2024-04-04 | Koa株式会社 | Electronic component |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6861734B2 (en) | Resin-molded semiconductor device | |
| US6177725B1 (en) | Semiconductor device having an improved structure for preventing cracks, improved small-sized semiconductor and method of manufacturing the same | |
| US6630729B2 (en) | Low-profile semiconductor package with strengthening structure | |
| US6553657B2 (en) | Semiconductor device | |
| US20100193922A1 (en) | Semiconductor chip package | |
| JPH09312375A (en) | Lead frame, semiconductor device, and method of manufacturing semiconductor device | |
| US6495908B2 (en) | Multi-chip semiconductor package | |
| JP2000031343A (en) | Semiconductor device | |
| JPH08264569A (en) | Method for manufacturing resin-sealed semiconductor device | |
| JPH06151648A (en) | Semiconductor device | |
| US8105871B2 (en) | Semiconductor device and manufacturing method of the same | |
| US20030038358A1 (en) | Semiconductor package without outer leads | |
| JPH07161910A (en) | Resin-sealed semiconductor device | |
| JPH07312404A (en) | Resin-sealed semiconductor device | |
| JP2000286372A (en) | Manufacture of semiconductor device | |
| JPH08115941A (en) | Semiconductor device | |
| JP2001267484A (en) | Semiconductor device and method of manufacturing the same | |
| JPH06334106A (en) | Resin-sealed semiconductor device | |
| JPH077112A (en) | Resin-sealed semiconductor device | |
| JPH05152495A (en) | Semiconductor device | |
| JPH08306818A (en) | Semiconductor device | |
| JP3015181B2 (en) | Semiconductor device | |
| JPS61240664A (en) | Semiconductor device | |
| JP2963548B2 (en) | Semiconductor device | |
| JPH10303232A (en) | Electric circuit module and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20000201 |