JPH06151728A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Abstract] [Purpose] A power MOSFET for flowing a current from the first main surface side of the semiconductor substrate to the second main surface side, and a control element formed on the first main surface side of the semiconductor substrate. A trench isolation method is easily applied to isolate the. [Structure] An N ⁻ type epitaxial layer 2 is provided on an N ⁺ type substrate 3, and a P type epitaxial layer 1 is further provided thereon to form a semiconductor substrate, and a semiconductor substrate is formed from a first main surface side to a first main surface side. 2, a power MOSFET 38 for flowing a current on the main surface side of the second control element 36 and a control element 36 formed on the first main surface side of the semiconductor substrate,
The first trench 14 a is used for element isolation for isolating the element 37. In addition, the channel region 20 of the MOSFET 38 is formed in the P-type epitaxial layer 1 by the second trench 14
It is formed on the side wall of b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and, more particularly, to an insulated gate field effect transistor (hereinafter referred to as MOSFET) for electric power for flowing a current from a first main surface side to a second main surface side of a semiconductor substrate. , And a control circuit for controlling this MOSFET are provided on the same semiconductor chip (semiconductor substrate).

[0002]

2. Description of the Related Art FIG. 4 shows a cross section of an example of a semiconductor integrated circuit of this type according to the prior art. A P ⁻ type silicon epitaxial layer 25 is formed on the N ⁺ type silicon substrate 3 having a high impurity concentration, and an N ⁺ type buried layer 26 is formed in the P ⁻ type epitaxial layer 25. In addition, an N ⁻ type silicon epitaxial layer 27 is formed on the P ⁻ type epitaxial layer 25.
Is formed, and a P ⁺ type diffusion layer 28 for element isolation is formed penetrating the N ⁻ type epitaxial layer 27. N
By reverse-biasing the ⁻ type epitaxial layer 27 and the P ⁺ type diffusion layer 28, the N ⁻ type epitaxial layer 27 is electrically separated into island-shaped regions 27a, 27b and 27c. In the region 27a of the N ⁻ type epitaxial layer 27, the P ⁺ type collectors 4, P ⁺ , which are connected to the electrodes 17, respectively, are formed.
Type emitter 5 and N ⁺ type base contact portion 6 have N ⁻
A PNP bipolar transistor 36 based on the surface of the mold region 27a is formed as one of the elements of the control circuit for controlling the power MOSFET for electric power. N
^The P well 2 is formed in the region 27b of the ⁻ type epitaxial layer 27.
9 is formed and has an N ⁺ -type collector 8, an N ⁺ -type emitter 9 and a P ⁺ -type base contact 10 respectively connected to the electrode 17, and has an NPN bipolar transistor 37 based on the surface of the P well 29. Is formed as one of the elements of the control circuit for controlling the power MOSFET for electric power. Further, the region 2 of the N ⁻ type epitaxial layer 27 which is connected to the N ⁺ type buried layer 26 and is located thereabove.
7c includes an N ⁺ type source 11 in the P type region 22, a channel region 24 on the surface of the P type region 22, and an N ⁻ type region 27c.
A drain composed of the N ⁺ type buried layer 26 and the N ⁺ type silicon substrate 3, a source electrode 16 connected to the N ⁺ type source 11,
Drain electrode 1 connected to the back surface of the N ^{+ type} silicon substrate 3
5, a power MOSFET for power having a gate insulating film 41 on the channel region 24 and a gate electrode 42 thereon
39 is formed.

[0003] Typically in the power IC of such a configuration P ^-
Since the type epitaxial layer 25 is used as the ground potential and the N ⁻ type region 27c, the N ⁺ type buried layer 26, and the N ⁺ type silicon substrate 3 are used as the positive potential, the PN junction therebetween is reverse biased and the bipolar transistor 36 is used. , 37 and MO
The SFET 39 is electrically isolated.

At this time, the reverse bias breakdown voltage of the P ⁻ N ⁺ junction formed between the P ⁻ type epitaxial layer 25 and the N ⁺ type silicon substrate 3 is determined by the thickness of the P ⁻ type epitaxial layer 25 and the breakdown voltage. Voltage is 60
In the case of V, about 20 μm is required.

On the other hand, the drain breakdown voltage of the MOSFET is N
It depends on the thickness of the ⁻ type epitaxial layer 27, and normally requires a thickness of about 10 μm.

[0006]

In the power IC shown in FIG. 4, the P ⁺ type diffusion layer 28 is formed in order to electrically separate the control transistors 36 and 37 and the power element MOSFET 39. However, this P ⁺ type diffusion layer 28 has a drawback that it requires a large area and requires a long time for its formation.

In order to solve this drawback, it can be considered to use a trench isolation method (groove isolation method) used in a small signal bipolar IC or the like. This method is shown in FIG.
5 that are the same as or similar to those in FIG. 4 are denoted by the same reference numerals, and a duplicate description will be omitted. In FIG. 5, the element isolation region is formed by the trench 30 and the insulator layer 13 filling the inside of the trench 30. But,
When the trench isolation method is applied to the conventional power IC, the N ⁻ type epitaxial layer 27 needs to have a thickness of about 10 μm for the drain withstand voltage of the MOSFET as described above, so that the trench 30 has a thickness of 12 to 15 μm. It must be formed deeply, and the process is complicated and difficult, which is not practical.

[0008]

A feature of the present invention is that a power MOSFET for supplying a current from a first main surface side of a semiconductor substrate to a second main surface side thereof, and a first main surface of the semiconductor substrate. A control element formed on the side for controlling the MOSFET,
In a semiconductor integrated circuit device having an element isolation region for separating the MOSFET and the control element, the semiconductor substrate has a first conductivity type semiconductor substrate and an impurity concentration lower than that of the semiconductor substrate. A first semiconductor layer of the first conductivity type formed on the first semiconductor layer; and a second semiconductor layer of the second conductivity type formed on the first semiconductor layer. The surface opposite to the surface on which the first semiconductor layer is formed is the second main surface of the semiconductor substrate, and the element isolation region penetrates the second semiconductor layer to form the first main surface. A first trench reaching the semiconductor layer, and an insulator layer (dielectric layer) formed on the inner surface of the first trench.
The channel region of T is in the semiconductor integrated circuit device formed in the side wall of the second trench in the second semiconductor layer in the direction perpendicular to the first and second main surfaces of the semiconductor substrate.

Here, the second semiconductor layer of the second conductivity type may be the uppermost semiconductor layer of the semiconductor substrate, and the surface thereof may be the first main surface of the semiconductor substrate. Alternatively, a third semiconductor layer of the first conductivity type having an impurity concentration lower than that of the semiconductor substrate is formed as an uppermost semiconductor layer of a semiconductor substrate on the second semiconductor layer of the second conductivity type, and the third semiconductor layer is formed. Is the first main surface of the semiconductor substrate, and the trench of the element isolation region penetrates the third semiconductor layer and then the second semiconductor layer to reach the first semiconductor layer. Can be

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a semiconductor chip according to the first embodiment of the present invention. 2A to 2E showing the method of manufacturing the semiconductor chip of FIG. 1 in the order of steps will be described at the same time.

First, the N ⁻ type silicon epitaxial layer 2 is formed on the high impurity concentration N ⁺ type silicon substrate 3 to a film thickness of about 10 μm.
to a thickness of about 3 μm to form the semiconductor substrate 50. In the semiconductor substrate 50, the surface of the P-type silicon epitaxial layer 1 is used as the first main surface 51, and the surface of the N ⁺ -type silicon substrate 3 opposite to the surface on which the N ⁻ -type silicon epitaxial layer 2 is formed is the second surface. The main surface 52 of the
The second main surfaces 51 and 52 are flat surfaces that are substantially parallel to each other (FIG. 2 (a)).

Next, the first trench (groove) 14a and the second trench (groove) which penetrate the P-type silicon epitaxial layer 1 and reach the N ^-- type silicon epitaxial layer 2.
14b is formed vertically from the first main surface 51. The first trench 14a is for element isolation, whereby the P-type epitaxial layer 1 is electrically isolated into island-shaped regions 1a, 1b, 1c. The second trench 14b is an island-shaped region 1c
It is formed for the vertical channel gate structure of the MOSFET (FIG. 2B).

Next, the first trench 14a is filled with an insulating film 13 such as silicon dioxide to form an element isolation region. On the other hand, a gate insulating film 21 such as silicon dioxide formed by thermal oxidation is formed on the inner wall of the second trench 14b, and polysilicon is deposited on the gate insulating film 21 so as to fill the trench 14b to form the gate electrode 12. The insulating film 43 is formed on the electrode 12 (FIG. 2C).

Next, by using the photolithography technique, P is formed in the island-shaped region 1a of the P-type epitaxial layer 1.
Forming the N-type base 7 of the NP bipolar transistor,
A P ⁺ type collector 4, a P ⁺ type emitter 5 and an N ⁺ type base contact portion 6 of this transistor are formed therein.
Further, an N-type well 19 is formed in the island-shaped region 1b of the P-type epitaxial layer 1 and a P-type base 18 of an NPN bipolar transistor is formed therein, and the N ⁺ type collector 8 and N ⁺ type of this transistor are formed therein. The emitter 9 and the P ⁺ type base contact portion 10 are formed. Further, the N ⁺ type source 11 of the power power MOSFET is formed on the outer peripheral surface of the trench 14b in the island-shaped region 1c of the P type epitaxial layer 1. Then, an insulating film 33 such as silicon dioxide is deposited on the entire surface (FIG. 2 (d)).

Finally, contact holes are opened in the insulating film 33, the electrodes 17 are connected to the respective impurity regions, and the PNP bipolar transistor 36 controls the power MOSFET for power in the island-shaped region 1a. It is formed as one of the elements of the control circuit, and NP is formed in the island-shaped region 1b.
N bipolar transistor 37 is a power MOS for power
It is formed as one of the elements of the control circuit for controlling the FET.

On the other hand, the source electrode 16 is formed on the N ⁺ type source 11.
And N ⁺ which is the second main surface 52 of the semiconductor substrate 50.
The drain electrode 15 is connected to the back surface of the silicon substrate 3, and the channel region 20 is formed on the side wall of the second trench 14b in the direction perpendicular to the main surface 51 of the semiconductor substrate 50.
The power MOSFET 38 for electric power having a current path between the source electrode 16 on one main surface 51 of the semiconductor substrate and the drain electrode 15 on the other main surface 52 of the semiconductor substrate is an island-shaped region 1c of the P-type silicon epitaxial layer 1. To the N ⁻ -type silicon epitaxial layer 2 and the N ⁺ -type silicon substrate 3 which will be drains (FIG. 2 (d) and FIG. 1).

In FIG. 2, the left half of FIG. 1 is shown for the MOSFET. Since the second trench 14b shown in the cross section of FIG. 1 has a plane shape and a ring shape, the second trenches 14b illustrated on the left and right sides are continuously formed. Therefore, the channel area 2
0, the gate insulating film 21, and the source 11 are formed along the inner circumference and the outer circumference of the ring-shaped second trench 14b having a planar shape.

According to the present invention described above, the P-type silicon epitaxial layer 1 has a thickness such that the channel length of the MOSFET 38 (between the source and the drain in the vertical direction) can be obtained and the bipolar transistors 36 and 37 can be formed. Only about 3 μm is sufficient. Therefore,
The depth of 3 to 4 μm is sufficient for the second trench 14b for element isolation, so that trench isolation can be used for the power IC.

That is, although the drain breakdown voltage of the MOSFET is determined by the film thickness of the N ⁻ type silicon epitaxial layer 2, the trench penetrates the P type silicon epitaxial layer 1 and the N ⁻ type silicon epitaxial layer 2 is formed.
Does not penetrate, the drain breakdown voltage and the depth of the trench are irrelevant.

Further, in the semiconductor integrated circuit device of the present invention, normally, the P-type silicon epitaxial layer 1 is used at the ground potential, and the N ^-- type silicon epitaxial layer 2 and the N ⁺ -type silicon substrate 3 are set at the positive potential. At this time, the breakdown voltage between the P-type silicon epitaxial layer 1 and the N ⁻ -type silicon epitaxial layer 2 is
Similar to the drain breakdown voltage of the FET, it is determined by the film thickness of the N ⁻ type silicon epitaxial layer 2. As described above, in the related art shown in FIGS. 4 and 5, the breakdown voltage is P ^−.
In the present invention, both the breakdown voltage and the drain breakdown voltage are different from the drain breakdown voltage of the MOSFET which depends on the thickness of the N ^- type epitaxial layer 27 and the drain breakdown voltage of the MOSFET. Since it depends on only one N ⁻ type silicon epitaxial layer 2, the N ⁺ type buried layer 26 in the MOSFETs of FIGS. 4 and 5 can be omitted, and the process is further simplified.

Next, FIG. 3 is a sectional view showing a semiconductor chip according to a second embodiment of the present invention. In FIG. 3, parts that are the same as or similar to those in FIGS. 1 and 2 are denoted by the same reference numerals, and a duplicate description will be omitted.

In the second embodiment, an N ⁻ type silicon epitaxial layer 32 is further grown on the P type silicon epitaxial layer 1 to form a semiconductor substrate. The first and second trenches 14a and 14b penetrate the N ⁻ type silicon epitaxial layer 32 and then the P type silicon epitaxial layer 1, and the trench 14a also causes the N ⁻ type silicon epitaxial layer 32 to be an island-shaped region 32a. 32
The elements are separated into b and 32c. In the MOSFET, the N ⁺ type source 11 serving as a source contact portion is formed in the island-shaped region 32c of the N ⁻ type silicon epitaxial layer 32,
The island-shaped region 32c of the N ⁻ type silicon epitaxial layer serves as an N ⁻ type source that is in contact with the channel region 20.

Then, the PNP bipolar transistor 3
6 is a region 32 of the N ⁻ type silicon epitaxial layer 32.
In the NPN bipolar transistor 37, the formation of the N well is omitted and the region 32b of the N ⁻ type silicon epitaxial layer 32 is directly used as the collector to form the N ⁺ type collector buried layer 34 and the N ⁺ type extraction region 35. To do. With such a structure, a high performance bipolar transistor can be obtained.

Although the bipolar transistor has been described as an example of the control element, the control element is not limited to the bipolar transistor, and the present invention can be applied even when a CMOS or a diode is used as the control element. Is applicable. Further, the present invention can be applied even when the polarities of the semiconductors of the examples are reversed, that is, when N type is P type and P type is N type.

[0026]

As described above, according to the present invention, the semiconductor substrate is constructed by having the N ⁻ type epitaxial layer on the N ⁺ type substrate and further having the P type epitaxial layer on it. A power MOSFET for flowing a current from the first main surface side of the semiconductor substrate to the second main surface side and the first of the semiconductor substrate
A trench isolation method can be used in the element isolation region for isolating the control element formed on the main surface side of the. Also, MO
Since the channel region of the SFET is formed in the sidewall of the trench in the P-type epitaxial layer in the direction perpendicular to the first and second main surfaces of the semiconductor substrate, the buried layer can be eliminated and the structure can be simplified. .

[Brief description of drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the method of manufacturing the first embodiment of the present invention in the order of steps.

FIG. 3 is a sectional view showing a second embodiment of the present invention.

FIG. 4 is a cross-sectional view showing an example of a conventional technique.

FIG. 5 is a sectional view showing another example of the prior art.

[Explanation of symbols]

1 P-type silicon epitaxial layer 1a, 1b, 1c Island-shaped region of P-type epitaxial layer 1 2 N ^- type silicon epitaxial layer 3 N ⁺ type silicon substrate 4 P ⁺ type collector of PNP bipolar transistor 5 P ^{+ of} PNP bipolar transistor Type emitter 6 N ⁺ type base contact part of PNP bipolar transistor 7 N type base of PNP bipolar transistor 8 N ⁺ type collector of NPN bipolar transistor 9 N ⁺ type emitter of NPN bipolar transistor 10 P ⁺ type base contact part of NPN bipolar transistor 11 second trench for gate structure of a MOSFET of the N ⁺ -type first trench 14b MOSFET for insulating film 14a isolation of the source 12 within the first trench for gate electrode 13 isolation of MOSFET 5 MOSFET drain electrode 16 MOSFET source electrode 17 Bipolar transistor electrode 18 NPN bipolar transistor P-type base 19 NPN bipolar transistor forming N-type well 20 MOSFET channel region 21 MOSFET gate insulating film 22 P-type region 24 MOSFET Channel region 25 P ⁻ type epitaxial layer 26 N ⁺ type buried layer 27 N ⁻ type silicon epitaxial layer 27a, 27b, 27c N ⁻ type epitaxial layer 2
7 island-shaped region 28 P ⁺ type diffusion layer 29 P well 30 trench 32 N ⁻ type silicon epitaxial layer 32a, 32b, 32c N ⁻ type silicon epitaxial layer 32 island shaped region 33 insulating film on semiconductor substrate 34 N ⁺ Type collector burying layer 35 N ⁺ type extraction region 36 PNP bipolar transistor 37 NPN bipolar transistor 38 MOSFET of the present invention 39 Prior art MOSFET 41 Gate insulating film 42 Gate electrode 43 Insulating film 50 Semiconductor substrate 51 First semiconductor substrate Main surface 52 Second main surface of semiconductor substrate

Claims (9)

[Claims] 1. An insulated gate field effect transistor for electric power for flowing a current from a first main surface side of a semiconductor substrate to a second main surface side, and a first main surface side of the semiconductor substrate,
In a semiconductor integrated circuit device having a control element for controlling the insulated gate field effect transistor and an element isolation region for separating the insulated gate field effect transistor and the control element, the semiconductor substrate is a semiconductor of a first conductivity type. A base, a first semiconductor layer of a first conductivity type having a lower impurity concentration than that of the semiconductor base and formed on the semiconductor base;
And a second semiconductor layer of a second conductivity type formed on the semiconductor layer, the element isolation region penetrating the second semiconductor layer and reaching the first semiconductor layer. A channel region of the insulated gate field effect transistor is formed on a sidewall of the second trench in the second semiconductor layer, the channel region of the insulated gate field effect transistor being formed of the first trench and an insulator layer formed on an inner surface thereof. A semiconductor integrated circuit device characterized by the above. 2. The semiconductor integrated circuit device according to claim 1, wherein the surface of the second semiconductor layer of the second conductivity type is the first main surface of the semiconductor substrate. 3. A source of the first conductivity type of the insulated gate field effect transistor is formed inside the surface of the second semiconductor layer, a source electrode is connected to the surface of the source, and a second electrode of the semiconductor substrate is formed. The drain electrode of the insulated gate field effect transistor is connected to a surface of the first conductive type semiconductor substrate in a direction opposite to the surface on which the first semiconductor layer is formed, which is the main surface of the. The semiconductor integrated circuit device according to claim 2. 4. A well of the first conductivity type is formed in a portion of the second semiconductor layer of the second conductivity type surrounded by the element isolation region, and the control element is formed in the well of the first conductivity type. It is formed, The semiconductor integrated circuit device of Claim 2 or Claim 3 characterized by the above-mentioned. 5. The control device according to claim 1, wherein the control device is a bipolar transistor.
Alternatively, the semiconductor integrated circuit device according to claim 4. 6. A third semiconductor layer of the first conductivity type having an impurity concentration lower than that of the semiconductor substrate is formed on the second semiconductor layer of the second conductivity type, and the surface of the third semiconductor layer is the surface of the third semiconductor layer. The first main surface of the semiconductor substrate, wherein the first trench in the element isolation region penetrates the third semiconductor layer and then the second semiconductor layer to form the first semiconductor layer. 2. The semiconductor integrated circuit device according to claim 1, which has reached. 7. The third semiconductor layer serves as a source of the first conductivity type of the insulated gate field effect transistor, and a source contact region of the first conductivity type having a high impurity concentration is formed on the surface of the source, and the source contact region is formed therein. The source electrode is connected,
A drain electrode of the insulated gate field effect transistor is connected to a surface of the semiconductor substrate of the first conductivity type, which is the second main surface of the semiconductor substrate, in a direction opposite to the surface on which the first semiconductor layer is formed. 7. The semiconductor integrated circuit device according to claim 6, wherein: 8. The control element is formed at a portion of the third semiconductor layer of the first conductivity type surrounded by the element isolation region, and the control element is formed. Semiconductor integrated circuit device. 9. The semiconductor integrated circuit device according to claim 6, wherein the control element is a bipolar transistor.