JPH06151871A - Semiconductor device and manufacture thereof - Google Patents

Abstract

(57) [Summary] [Object] The present invention relates to a nonvolatile semiconductor memory device having a floating gate, which has a good matching with peripheral circuits, a large C ratio, and a small memory cell structure. An object is to provide a semiconductor device. A channel region 11 on a semiconductor substrate 10 of the first conductivity type has two opposing sides defined by a first thick insulating film 18, and the other two opposing sides are defined by a second thick insulating film 26. The first conductive type impurity region 16 is formed below the first thick insulating film 18, the second conductive type impurity region 24 is formed below the second thick insulating film 26, and the floating gate 30 is The control gate 34 is formed so as to cover the channel region 11 and the first and second thick insulating films 18 and 26 around the channel region 11, and the control gate 34 is formed on the floating gate 30 with the insulating film 32 interposed therebetween.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a nonvolatile semiconductor memory device having a floating gate and its manufacturing method.

[0002]

2. Description of the Related Art Nonvolatile semiconductor memories are attracting attention because they are easy to handle because they can retain stored information even when a power supply voltage is not applied. In particular, Flash
h) Since the EEPROM is electrically rewritable, it has attracted a great deal of attention as being replaceable with a conventional hard disk.

The memory cell of the flash EEPROM is
A floating gate is formed on the channel region via an oxide film, and a control gate is formed on the floating gate via an oxide film.
It has the same structure as M. This flash EEPRO
In M, the design of the coupling capacitance value in the memory cell is important for electrically erasing. Particularly, the coupling capacitance between the control gate and the floating gate (C1) and the coupling capacitance between the floating gate and the channel region (C1)
It is important to secure the ratio with 2) (C ratio = C1 / C2) as large as possible.

The C ratio is important because when the voltage V is applied to the control gate and the source / drain from the outside, the voltage Vox applied to the oxide film under the floating gate is expressed as Vox = V / (1 + 1 / C). , The larger the C ratio, the more effectively the external voltage can be applied to the oxide film, and the easier the electrical erasing becomes.

In order to increase the C ratio, the area in which the control gate and the floating gate overlap each other is increased, and the area in which the floating gate and the channel region overlap each other is decreased. However, the area of the channel region is determined by the characteristics of the transistors forming the memory cell, and the size of the floating gate is also determined accordingly, so that it is not easy to secure a large C ratio.

A memory cell structure of a conventional flash EEPROM will be described with reference to FIGS. 26 and 27. The memory cell structure of the flash EEPROM of the first conventional example is shown in FIG.
6 shows. FIG. 26A is a plan view of the memory cell, and FIG.
26B is a sectional view taken along the line XX ′, and FIG. 26C is a sectional view taken along the line YY ′.

A strip-shaped thick oxide film 202 is formed on the p-type silicon substrate 200. This thick oxide film 202 is formed.
Defines the left and right sides of the channel region 204 and separates the channel regions 204 of adjacent memory cells. A gate oxide film 206 is formed on the channel region 204, and an n + -type impurity region 208 is formed below the gate oxide film 202 above and below the channel region 204 in FIG. One of the n + type impurity regions 208 is shown in FIG.
6 (a), the n + -type impurity regions 208 of the memory cells adjacent to each other in the left-right direction form a ground line Vss continuously extending in the left-right direction. The other n + type impurity region 208
Is an n + type impurity region 2 of a memory cell adjacent in the left-right direction.
08 are separated from each other.

The floating gate 212, together with the gate oxide film 206 in the channel region 204, is shown in FIG.
Has a rectangular shape reaching up to the upper left and right thick oxide films 202. A control gate 216 is formed on the floating gate 212 via an interlayer insulating film 214. The control gate 216 is the control gate 21 of the memory cells adjacent in the left-right direction in FIG.
Six of the word lines WL continuously extend in the left-right direction.

On the BPSG film 218 formed on the entire surface, a bit line BL extending in the up-down direction of FIG. 26 (a) orthogonal to the word line WL is formed. Bit line BL
Contacts the n + type impurity regions 208 on the side opposite to the ground line Vss with the channel region 204 interposed therebetween, and connects the n + type impurity regions 208 of vertically adjacent memory cells to each other.

In the first conventional example, between the silicon substrate 200 and the floating gate 212, a gate oxide film 206 is formed in the channel region 204 and a thick oxide film 202 is formed in the left and right regions of the channel region 204. Therefore, the effective coupling capacitance is the channel region 2
04 area and the thickness of the gate oxide film 206.

On the other hand, a thin interlayer insulating film 214 is formed between the floating gate 212 and the control gate 216, and the coupling capacitance thereof is determined by the total area of the floating gate 212 and the thickness of the interlayer insulating film 214. The thickness of the gate oxide film 206 is mainly determined by the transistor characteristics and tunnel characteristics required for the memory cell, and the thickness of the interlayer insulating film 214 is mainly determined by the allowable leak current. Therefore, in order to set the C ratio to an appropriate value, the ratio of the area of the channel region 204 and the area of the floating gate 212 is set to an appropriate value.

In the case of the first conventional example, the area of the floating gate 212 is shown in FIG.
It is extended in the left and right directions of 04, and as shown in FIG.
Area of channel region 204 and floating gate 21
By setting the ratio of the area of 2 to 3: 1 and laying it out, the value of the C ratio is secured. When the pattern design rule is 0.4 μm, the dimensions of each part are, as shown in FIG. 26A, a word line WL pitch of 1.3 μm, a bit line BL pitch of 1.6 μm, and a memory cell area of 2 μm. ．
08 μm ^{2 and} the pitch of the bit lines BL is the word lines W
It is larger than the L pitch.

FIG. 27 shows the memory cell structure of the flash EEPROM of the second conventional example. 27A is a plan view of the memory cell, FIG. 27B is a sectional view taken along line XX ′ of FIG.
7C is a sectional view taken along the line YY '. The second conventional example is
Since the n + -type impurity region buried under the thick oxide film forms a bit line and there is no need to form a bit line contact as in the first conventional example, the area of the memory cell can be reduced. This is a structure that has recently been drawing attention.

A strip-shaped thick oxide film 222 is formed on the p-type silicon substrate 220. This thick oxide film 2 is formed.
The upper and lower sides of a channel region 224 are defined by 22 and the channel regions 214 of adjacent memory cells are separated. A gate oxide film 226 is formed on the channel region 224. In FIG. 27A, the channel region 22
An n + type impurity region 228 is formed below the thick oxide film 222 that defines the upper and lower sides of the No. 4 layer. The n + -type impurity region 228 forms a bit line BL and a ground line Vss that extend continuously in the left-right direction between the n + -type impurity regions 228 of the memory cells adjacent in the left-right direction in FIG. ing.

In FIG. 27A, the channel region 224
Under the gate oxide film 226 on the left and right of the
A + type impurity region 230 is formed. The floating gate 232, together with the gate oxide film 226 in the channel region 224, has a thick oxide film 222 above and below in FIG.
It has a rectangular shape that reaches to the top. A control gate 236 is formed on the floating gate 232 via an interlayer insulating film 234. The control gate 236 constitutes a word line WL continuously extending in the vertical direction between the control gates 236 of the memory cells adjacent to each other in the vertical direction in FIG.

In the case of the second conventional example, the area of the floating gate 232 is extended in the vertical direction of the channel region 224 in FIG. 27A, and as shown in FIG. By setting the area ratio of the floating gate 232 and the floating gate 232 to 3: 1 and laying it out, the value of the C ratio is secured. When the pattern design rule is 0.4 μm, the dimensions of each part are shown in FIG.
And the pitch of the word lines WL is 0.8μ.
m, the bit line BL pitch is 1.6 μm, and the memory cell area is 1.28 μm ² . The pitch of the bit lines BL reaches twice the pitch of the word lines WL. Further, since the bit line BL and the ground line Vss are only separated by the p + -type impurity region 230 under the gate oxide film 226, some problem remains in the separation characteristic.

[0017]

As described above, in the conventional flash EEPROM, even if the area of the memory cell is small, a large C ratio is ensured to form a memory cell structure that can be easily electrically erased. The pitch was larger than the pitch of the word lines WL. Flash EE
In the PROM, it is important to reduce the area of the memory cell itself, but in order to downsize the entire flash EEPROM, the sense amplifier S / A and the decoder DC are required.
It is necessary to consider compatibility with peripheral circuits such as. That is, the sense amplifier S / A is connected to the bit line BL,
Since the decoder DC is connected to the word line WL, the pitch of the bit line BL needs to match the pitch of the sense amplifier S / A, and the pitch of the word line WL matches the pitch of the decoder DC. There is a need.

Generally, when writing / erasing information to / from a memory cell, since a higher voltage is applied to the word line WL than to the bit line BL, it is necessary to use a transistor having a higher breakdown voltage for the decoder DC. The DC pitch is larger than the sense amplifier S / A pitch. On the other hand, in order to realize high-speed operation of the flash EEPROM,
It is important to suppress the delay of the word line WL as much as possible.
Therefore, it is necessary to line the word line WL with a metal wiring to reduce the resistance of the word line WL. For this purpose, it is necessary to have a pattern allowance for forming the metal wiring for backing, and it is desirable that the pitch of the word lines WL is large.

Considering such a situation, the word line W
A memory cell structure in which the L pitch is larger than the bit line BL pitch is desirable. However, in the above-mentioned conventional flash EEPROM, since the pitch of the word lines WL is smaller than the pitch of the bit lines BL in both the first and second conventional examples, as described above, the compatibility with the peripheral circuits and the backing are not provided. There was a problem in forming the metal wiring.

Further, as in the first conventional example, the bit line BL
When the wiring is formed by a metal wiring and the backing of the word line WL is performed by the metal wiring in the upper layer, the pitch of the word line WL is smaller than the pitch of the bit line BL. The pattern rule is stricter in the upper metal wiring for backing than in the wiring.
Since the upper metal wiring has a larger unevenness of the base than the lower metal wiring, considering the depth of focus of the exposure apparatus, the upper metal wiring is disadvantageous in terms of fine processing.
In the conventional example, there is a problem that a stricter pattern rule is required.

Further, in the second conventional example, since the word line WL is formed according to the minimum pattern rule, it is impossible to perform backing with metal wiring. If the word line W
There is a problem that the memory cell area must be increased if the metal wiring for backing is formed on L. An object of the present invention is to provide a memory cell structure which has good compatibility with peripheral circuits, has a large ratio of the coupling capacitance between the control gate and the floating gate and the coupling capacitance between the floating gate and the channel region, and has a small memory cell area. To provide a semiconductor device and a manufacturing method thereof.

[0022]

The above object is to provide a semiconductor substrate of the first conductivity type, a channel region covered with a thin insulating film and defined on the semiconductor substrate, and one of the channel regions facing each other. A first thick insulating film defining a side, a first conductivity type impurity region formed under the first thick insulating film, and a second thick insulating film defining another two opposite sides of the channel region. A film, a second conductivity type impurity region formed under the second thick insulating film, and the thin insulating film on the channel region, and the first and second thick insulating films around the channel region. A semiconductor device having a floating gate formed to cover the film and a control gate formed on the floating gate via an insulating film.

The above-mentioned object is to form a first oxidation resistant film patterned in a strip shape extending in the first direction on a semiconductor substrate of the first conductivity type, and to form the first oxidation resistant film. After introducing an impurity of the second conductivity type into the semiconductor substrate as a mask and then oxidizing the semiconductor substrate with the first oxidation resistant film as a mask, a strip-shaped first thick insulating film is formed, and Forming a second conductivity type impurity region buried under the first thick insulating film, and patterning on the semiconductor substrate into a strip extending in a second direction orthogonal to the first direction. The step of forming a second oxidation resistant film, and the step of introducing the first conductivity type impurity into the semiconductor substrate using the second oxidation resistant film and the first thick insulating film as a mask, The semiconductor substrate using the oxidation resistant film of 2 as a mask To form a second thick insulating film and at the same time form a first conductivity type impurity region buried under the second thick insulating film, and the first thick insulating film and Forming a thin insulating film on a channel region whose periphery is defined by the second thick insulating film; covering the thin insulating film on the channel region; and forming the first and second thin film around the channel region. And forming a floating gate patterned so as to cover the thick insulating film of FIG.

[0024]

According to the present invention, the periphery of the channel region is defined by the first thick insulating film and the second thick insulating film on the semiconductor substrate of the first conductivity type, and the first thick insulating film is formed under the first thick insulating film. A conductive type impurity region is formed, a second conductive type impurity region is formed under the second thick insulating film, and the floating gate is formed so as to cover not only the channel region but also the first and second thick insulating films around the channel region. Since it is formed, it has good compatibility with the peripheral circuits, and has a large ratio of the coupling capacitance between the control gate and the floating gate to the coupling capacitance between the floating gate and the channel region, so that the memory cell structure has a small memory cell structure. The device can be realized.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Flash EE according to the first embodiment of the present invention
The memory cell structure of the PROM will be described with reference to FIG. FIG. 1A is a plan view of the memory cell, and FIG. 1B is XX ′.
FIG. 1C is a sectional view taken along line YY 'of FIG. The channel region 11 on the p-type silicon substrate 10 is surrounded by thick oxide films 18 and 26 to define the region. A gate oxide film 28 is formed on the channel region 11.

In FIG. 1A, an n + type impurity region 16 is formed under the thick oxide film 18 which defines the upper and lower sides of the channel region 11. The n + -type impurity region 16 forms a bit line BL and a ground line Vss that extend continuously in the left-right direction between the n + -type impurity regions 16 of the memory cells adjacent in the left-right direction in FIG. 1A. There is. In FIG. 1A, the thick oxide film 2 that defines the left and right sides of the channel region 11
A p @ + type impurity region 24 is formed under 6. The p + type impurity region 24 separates the channel regions 11 of the adjacent memory cells.

The floating gate 30 has a rectangular shape that covers the gate oxide film 28 in the channel region 11 and the thick oxide films 18 and 26 around the gate oxide film 28. A control gate 34 is formed on the floating gate 30 via an interlayer insulating film 32. The control gate 34 constitutes a word line WL that continuously extends in the vertical direction between the control gates 34 of the memory cells adjacent in the vertical direction in FIG.

In this embodiment, the channel region 11 is surrounded by thick oxide films 18 and 26, and the floating gate 30 is surrounded by the thick oxide film 1 around the channel region 11.
By forming large up, down, left and right so as to reach 8 and 26, the ratio of the area of the floating gate 30 to the area of the channel region 11 is increased to secure the value of the C ratio.

The pattern design rule is 0.4 μm, and the floating gate 3 with respect to the area of the channel region 11 is used.
If the area ratio of 0 is designed to be tripled, the dimensions of each part are as shown in FIG.
Pitch is 1.2 μm, and bit line BL pitch is 1.0
μm, and the area of the memory cell is 1.2 μm ² . 0.16 (= 0.4 × 0.4) μm of the area of the channel region 11
The area of the floating gate 30 is 0.48 with respect to ² .
(= 0.6 × 0.8) μm ² .

According to the present embodiment, the area of the memory cell is slightly smaller than 1.28 ² of the second conventional example, the pitch of the word line WL of the second conventional example 0.8μm Is secured to be 1.5 times larger than the pitch of the bit lines BL to improve the matching with the peripheral circuit. Next, the flash EEPRO according to the first embodiment of the present invention.
A method of manufacturing M will be described with reference to FIGS.
2 to 7, each drawing (a) is a plan view of the memory cell, each drawing (b) is a sectional view taken along line XX ′, and each drawing (c) is Y-.
FIG. 10 is a cross-sectional view taken along the line Y ′, and in FIGS. 8 and 9, each drawing (a) is a cross-sectional view taken along the line XX ′ and each drawing (b) is a cross-sectional view taken along the line YY ′.

First, the surface of the p-type silicon substrate 10 is thermally oxidized to form an oxide film 12 having a thickness of about 10 nm. Then, a nitride film 14 having a thickness of about 100 nm is formed on the entire surface by the CVD method.
Deposit. Then, by photolithography technology,
The nitride film 14 is selectively etched and patterned into a strip shape extending in the left-right direction in FIG. Subsequently, with the nitride film 14 patterned in the shape of a strip as a mask, the acceleration energy is about 40 keV and the dose amount is about 1 × 10 ¹⁵ c.
As is ion-implanted under the condition of m ⁻² . Silicon substrate 10
A band-shaped n + type impurity region 16 is formed on the surface (FIG. 2).

Next, the silicon substrate 10 is oxidized using the nitride film 14 as a mask to form a thick oxide film 18 having a thickness of about 300 nm. The n + type impurity region 16 is buried in the silicon substrate 10 under the thick oxide film 18. Then, the nitride film 1
4 and the oxide film 12 are sequentially removed by etching (FIG. 3). Next, the surface of the silicon substrate 10 is again thermally oxidized to about 10n.
An m-thick oxide film 20 is formed. Then, a nitride film 22 having a thickness of about 100 nm is deposited on the entire surface by the CVD method. Subsequently, the nitride film 22 is selectively etched by a photolithography technique to form a strip shape extending vertically in FIG. 4A orthogonal to the strip pattern of the thick oxide film 18 and the n + -type impurity region 16. Pattern. Then, with the nitride film 22 and the thick oxide film 18 patterned in the form of strips as masks, the acceleration energy is about 15 keV and the dose amount is about 5 keV.
B is ion-implanted under the condition of × 10 ¹³ cm ^-2 . A p + type impurity region 24 is formed on the surface of the silicon substrate 10 (FIG. 4).

Next, the silicon substrate 10 is oxidized using the nitride film 22 as a mask to form a thick oxide film 26 having a thickness of about 300 nm. The p + type impurity region 24 is buried in the silicon substrate 10 under the thick oxide film 26. Then, the nitride film 2
2 and the oxide film 20 are sequentially removed by etching (FIG. 5). Next, the surface of the silicon substrate 10 is again thermally oxidized to about 10n.
A gate oxide film 28 having a thickness of m is formed. Then, a polycrystalline silicon layer 30 having a thickness of about 100 nm is deposited on the entire surface by the CVD method. Then, the polycrystalline silicon layer 30 is formed by a thermal diffusion method.
Introduce P to reduce the resistance. Subsequently, the polycrystalline silicon layer 30 is selectively etched by a photolithography technique to be patterned into a strip extending in the left-right direction in FIG. The width of the strip pattern is the channel region 11
It is slightly thicker (about 0.1 μm) above and below the width. Then, the polycrystalline silicon layer 30 patterned in a strip shape
Is oxidized to form an oxide film 32 having a thickness of about 20 nm (FIG. 6).

Next, a conductive layer 34 is formed by laminating a polycrystalline silicon layer having a thickness of about 50 nm and a tungsten silicide layer having a thickness of about 150 nm on the entire surface by the CVD method. continue,
P is introduced into the polycrystalline silicon layer of the conductive layer 34 by the thermal diffusion method to reduce the resistance. Then, the conductive layer 34, the oxide film 32, and the polycrystalline silicon layer 30 are formed by photolithography.
Is selectively etched and patterned in a strip shape extending in the vertical direction of FIG. The width of the strip pattern is slightly thicker (about 0.2 μm) above and below the width of the channel region 11. As a result, a rectangular floating gate 30 that covers the gate oxide film 28 in the channel region 11 and the thick oxide films 18 and 26 around it, and a control gate 34 are formed on the floating gate 30 with an interlayer insulating film 32 interposed therebetween. . The control gate 34 is shown in FIG.
In FIG. 7A, the control gates 34 of the memory cells adjacent to each other in the vertical direction are continuously arranged to form the word line WL extending in the vertical direction (FIG. 7).

Next, an oxide film (not shown) with a thickness of about 20 nm is formed on the entire surface by thermal oxidation, and then an oxide film (not shown) with a thickness of about 50 nm is grown by the CVD method, and then C
A BPSG film 36 having a thickness of about 500 nm is deposited by the VD method. Then, the BPSG film 36 is reflowed and planarized by heat treatment, and then a contact hole (not shown) reaching the word line WL is opened by a photolithography technique. Subsequently, a tungsten layer 38 having a thickness of about 300 nm is deposited on the entire surface by sputtering. Subsequently, the tungsten layer 38 is patterned using a photolithography technique to form a backing wiring 38 for lowering the resistance of the word line WL in the memory cell region, and a wiring for a peripheral circuit (not shown). Formed (FIG. 8).

Next, about 1 is formed on the entire surface by the plasma CVD method.
An oxide film (not shown) having a thickness of 00 nm is formed, and then T
An oxide film 40 having a flow shape is formed by an atmospheric pressure CVD method using EOS and O ₃ . Then, a via hole reaching the tungsten layer 38 is opened in the oxide film 40 by using the photolithography technique. Then, after depositing an aluminum layer 42 with a thickness of about 1 μm by a sputtering method, the aluminum layer 42 is patterned by using a photolithography technique to form an upper wiring layer (FIG. 9).

In the upper wiring layer, along with the wiring of the peripheral circuit, a selection transistor is provided at the array end of the memory cell in the memory cell region, and half the number of bit lines or ground lines of the n + type impurity region 16 are formed. In this way, the metal wiring of the first layer formed of the tungsten layer 38 is the word line W.
Aluminum layer 4 patterned with the same pitch as L
The second-layer metal wiring formed by 2 is patterned at a pitch double that of the bit line BL. By providing the selection transistor, the pitch of the metal wiring of the second layer is doubled the pitch of the metal wiring of the first layer. Since the second-layer metal wiring is used for forming long-distance wiring and bonding pads, it needs to have a certain thickness or more. Therefore,
If the second-layer metal wiring must be patterned with a fine pitch, it will be patterned with an extremely large aspect ratio, which makes it difficult to manufacture. Flash EEP according to a second embodiment of the present invention
The memory cell structure of the ROM will be described with reference to FIG. FIG. 10A is a plan view of the memory cell, and FIG.
FIG. 10C is a sectional view taken along the line YY ', taken along the line X'.

The channel region 51 on the p-type silicon substrate 50 is surrounded by thick oxide films 58 and 66 to define the region. A gate oxide film 68 is formed on the channel region 51. In FIG. 10A, the thick oxide film 58 that defines the left and right sides of the channel region 51.
A p + type impurity region 56 is formed below. This p
The + type impurity region 56 separates the channel regions 51 of the adjacent memory cells.

In FIG. 10A, an n + type impurity region 64 is formed under the thick oxide film 66 which defines the upper and lower sides of the channel region 51. One n + type impurity region 6
Reference numeral 4 constitutes a ground line Vss continuously extending in the left-right direction between the n + type impurity regions 64 of the memory cells adjacent in the left-right direction in FIG. The floating gate 70, together with the gate oxide film 68 in the channel region 51,
It has a rectangular shape that covers the surrounding thick oxide films 58 and 66. A control gate 74 is formed on the floating gate 70 via an interlayer insulating film 72. The control gate 74 constitutes a word line WL that extends in the left-right direction by continuously connecting the control gates 74 of the memory cells adjacent in the left-right direction in FIG. 10A.

Flattened BPSG on the word line WL
The film 36 is formed. A contact hole 78 reaching the n + type impurity region 64 is formed in the BPSG film 36. On the BPSG film 36, a bit line BL extending in the vertical direction of FIG. 10A and contacting the n + -type impurity region 64 through the contact hole 78 is formed.

In this embodiment, the channel region 51 is surrounded by thick oxide films 58 and 66, and the floating gate 70 is surrounded by the thick oxide film 5 around the channel region 51.
By forming large up, down, left and right so as to reach 8 and 66, the ratio of the area of the floating gate 70 to the area of the channel region 51 is increased to secure the value of C ratio.

The pattern design rule is set to 0.4 μm, and the floating gate 7 with respect to the area of the channel region 51 is formed.
If the area ratio of 0 is designed to be tripled, the dimensions of each part are as shown in FIG.
The L pitch is 1.6 μm, and the bit line BL pitch is 1.
0 μm, the area of the memory cell is 1.6 μm ² . 0.16 (= 0.4 × 0.4) μ of the area of the channel region 51
The area of the floating gate 70 is 0.4 with respect to m ² .
8 (= 0.6 × 0.8) μm ² .

As described above, according to this embodiment, the area of the memory cell is drastically reduced from 2.08 μm ² of the first conventional example, and the pitch of the word lines WL is 1 of the first conventional example. A value sufficiently larger than 0.3 .mu.m is ensured to be larger than the pitch of the bit lines BL to improve the matching with the peripheral circuit. Next, a method of manufacturing the flash EEPROM according to the second embodiment of the present invention will be described with reference to FIGS. 11 to 18, each figure (a)
Is a plan view of the memory cell, each drawing (b) is a sectional view taken along line XX ', and each drawing (c) is a sectional view taken along line YY'.

First, the surface of the p-type silicon substrate 50 is thermally oxidized to form an oxide film 52 having a thickness of about 10 nm. Then, a nitride film 54 having a thickness of about 100 nm is formed on the entire surface by the CVD method.
Deposit. Then, by photolithography technology,
The nitride film 54 is selectively etched and patterned into a well shape shown in FIG. Then, with the nitride film 54 patterned in the shape of a well as a mask, the acceleration energy is about 15 keV and the dose is about 5 × 10 ¹³ cm ^-2.
B is ion-implanted under the condition of. A p + type impurity region 56 is formed on the surface of the silicon substrate 50 (FIG. 11).

Next, the silicon substrate 50 is oxidized using the nitride film 54 as a mask to form a thick oxide film 58 having a thickness of about 200 nm. The p + type impurity region 56 is buried in the silicon substrate 50 under the thick oxide film 58. Then, the nitride film 5
4 and the oxide film 52 are sequentially removed by etching (FIG. 12).
Next, the surface of the silicon substrate 50 is again thermally oxidized to about 10
An oxide film 60 having a thickness of nm is formed. Subsequently, a nitride film 62 having a thickness of about 100 nm is deposited on the entire surface by the CVD method. Subsequently, the nitride film 62 is selectively etched by photolithography to form a strip shape extending in the left-right direction in FIG. 2A orthogonal to the strip pattern of the thick oxide film 58 and the p + -type impurity region 56. Pattern. Subsequently, with the nitride film 62 and the thick oxide film 58 patterned in the strip shape as a mask, the acceleration energy is about 50 keV and the dose amount is about 4
As is ion-implanted under the condition of × 10 ¹⁵ cm ^-2 . An n + type impurity region 64 is formed on the surface of the silicon substrate 50 (FIG. 13).

Next, the silicon substrate 50 is oxidized using the nitride film 62 as a mask to form a thick oxide film 66 having a thickness of about 200 nm. The n + type impurity region 64 is buried in the silicon substrate 50 under the thick oxide film 66. Then, the nitride film 6
2 and the oxide film 60 are sequentially removed by etching (FIG. 14).
Next, the surface of the silicon substrate 50 is again thermally oxidized to about 10
A gate oxide film 68 having a thickness of nm is formed. Then, CVD
A polycrystalline silicon layer 70 having a thickness of about 100 nm on the entire surface by
Deposit. Then, the polycrystalline silicon layer 7 is formed by a thermal diffusion method.
By introducing P into 0, the resistance is lowered. Then, the polycrystal silicon layer 70 is selectively etched by the photolithography technique and patterned into a strip shape extending in the vertical direction of FIG. The width of the strip pattern is slightly thicker (about 0.1 μm) to the left and right than the width of the channel region 51. Subsequently, the strip-shaped patterned polycrystalline silicon layer 70 is oxidized to form an oxide film 72 having a thickness of about 20 nm (FIG. 15).

Next, the entire surface is deposited to about 100 nm by the CVD method.
A conductive layer 74 is formed by laminating a thick polycrystalline silicon layer and a tungsten silicide layer having a thickness of about 200 nm. Then, P is introduced into the polycrystalline silicon layer of the conductive layer 74 by the thermal diffusion method to reduce the resistance. Subsequently, the conductive layer 74, the oxide film 72, and the polycrystalline silicon layer 70 are selectively etched by a photolithography technique, and patterned into a strip shape extending in the left-right direction in FIG. 16A. The width of the strip pattern is slightly smaller (about 0.2 μm) above and below the width of the channel region 51.
Make only m) thicker. As a result, a rectangular floating gate 70 that covers the gate oxide film 68 in the channel region 51 and the thick oxide films 58 and 66 around it, and a control gate 74 are formed on the floating gate 70 via an interlayer insulating film 72. . Control gate 74
Configures a word line WL in which the control gates 74 of the memory cells adjacent in the left-right direction in FIG. 16A are continuously extended in the left-right direction (FIG. 16).

Next, an oxide film (not shown) having a thickness of about 20 nm is formed on the entire surface by thermal oxidation, and then an oxide film (not shown) having a thickness of about 50 nm is grown by the CVD method.
A BPSG film 76 having a thickness of about 500 nm is deposited by the VD method. Then, the BPSG film 76 is reflowed and flattened by heat treatment, and then a contact hole 78 reaching the n + type impurity region 64 is opened by a photolithography technique (FIG. 17).

Next, about 300 n is formed on the entire surface by the sputtering method.
Deposit a m-thick tungsten layer 80. Subsequently, the tungsten layer 80 is patterned by using the photolithography technique to form the bit line BL extending in the vertical direction in FIG. 18A and contacting the n + -type impurity region 64 (FIG. 18). After that, although not shown in the drawing, it is possible to form a wiring for backing the word line WL by an upper wiring layer.

Flash E according to a third embodiment of the present invention
The memory cell structure of the EPROM will be described with reference to FIG. FIG. 19A is a plan view of the memory cell, and FIG.
Is a sectional view taken along the line XX ', and FIG. 19C is a sectional view taken along the line YY'. Channel region 91 on p-type silicon substrate 90
Is surrounded by thick oxide films 98 and 106 to define its region. A gate oxide film 108 is formed on the channel region 91.

In FIG. 19A, an n + -type impurity region 96 and a p + -type impurity region 104 are formed under the thick oxide film 98 that defines the upper and lower sides of the channel region 91.
In the vicinity of the upper and lower sides of the thick oxide film 98, n + type impurity regions 9 are formed.
6 are formed separately, and these n + type impurity regions 96 are electrically separated by the central p + type impurity region 104.

The n + type impurity regions 96 are the n + type impurity regions 96 of the memory cells adjacent to each other in the lateral direction of FIG.
The bit line BL and the ground line Vss which extend continuously in the left-right direction are formed between each other, and the p + -type impurity region 104 is also formed in FIG.
The bit line BL and the ground line Vss, which continuously extend between the p + type impurity regions 104 of the memory cells adjacent to each other in the left-right direction of FIG.

In FIG. 19A, the p + -type impurity region 104 is formed under the thick oxide film 106 that defines the left and right sides of the channel region 91. The p + type impurity region 104 separates the channel regions 91 of the adjacent memory cells. The floating gate 110 has a channel region 9
Along with the first gate oxide film 108, a rectangular shape is formed to cover the surrounding thick oxide films 98 and 106. A control gate 114 is formed on the floating gate 110 via an interlayer insulating film 112. The control gate 114 constitutes a word line WL which continuously extends in the vertical direction between the control gates 114 of the memory cells adjacent in the vertical direction in FIG.

In the present embodiment, the channel region 91 is surrounded by thick oxide films 98 and 106, and the floating gate 110 is formed to be large vertically and horizontally so as to reach the thick oxide films 98 and 106 around the channel region 91. As a result, the ratio of the area of the floating gate 110 to the area of the channel region 91 is increased to secure the value of C ratio. In particular, in the present embodiment, since the thick oxide film 98 has a wide width, the floating gate 110 can be formed to be large in the vertical direction of the channel region 91 above the bit line BL and the ground line Vss.
Ratio can be realized.

If the pattern design rule is designed to be 0.4 μm, the dimensions of each part are as shown in FIG. 19A, the pitch of the word lines WL is 1.2 μm, and the bit lines BL.
Pitch is 1.6 μm, memory cell area is 1.92 μ
It becomes m ² . 0.16 of the area of the channel region 91 (=
The area of the floating gate 110 is 0.96 (= 1.2 × 0.8) μm ^{2, which} is six times as large as 0.4 × 0.4) μm ² .

As described above, according to this embodiment, the area of the memory cell is 1.5 times the 1.28 μm ² of the second conventional example, but the pitch of the word lines WL is 0 of the second conventional example. .8μ
In addition to being 1.5 times m, the floating gate 110 having an area 6 times as large as that of the channel region 91 can be secured, and a large C ratio can be realized. If a large C ratio can be realized, the applied voltage at the time of writing and erasing can be dramatically reduced, and the peripheral circuit can be designed compactly,
As a result, the matching with the peripheral circuit is improved.

Next, a method for manufacturing a flash EEPROM according to the third embodiment of the present invention will be described with reference to FIGS.
Will be explained. Each figure (a) is a plan view of a memory cell,
Each figure (b) is a sectional view taken along line XX ', and each figure (c) is YY'.
It is a line sectional view. First, the surface of the p-type silicon substrate 90 is thermally oxidized to form an oxide film 92 having a thickness of about 10 nm. Then, a nitride film 9 having a thickness of about 100 nm is formed on the entire surface by the CVD method.
4 is deposited. Then, the nitride film 94 is selectively etched by the photolithography technique, and then, as shown in FIG.
Patterning is performed in a strip shape extending in the left-right direction of FIG.
Subsequently, with the nitride film 94 patterned into a strip shape as a mask, the acceleration energy is about 40 keV and the dose amount is about 1
As is ion-implanted under the condition of × 10 ¹⁵ cm ^-2 . A band-shaped n + type impurity region 96 is formed on the surface of the silicon substrate 90 (FIG. 20).

Next, using the nitride film 94 as a mask, silicon is used.
The substrate 90 is oxidized to form a thick oxide film 98 having a thickness of about 300 nm.
Form. The n + type impurity region 96 is formed under the thick oxide film 98.
It is embedded in the silicon substrate 90. Then, the nitride film 9
4 and the oxide film 92 are sequentially removed by etching (FIG. 21).
Next, the surface of the silicon substrate 90 is thermally oxidized again to about 10
An oxide film 100 having a thickness of nm is formed. Then, the CVD method
A nitride film 102 having a thickness of about 100 nm is deposited on the entire surface.
Then, the nitride film 102 is formed by the photolithography technique.
Is selectively etched to remove the thick oxide film 98 and the n + -type
22A orthogonal to the strip-shaped pattern of the pure material region 96.
Rectangular shape that extends in the vertical direction and straddles two strip-shaped patterns
Pattern. Then, it is patterned into a rectangular shape.
Using the nitride film 102 and the thick oxide film 98 as a mask.
Fast energy of about 15 keV and dose of about 5 × 10¹³c
m ^-2B is ion-implanted under the condition of. Silicon substrate 90 table
Area between the rectangular nitride films 102 on the surface and a band-shaped thick oxide film
A p + type impurity region 104 is formed in the region between 98.
(FIG. 22).

Next, the silicon substrate 90 is oxidized using the nitride film 102 as a mask to form a thick oxide film 10 having a thickness of about 300 nm.
6 and 107 are formed. The thick oxide film 107 is formed so as to fill the space between the belt-shaped thick oxide films 98 that have already been formed. The p + -type impurity region 104 has a thick oxide film 106, 1
It is embedded in the silicon substrate 90 below. The thick oxide film 107 is formed between the strip-shaped n + type impurity regions 96. Then, the nitride film 102 and the oxide film 100 are sequentially removed by etching (FIG. 23).

Next, the surface of the silicon substrate 90 is again thermally oxidized to form a gate oxide film 108 having a thickness of about 10 nm.
Then, a polycrystalline silicon layer 110 having a thickness of about 100 nm is deposited on the entire surface by the CVD method. Then, P is introduced into the polycrystalline silicon layer 110 by a thermal diffusion method to reduce the resistance. Subsequently, the polycrystal silicon layer 110 is selectively etched by photolithography, and patterned into a strip shape extending in the left-right direction in FIG. The width of the strip-shaped pattern is large up and down to the width of the thick oxide film 98 (about 0.
4 μm) thicken. Subsequently, the strip-shaped patterned polycrystalline silicon layer 110 is oxidized to form an oxide film 112 having a thickness of about 20 nm (FIG. 24).

Next, a conductive layer 114 is formed by laminating a polycrystalline silicon layer having a thickness of about 50 nm and a tungsten silicide layer having a thickness of about 150 nm on the entire surface by the CVD method. Then, P is applied to the polycrystalline silicon layer of the conductive layer 114 by a thermal diffusion method.
To reduce the resistance. Subsequently, the conductive layer 114, the oxide film 112, and the polycrystalline silicon layer 110 are selectively etched by a photolithography technique, and then, as shown in FIG.
Patterning is performed in a strip shape extending in the vertical direction. The width of the strip pattern is slightly thicker (about 0.2 μm) above and below the width of the channel region 91. As a result, the gate oxide film 108 in the channel region 91 and the surrounding thick oxide films 98, 1
A rectangular floating gate 110 covering 06,
An interlayer insulating film 112 is formed on the floating gate 110.
The control gate 114 is formed via the. The control gate 114 constitutes a word line WL which extends vertically in the control gates 114 of the memory cells adjacent to each other in the vertical direction in FIG. 25A (FIG. 25).

After that, a backing wiring (not shown) for reducing the resistance of the word line WL is formed. The present invention is not limited to the above embodiment, and various modifications can be made. For example, in the above-described embodiment, the impurity is ion-implanted with the nitride film as the mask to form the n + -type impurity region. However, the low-concentration impurity is ion-implanted with the nitride film as the mask to form the sidewall, and then the high concentration The transistor of the memory cell may be a transistor having an LDD structure by ion-implanting impurities of a concentration. Also, using the sidewall,
All the methods used for ordinary memories, such as forming a high-concentration p-type impurity region at the drain end to improve transistor characteristics, can be applied.

[0063]

As described above, according to the present invention, the periphery of the channel region is defined by the first thick insulating film and the second thick insulating film on the semiconductor substrate of the first conductivity type, and the first thick insulating film is formed. The first conductivity type impurity region is formed under the insulating film, the second conductivity type impurity region is formed under the second thick insulating film, and the channel region and the first and second thick insulating films around the channel region are formed. Since the floating gate is formed so as to cover it, the matching with the peripheral circuit is good, and the ratio of the coupling capacitance between the control gate and the floating gate and the coupling capacitance between the floating gate and the channel region is large, which reduces the memory cell area. A semiconductor device having a small memory cell structure can be realized.

[Brief description of drawings]

FIG. 1 is a flash EEP according to a first embodiment of the present invention.
It is a figure which shows ROM.

FIG. 2 is a flash EEP according to a first embodiment of the present invention.
FIG. 6 is a process diagram (1) of a method for manufacturing a ROM.

FIG. 3 is a flash EEP according to a first embodiment of the present invention.
It is process drawing (2) of the manufacturing method of ROM.

FIG. 4 is a flash EEP according to a first embodiment of the present invention.
It is process drawing (the 3) of the manufacturing method of ROM.

FIG. 5 is a flash EEP according to a first embodiment of the present invention.
It is process drawing (4) of the manufacturing method of ROM.

FIG. 6 is a flash EEP according to a first embodiment of the present invention.
It is process drawing (the 5) of the manufacturing method of ROM.

FIG. 7 is a flash EEP according to a first embodiment of the present invention.
It is process drawing (the 6) of the manufacturing method of ROM.

FIG. 8 is a flash EEP according to a first embodiment of the present invention.
It is process drawing (the 7) of the manufacturing method of ROM.

FIG. 9 is a flash EEP according to the first embodiment of the present invention.
It is process drawing (8) of the manufacturing method of ROM.

FIG. 10 shows a flash EE according to a second embodiment of the present invention.
It is a figure which shows PROM.

FIG. 11 shows a flash EE according to a second embodiment of the present invention.
It is a process drawing (1) of the manufacturing method of PROM.

FIG. 12 shows a flash EE according to a second embodiment of the present invention.
It is process drawing (the 2) of the manufacturing method of PROM.

FIG. 13 shows a flash EE according to a second embodiment of the present invention.
It is process drawing (3) of the manufacturing method of PROM.

FIG. 14 shows a flash EE according to a second embodiment of the present invention.
It is process drawing (4) of the manufacturing method of PROM.

FIG. 15 is a flash EE according to a second embodiment of the present invention.
It is process drawing (the 5) of the manufacturing method of PROM.

FIG. 16 shows a flash EE according to the second embodiment of the present invention.
It is process drawing (the 6) of the manufacturing method of PROM.

FIG. 17 is a flash EE according to the second embodiment of the present invention.
It is process drawing (7) of the manufacturing method of PROM.

FIG. 18 is a flash EE according to a second embodiment of the present invention.
It is process drawing (8) of the manufacturing method of PROM.

FIG. 19 shows a flash EE according to a third embodiment of the present invention.
It is a figure which shows PROM.

FIG. 20 shows a flash EE according to a third embodiment of the present invention.
It is a process drawing (1) of the manufacturing method of PROM.

FIG. 21 is a flash EE according to a third embodiment of the present invention.
It is process drawing (the 2) of the manufacturing method of PROM.

FIG. 22 is a flash EE according to the third embodiment of the present invention.
It is process drawing (3) of the manufacturing method of PROM.

FIG. 23 is a flash EE according to a third embodiment of the present invention.
It is process drawing (4) of the manufacturing method of PROM.

FIG. 24 is a flash EE according to the third embodiment of the present invention.
It is process drawing (the 5) of the manufacturing method of PROM.

FIG. 25 shows a flash EE according to a third embodiment of the present invention.
It is process drawing (the 6) of the manufacturing method of PROM.

FIG. 26 is a diagram showing a flash EEPROM of a first conventional example.

FIG. 27 is a diagram showing a flash EEPROM of a second conventional example.

[Explanation of symbols]

 10 ... Silicon substrate 11 ... Channel region 12 ... Oxide film 14 ... Nitride film 16 ... N + type impurity region 18 ... Thick oxide film 20 ... Oxide film 22 ... Nitride film 24 ... P + type impurity region 26 ... Thick oxide film 28 ... Gate oxide film 30 ... Floating gate 32 ... Interlayer insulating film 34 ... Control gate 36 ... BPSG film 38 ... Tungsten layer 40 ... Oxide film 42 ... Aluminum layer 50 ... Silicon substrate 51 ... Channel region 52 ... Oxide film 54 ... Nitride film 56 ... p + type impurity region 58 ... Thick oxide film 60 ... Oxide film 62 ... Nitride film 64 ... N + type impurity region 66 ... Thick oxide film 68 ... Gate oxide film 70 ... Floating gate 72 ... Interlayer insulating film 74 ... Control gate 76 ... BPSG film 78 ... Contact hole 80 ... Tungsten layer 90 ... Silicon substrate 91 ... Channel Region 92 ... Oxide film 94 ... Nitride film 96 ... N + type impurity region 98 ... Thick oxide film 100 ... Oxide film 102 ... Nitride film 104 ... P + type impurity regions 106, 107 ... Thick oxide film 108 ... Gate oxide film 110 ... Floating gate 112 ... Interlayer insulating film 114 ... Control gate 200 ... Silicon substrate 202 ... Thick oxide film 204 ... Channel region 206 ... Gate oxide film 208 ... N + type impurity region 212 ... Floating gate 214 ... Interlayer insulating film 216 ... Control gate 218 BPSG film 220 Silicon substrate 222 Thick oxide film 224 Channel region 226 Gate oxide film 228 n + type impurity region 230 p + type impurity region 232 Floating gate 234 ... Interlayer insulating film 236 Control gate

Claims (6)

[Claims] 1. A semiconductor substrate of a first conductivity type, a channel region defined by a thin insulating film and defined on the semiconductor substrate, and a first thick region defining two opposite sides of the channel region. An insulating film, a first conductivity type impurity region formed under the first thick insulating film, a second thick insulating film that defines the other two opposite sides of the channel region, and the second thick The second conductivity type impurity region formed under the insulating film and the thin insulating film on the channel region are formed to cover the first and second thick insulating films around the channel region. A semiconductor device having a floating gate and a control gate formed on the floating gate via an insulating film. 2. The semiconductor device according to claim 1, wherein the control gate is connected, the word line extending in the first direction is connected to the second conductivity type impurity region, and the word line is connected to the first direction. A bit line extending in a second direction orthogonal to each other, wherein a pitch of the word line is larger than a pitch of the bit line. 3. The semiconductor device according to claim 2, wherein the first direction in which the word line extends is parallel to the two opposite sides of the channel region, and the bit line is The second conductivity type impurity region formed under the second thick insulating film is formed by extending the second conductivity type impurity region under the second thick insulating film in the second direction to be continuous. A semiconductor device characterized by the above. 4. The semiconductor device according to claim 2, wherein the first direction in which the word line extends is parallel to the other two opposite sides of the channel region, and the bit line is Formed across the word line,
A semiconductor device, comprising: a conductive layer that is in contact with a second conductivity type impurity region formed under the second thick insulating film. 5. A step of forming a band-shaped patterned first oxidation resistant film extending in a first direction on a semiconductor substrate of the first conductivity type, and using the first oxidation resistant film as a mask. After introducing a second conductivity type impurity into the semiconductor substrate, the semiconductor substrate is oxidized by using the first oxidation resistant film as a mask to form a strip-shaped first thick insulating film, and Forming a second conductivity type impurity region buried under the first thick insulating film; and a second patterned second region extending in a second direction orthogonal to the first direction on the semiconductor substrate. A step of forming an anti-oxidation film, and using the second anti-oxidation film and the first thick insulating film as a mask to introduce impurities of the first conductivity type into the semiconductor substrate, Oxidize the semiconductor substrate using the oxidation resistant film as a mask To form a second thick insulating film, and to fill the first thick insulating film under the first thick insulating film.
Forming a conductivity type impurity region; forming a thin insulating film on a channel region whose periphery is defined by the first thick insulating film and the second thick insulating film; And a step of forming a floating gate patterned so as to cover the thin insulating film and to cover the first and second thick insulating films around the channel region. 6. A step of forming a band-shaped patterned first oxidation resistant film extending in a first direction on a first conductivity type semiconductor substrate; and using the first oxidation resistant film as a mask. After introducing impurities of the first conductivity type into the semiconductor substrate, the semiconductor substrate is oxidized by using the first oxidation resistant film as a mask to form a band-shaped first thick insulating film, and A step of forming a first conductivity type impurity region buried under a thick insulating film of No. 1, and a second patterned second band extending in a second direction orthogonal to the first direction on the semiconductor substrate. Forming a second conductive type impurity into the semiconductor substrate using the second oxidation resistant film and the first thick insulating film as a mask, Oxidize the semiconductor substrate using the oxidation resistant film as a mask To form a second thick insulating film and to fill the second thick insulating film under the second thick insulating film.
Forming a conductivity type impurity region; forming a thin insulating film on a channel region whose periphery is defined by the first thick insulating film and the second thick insulating film; And a step of forming a floating gate patterned so as to cover the thin insulating film and to cover the first and second thick insulating films around the channel region.