JPH06151901A - Method of combining capacity of variable capacity diode - Google Patents
Method of combining capacity of variable capacity diodeInfo
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- JPH06151901A JPH06151901A JP29474892A JP29474892A JPH06151901A JP H06151901 A JPH06151901 A JP H06151901A JP 29474892 A JP29474892 A JP 29474892A JP 29474892 A JP29474892 A JP 29474892A JP H06151901 A JPH06151901 A JP H06151901A
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- capacitance
- bias
- small
- wafer
- subdivided
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Abstract
(57)【要約】
【目的】 組立、選別、梱包までの一貫した製造工程で
生産された可変容量ダイオードにおける容量の連続性を
向上する。
【構成】 ウェーハプローブにより測定された複数の逆
方向印加電圧点の容量値の内、所定の１バイアスの容量
値を細区分し、細区分された領域毎に他の１バイアスの
容量値が大から小へ又は小から大へと連続的に変化する
ようにウェーハ内のすべてのチップを並べ替える可変容
量ダイオードの容量組合せ方法。また、前記細区分され
た領域毎に容量−電圧カーブを傾きの異なる２つの領域
に分割し、分割された２つの領域の容量変化比を計算
し、その比が大から小へ又は小から大へと連続的に変化
するようにウェーハ内のすべてのチップを並べ替える。
また、前記組区分された領域毎にさらに別のバイアス点
で細区分を繰り返すことにより容量値が連続的に変化す
るようにウェーハ内のすべてのチップを並べ替える。
(57) [Abstract] [Purpose] To improve the continuity of capacitance in a varactor diode produced by a consistent manufacturing process from assembly, selection, and packaging. [Structure] Of the capacitance values of a plurality of reverse applied voltage points measured by a wafer probe, a capacitance value of a predetermined one bias is subdivided, and the capacitance value of the other one bias is large in each subdivided area. A method of capacitance combination of variable capacitance diodes in which all chips in a wafer are rearranged so as to continuously change from small to small or from small to large. Further, the capacitance-voltage curve is divided into two regions having different slopes for each of the subdivided regions, the capacitance change ratio of the two divided regions is calculated, and the ratio is changed from large to small or from small to large. Reorder all the chips in the wafer so that they are continuously changing to.
Further, by repeating the subdivision at each of the regions divided into groups, at another bias point, all the chips in the wafer are rearranged so that the capacitance value changes continuously.
Description
【０００１】[0001]
【産業上の利用分野】本発明は、可変容量ダイオードに
関し、特に、可変容量ダイオードの組立（ペレット付、
ワイヤボンディング、モールド）、選別、梱包までの一
貫した連続連結方式により、容量の連続性が保たれるよ
うに生産する技術に適用して有効な技術に関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable capacitance diode, and more particularly, to an assembly of a variable capacitance diode (with a pellet,
The present invention relates to a technology effectively applied to a technology for producing so as to maintain the continuity of capacity by a continuous continuous connection method including wire bonding, molding, selection, and packaging.
【０００２】[0002]
【従来の技術】ウェーハ内の隣接するチップは容量特性
が近く、かつ特性が全バイアス点で平行に変化している
と仮定して、図８（第１バイアスの容量区分によるチッ
プの組立順番を示す図）に示すように、１バイアス点の
容量を細区分し、容量特性が区分毎に連続的に変化する
ようにウェーハ内のチップを並べ替えることで特性の連
続性を保証している。2. Description of the Related Art Assuming that adjacent chips in a wafer have similar capacitance characteristics and that the characteristics change in parallel at all bias points, the order of assembling chips according to the capacitance division of the first bias is shown in FIG. As shown in the drawing), the capacitance at one bias point is subdivided, and the continuity of the characteristic is guaranteed by rearranging the chips in the wafer so that the capacitance characteristic continuously changes for each division.
【０００３】[0003]
【発明が解決しようとする課題】本発明者は、前記従来
技術を検討した結果、以下の問題点を見い出した。The present inventor has found the following problems as a result of examining the above-mentioned prior art.
【０００４】すなわち、前記従来の方法では、前工程の
製造プロセスの変動により隣合うチップの特性の平行性
が保たれなくなると、他のバイアス点の容量値のバラツ
キがおさえられず、連続性が保証できなくなるという問
題があった。That is, in the above-mentioned conventional method, when the parallelism of the characteristics of the adjacent chips cannot be maintained due to the variation of the manufacturing process of the previous step, the variation in the capacitance value of other bias points is not suppressed and the continuity is maintained. There was a problem that we could not guarantee.
【０００５】本発明の目的は、組立(ペレット付、ワイ
ヤボンディング、モールド)、選別、梱包までの一貫し
た製造工程で生産された可変容量ダイオードにおける容
量の連続性を向上することが可能な技術を提供すること
にある。An object of the present invention is to provide a technique capable of improving the continuity of capacitance in a variable capacitance diode produced by a consistent manufacturing process from assembly (with pellets, wire bonding, molding), selection, and packaging. To provide.
【０００６】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面によって明らか
になるであろう。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
【０００７】[0007]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
下記のとおりである。Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.
【０００８】（１）の手段は、ウェーハプローブにより
測定された複数バイアス（逆方向印加電圧）点の容量値
の内、所定の１バイアスの容量値を細区分し、細区分さ
れた領域毎に他の１バイアスの容量値が大から小へ又は
小から大へと連続的に変化するようにウェーハ内のすべ
てのチップを並べ替える可変容量ダイオードの容量組合
せ方法である。The means (1) subdivides a capacitance value of a predetermined one bias out of the capacitance values of a plurality of bias (reverse applied voltage) points measured by the wafer probe, and for each subdivided area. Another capacitance combination method of variable capacitance diodes is that all chips in a wafer are rearranged so that the capacitance value of one bias is continuously changed from large to small or from small to large.
【０００９】（２）の手段は、ウェーハプローブにより
測定された複数バイアス点の容量値の内、所定の１バイ
アス点の容量値を細区分し、細区分された領域毎に容量
−電圧カーブを傾きの異なる２つの領域に分割し、分割
された２つの領域の容量変化比を計算し、その比が大か
ら小へ又は小から大へと連続的に変化するようにウェー
ハ内のすべてのチップを並べ替える可変容量ダイオード
の容量組合せ方法である。The means of (2) subdivides the capacitance value of a predetermined one bias point among the capacitance values of a plurality of bias points measured by the wafer probe, and obtains a capacitance-voltage curve for each subdivided region. All chips in the wafer are divided into two regions with different slopes, the capacitance change ratio of the divided two regions is calculated, and the ratio changes continuously from large to small or from small to large. Is a method of combining the capacitances of the variable capacitance diodes for rearranging.
【００１０】（３）の手段は、ウェーハプローブにより
測定された複数バイアス点の容量値の内、所定の１バイ
アス点の容量値を細区分し、細区分された領域毎にさら
に別のバイアス点で細区分を繰り返すことにより容量値
が連続的に変化するようにウェーハ内のすべてのチップ
を並べ替える可変容量ダイオードの容量組合せ方法であ
る。The means of (3) subdivides the capacitance value of a predetermined one bias point among the capacitance values of a plurality of bias points measured by the wafer probe, and further subdivides the bias value for each subdivided area. This is a capacitance combination method of variable capacitance diodes in which all the chips in the wafer are rearranged so that the capacitance value changes continuously by repeating the subdivision.
【００１１】[0011]
【作用】上述した（１）の手段によれば、ウェーハプロ
ーブにより測定された複数バイアス(逆方向印加電圧)点
の容量値の内、所定の１バイアスの容量値を細区分し、
細区分された領域毎に他の１バイアスの容量値が大から
小へ又は小から大へと連続的に変化するようにウェーハ
内のすべてのチップを並べ替えることによって、従来１
バイアス点では保証できなかったバイアス点での可変容
量ダイオードの容量の連続性を保証することができる。According to the above-mentioned means (1), the capacitance value of one predetermined bias is subdivided among the capacitance values of a plurality of bias (reverse applied voltage) points measured by the wafer probe,
Conventionally, by rearranging all the chips in the wafer so that the capacitance value of another bias for each subdivided region changes continuously from large to small or from small to large.
It is possible to guarantee the continuity of the capacitance of the variable capacitance diode at the bias point, which cannot be guaranteed at the bias point.
【００１２】（２）の手段によれば、ウェーハプローブ
により測定された複数バイアス点の容量値の内、所定の
１バイアス点の容量値を細区分し、細区分された領域毎
に容量−電圧カーブを傾きの異なる２つの領域に分割
し、分割された２つの領域の容量変化比を計算し、その
比が大から小へ又は小から大へと連続的に変化するよう
にウェーハ内のすべてのチップを並べ替えることによ
り、容量−電圧カーブの傾きを連続的に変化させること
ができるので、全バイアス点の可変容量ダイオードの容
量の連続性を保証することができる。According to the means (2), the capacitance value at a predetermined bias point is subdivided from the capacitance values at a plurality of bias points measured by the wafer probe, and the capacitance-voltage is determined for each subdivided region. Divide the curve into two areas with different slopes, calculate the capacitance change ratios of the two divided areas, and adjust the ratios continuously from large to small or from small to large. By rearranging the chips, the slope of the capacitance-voltage curve can be continuously changed, so that the continuity of the capacitance of the variable capacitance diode at all bias points can be guaranteed.
【００１３】（３）の手段によれば、ウェーハプローブ
により測定された複数バイアス点の容量値の内、所定の
１バイアス点の容量値を細区分し、細区分された領域毎
にさらに別のバイアス点で細区分を繰り返し、容量値が
連続的に変化するようにウェーハ内のすべてのチップを
並べ替えることにより、全バイアス点の可変容量ダイオ
ードの容量特性の連続性の保証が所定の容量バラツキ幅
の範囲で可能となる。According to the means (3), the capacitance value of a predetermined bias point is subdivided from the capacitance values of the plurality of bias points measured by the wafer probe, and the subdivided regions are further divided. By repeating subdivision at the bias point and rearranging all the chips in the wafer so that the capacitance value changes continuously, it is possible to guarantee the continuity of the capacitance characteristics of the variable capacitance diode at all bias points with the prescribed capacitance variation. It is possible within the range of width.
【００１４】以下、本発明の構成について、実施例とと
もに説明する。The structure of the present invention will be described below together with embodiments.
【００１５】なお、実施例を説明するための全図におい
て、同一機能を有するものは同一符号を付け、その繰り
返しの説明は省略する。In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.
【００１６】[0016]
（実施例１）図１は、本発明の可変容量ダイオードの容
量組合せ方法の実施例１の処理手順を示すフローチャー
ト図である。(Embodiment 1) FIG. 1 is a flow chart showing the processing procedure of embodiment 1 of the capacitance combination method for variable capacitance diodes of the present invention.
【００１７】本実施例１の可変容量ダイオードの容量組
合せ方法は、図１に示すように、ウェーハプローブテス
ト〈１０１〉により任意のｎ個のバイアス点の容量デー
タを集積し〈１０２〉、図２に示す容量−電圧特性及び
図３に示す第１バイアス点の容量細区分マップ中の細区
分Ａ，Ｂ，Ｃのように、第１バイアス点Ｖ1 で細区分を
実施する〈１０３〉。次に、細区分Ａ，Ｂ，Ｃ毎に第２
バイアス点Ｖ2 の容量値Ｃ2 が、図４に示す第２バイア
ス点Ｖ2 の容量値に基づく並べ替えのように、細区分Ａ
では小から大(又は小→大)へ、細区分Ｂでは大から小
(又は大→小)へ、細区分Ｃでは小か大(又は小→大)へと
連続的に変化するように並べ替えて〈１０４〉、チップ
の組立順番を示すデータを作成する〈１０５〉。前記図
３において、１はウェーハ、２はチップの組立順番を示
す矢印、Ａ,Ｂ,Ｃは細区分である。As shown in FIG. 1, the variable capacitance diode capacitance combination method of the first embodiment integrates capacitance data of arbitrary n bias points by a wafer probe test <101><102>, and FIG. The subdivision is performed at the first bias point V 1 like the subdivisions A, B, and C in the capacitance-voltage characteristics shown in FIG. 3 and the capacitance subdivision map of the first bias point shown in FIG. 3 <103>. Next, the second for each subdivision A, B, C
Capacitance value C 2 of the bias point V 2 is, as sort based on the capacitance value of the second bias point V 2 shown in FIG. 4, subdivision A
Then from small to large (or small to large), in subdivision B from large to small
(Or large → small), and in subdivision C, rearrange so as to continuously change to small or large (or small → large) <104>, and create data indicating the assembly order of chips <105>. . In FIG. 3, 1 is a wafer, 2 is an arrow indicating the order of assembling chips, and A, B, and C are subdivisions.
【００１８】次に、本発明に係る可変容量ダイオードの
組立、選別、梱包までの一貫した生産工程の概要を簡単
に説明する。Next, the outline of the consistent production process from the assembling, selection and packing of the variable capacitance diode according to the present invention will be briefly described.
【００１９】可変容量ダイオードの組立、選別、梱包ま
での一貫した生産工程は、プローブテスト→データ変換
→ペレットボンディング→ワイヤボンディング→レジン
モールド→切断→選別→テーピング(梱包)の順序で行わ
れる。A consistent production process from the assembly, selection, and packaging of the variable capacitance diode is performed in the order of probe test → data conversion → pellet bonding → wire bonding → resin mold → cutting → selection → taping (packing).
【００２０】以上の説明からわかるように、本実施例１
によれば、細区分ＡとＢ、細区分ＢとＣの間での容量の
不連続部分を低減することができるので、選別時の容量
の不連続性不良の発生が少くなり、図５(選別歩留の推
移を示す図)に示すように、本発明の方法は、従来の方
法に比べて選別歩留が向上する。As can be seen from the above description, the first embodiment
According to FIG. 5, since the capacity discontinuity portion between the subdivisions A and B and the subdivisions B and C can be reduced, the occurrence of capacity discontinuity at the time of sorting is reduced, and FIG. As shown in the graph of transition of selection yield), the method of the present invention improves the selection yield as compared with the conventional method.
【００２１】（実施例２）図６は、本発明の可変容量ダ
イオードの容量組合せ方法の実施例２の処理手順を示す
フローチャート図である。(Embodiment 2) FIG. 6 is a flow chart showing the processing procedure of embodiment 2 of the capacitance combination method for variable capacitance diodes of the present invention.
【００２２】本実施例２の可変容量ダイオードの容量組
合せ方法は、図２に示すように、容量−電圧特性の異な
る２つの領域(イ)と領域(ロ)に分割し〈６０１〉、領域
(イ)では第２バイアス点Ｖ2 ，Ｖ2 ’に対応する容量値
Ｃ2 ，Ｃ2 ’の比ｎ1 を式ｎ1 ＝Ｃ2 ’／Ｃ2 (領域
(イ))を計算し、次に領域(ロ)では第１バイアス点Ｖ
1 ，Ｖ1 ’に対応する容量値Ｃ1 ，Ｃ1 ’の比ｎ2 を式
ｎ2 ＝Ｃ1 ’／Ｃ1（領域（ロ))を計算し、領域(イ)、
領域(ロ)の容量値比ｎ3 を式ｎ3 ＝ｎ2 ／ｎ1 により計
算する〈６０２〉。次に、容量値比ｎ3 の値が小から大
（又は小→大）への連続的に変化するように細区分Ａ，
Ｂ，Ｃ毎に実施し並べ替えることにより、容量−電圧カ
ーブの形が連続的に変わるようにできるので、選別時の
容量の連続性不良の発生を低減することができる〈６０
３〉。As shown in FIG. 2, the capacitance combination method of the variable capacitance diode according to the second embodiment is divided into two regions (a) and (b) having different capacitance-voltage characteristics <601>, and the regions are divided.
In (a), the ratio n 1 of the capacitance values C 2 and C 2 'corresponding to the second bias points V 2 and V 2 ' is calculated by the formula n 1 = C 2 '/ C 2 (region
(B)), and then in the region (b), the first bias point V
The ratio n 2 of the capacitance values C 1 and C 1 ′ corresponding to 1 and V 1 ′ is calculated by the formula n 2 = C 1 ′ / C 1 (region (b)), and the region (b),
The capacitance value ratio n 3 of the region (b) is calculated by the formula n 3 = n 2 / n 1 <602>. Next, the subdivision A, so that the value of the capacity value ratio n 3 continuously changes from small to large (or small to large),
By carrying out and rearranging for each of B and C, the shape of the capacity-voltage curve can be continuously changed, so that occurrence of capacity continuity failure at the time of selection can be reduced <60.
3>.
【００２３】（実施例３）図７は、本発明の可変容量ダ
イオードの容量組合せ方法の実施例３の処理手順を示す
フローチャート図である。(Embodiment 3) FIG. 7 is a flow chart showing the processing procedure of Embodiment 3 of the method of combining the capacitances of the variable capacitance diodes of the present invention.
【００２４】本実施例３の可変容量ダイオードの容量組
合せ方法は、第１バイアス点Ｖ1 の容量を細区分Ａ，
Ｂ，Ｃ（図２及び図３参照）に細区分し〈７０１〉、次
に、細区分Ａを第２バイアス点Ｖ2 の容量を細区分Ａ
1 ，Ａ2 ，Ａ3 ・・・に細区分し〈７０２〉、細区分
Ｂ、細区分Ｃについても同様に細区分Ｂ1 ，Ｂ2 ，Ｂ3
・・・、Ｃ1 ，Ｃ2 ，Ｃ3 ・・・と細区分を実施し〈７
０３〉、(Ａ1 ，Ａ2 ，Ａ3・・・)（Ｂ1 ，Ｂ2 ，Ｂ3
・・・)(Ｃ1 ，Ｃ2 ，Ｃ3 ・・・)と並べ替えを行う
〈７０４〉。このようにすることにより、容量の不連続
点の発生を少くすることができる。In the method of combining the capacitances of the variable capacitance diodes according to the third embodiment, the capacitance at the first bias point V 1 is divided into subdivisions A,
B and C (see FIGS. 2 and 3) are subdivided <701>, and the subdivision A is then subdivided into the capacitance of the second bias point V 2 into subdivisions A.
Subdivision into 1 , A 2 , A 3 ... <702>, and subdivision B, subdivision C similarly subdivisions B 1 , B 2 , B 3
,, C 1 , C 2 , C 3 ... and subdivided <7
03>, (A 1 , A 2 , A 3 ...) (B 1 , B 2 , B 3
...) (C 1 , C 2 , C 3 ...) And rearrangement <704>. By doing so, it is possible to reduce the occurrence of discontinuity points in the capacity.
【００２５】前記実施例１，２，３によれば、従来の１
バイアス点区分方法で発生していた容量の不連続点の発
生を少くすることが可能となり、選別時に発生していた
容量の連続性の発生が少くなるので、選別歩留が図５に
示すように１００％近くまで改善する。これにより原価
を低減することができる。According to the first, second and third embodiments, the conventional 1
Since it is possible to reduce the occurrence of capacity discontinuity that has occurred in the bias point classification method and the occurrence of capacity continuity that occurs during selection, the selection yield is as shown in FIG. Improve to nearly 100%. This can reduce the cost.
【００２６】また、従来の容量特性の連続性の保証値が
３箇連続したダイオードの容量バラツキの保証が３％以
下であったものが５箇連続３％以下となり、連続性を向
上できる。Further, in the conventional diode, the guaranteed value of the continuity of the capacity characteristics is 3% or less continuously, but the guaranteed value of the capacity variation of 3% or less is 5% or less continuously 3% or less, and the continuity can be improved.
【００２７】以上、本発明者によってなされた発明を、
前記実施例に基づき具体的に説明したが、本発明は、前
記実施例に限定されるものではなく、その要旨を逸脱し
ない範囲において種々変更可能であることは勿論であ
る。As described above, the invention made by the present inventor is
Although the specific description has been given based on the above-described embodiments, the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.
【００２８】[0028]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
【００２９】従来の１バイアス点区分方法で発生してい
た容量の不連続点の発生を少くすることが可能となり、
選別時に発生していた容量の連続性の発生が少くなるの
で、選別歩留を向上することができる。It is possible to reduce the occurrence of discontinuity points in the capacitance, which has occurred in the conventional one bias point division method.
Since the occurrence of the continuity of the capacity generated at the time of sorting is reduced, the sorting yield can be improved.
【００３０】また、容量特性の連続性を向上することが
できる。Further, the continuity of capacity characteristics can be improved.
【図１】 本発明の可変容量ダイオードの容量組合せ方
法の実施例１の処理手順を示すフローチャート図、FIG. 1 is a flow chart diagram showing a processing procedure of a first embodiment of a capacitance combination method for variable capacitance diodes according to the present invention;
【図２】 ウェーハの容量−電圧特性を示す図、FIG. 2 is a diagram showing a capacitance-voltage characteristic of a wafer,
【図３】 ウェーハの第１バイアス点の容量細区分マッ
プを示す図、FIG. 3 is a diagram showing a capacity subdivision map of a first bias point of a wafer,
【図４】 ウェーハの第２バイアス点Ｖ2の容量値に基
づく並べ替えを示す図、FIG. 4 is a diagram showing sorting based on a capacitance value of a second bias point V 2 of a wafer,
【図５】 本発明の方法と従来の方法による選別歩留の
推移を示す図、FIG. 5 is a diagram showing the transition of the selection yield according to the method of the present invention and the conventional method;
【図６】 本発明の可変容量ダイオードの容量組合せ方
法の実施例２の処理手順を示すフローチャート図、FIG. 6 is a flow chart diagram showing a processing procedure of a second embodiment of the capacitance combination method for variable capacitance diodes according to the present invention;
【図７】 本発明の可変容量ダイオードの容量組合せ方
法の実施例３の処理手順を示すフローチャート図、FIG. 7 is a flow chart diagram showing a processing procedure of a third embodiment of the capacitance combination method for variable capacitance diodes according to the present invention;
【図８】 従来の第１バイアスの容量区分による組立順
番を示す図。FIG. 8 is a view showing an assembling order according to a conventional first bias capacity division.
１…ウェーハ、２…チップの組立順番を示す矢印、Ａ，
Ｂ，Ｃ…細区分。1 ... Wafer, 2 ... Arrow indicating the assembly order of chips, A,
B, C ... Subdivision.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 西井 也寸志 山梨県中巨摩郡竜王町西八幡 株式会社日 立製作所甲府工場内 (72)発明者 御崎 昭男 東京都青梅市藤橋３丁目３番地２ 日立東 京エレクトロニクス株式会社内 (72)発明者 山田 伸一 山梨県中巨摩郡竜王町西八幡 株式会社日 立製作所甲府工場内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasushi Nishii Nishihachiman, Ryuo-cho, Nakakoma-gun, Yamanashi Inside Kofu Factory, Niitsu Seisakusho Co., Ltd. (72) Akio Misaki 3-3, Fujihashi, Ome-shi, Tokyo Hitachi Tokyo Electronics Co., Ltd. (72) Inventor Shinichi Yamada Nishihachiman, Ryuo-cho, Nakakoma-gun, Yamanashi Pref.
Claims (3)
バイアス（逆方向印加電圧）点の容量値の内、所定の１
バイアスの容量値を細区分し、細区分された領域毎に他
の１バイアス点の容量値が大から小へ又は小から大へと
連続的に変化するようにウェーハ内のすべてのチップを
並べ替えることを特徴とする可変容量ダイオードの容量
組合せ方法。1. A predetermined one of capacitance values at a plurality of bias (reverse applied voltage) points measured by a wafer probe.
Bias capacitance values are subdivided, and all chips in the wafer are arranged so that the capacitance value of the other bias point changes continuously from large to small or from small to large for each subdivided region. A method for combining capacitances of variable capacitance diodes, characterized in that they are replaced.
バイアス点の容量値の内、所定の１バイアス点の容量値
を細区分し、細区分された領域毎に容量−電圧カーブを
傾きの異なる２つの領域に分割し、分割された２つの領
域の容量変化比を計算し、その比が大から小へ又は小か
ら大へと連続的に変化するようにウェーハ内のすべての
チップを並べ替えることを特徴とする可変容量ダイオー
ドの容量組合せ方法。2. A capacitance value at a predetermined one bias point among the capacitance values at a plurality of bias points measured by a wafer probe is subdivided, and two capacitance-voltage curves having different slopes are provided for each subdivided region. Divide into regions, calculate the capacitance change ratio of the two divided regions, and rearrange all chips in the wafer so that the ratio changes continuously from large to small or from small to large. Characteristic variable capacitance diode capacitance combination method.
バイアス点の容量値の内、所定の１バイアス点の容量値
を細区分し、細区分された領域毎にさらに別のバイアス
点で細区分を繰り返すことにより容量値が連続的に変化
するようにウェーハ内のすべてのチップを並べ替えるこ
とを特徴とする可変容量ダイオードの容量組合せ方法。3. A capacitance value of a predetermined one bias point among the capacitance values of a plurality of bias points measured by a wafer probe is subdivided, and subdivision is repeated for each subdivided region at another bias point. A method of capacitance combination of variable capacitance diodes, characterized in that all chips in the wafer are rearranged so that the capacitance value changes continuously.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29474892A JP3436551B2 (en) | 1992-11-04 | 1992-11-04 | Manufacturing method of variable capacitance diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29474892A JP3436551B2 (en) | 1992-11-04 | 1992-11-04 | Manufacturing method of variable capacitance diode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06151901A true JPH06151901A (en) | 1994-05-31 |
| JP3436551B2 JP3436551B2 (en) | 2003-08-11 |
Family
ID=17811799
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29474892A Expired - Fee Related JP3436551B2 (en) | 1992-11-04 | 1992-11-04 | Manufacturing method of variable capacitance diode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3436551B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4849035A (en) * | 1987-08-11 | 1989-07-18 | Crucible Materials Corporation | Rare earth, iron carbon permanent magnet alloys and method for producing the same |
-
1992
- 1992-11-04 JP JP29474892A patent/JP3436551B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4849035A (en) * | 1987-08-11 | 1989-07-18 | Crucible Materials Corporation | Rare earth, iron carbon permanent magnet alloys and method for producing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3436551B2 (en) | 2003-08-11 |
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