JPH06164365A - Single-phase input level converting circuit - Google Patents

Abstract

PURPOSE:To obtain a single-phase level converting circuit which is stable and fast. CONSTITUTION:A 1st driving transistor(TR) mn1 and a 1st load TR mp1 are connected to each other through a mid-point node A, a 2nd driving TR mn2 and a 2nd load TR mp2 are connected in series with each other through an output node B, and an auxiliary TR mp3 is connected to the mid point node A. Then the 1st driving TR mn1 operates in response to a single-phase input clock pulse phi with a low amplitude (VCC) to turn on the 2nd load TR mp2 while suppressing the 2nd driving TR mn2 through the mid-point node A. The auxiliary TR mp3 performs auxiliary operation as the single-phase input clock pulse phi is reset to turn off the 2nd load TR mp2 while resetting the 2nd driving TR mn2 through the mid-point node A, thereby lowering an output clock pulse Q.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level conversion circuit. More specifically, the present invention relates to a single-phase input level conversion circuit incorporated in a thin film transistor integrated circuit device typified by an active matrix liquid crystal display device and used as a clock interface.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram showing an example of a conventional level conversion circuit. As shown, the level conversion circuit 101
Is incorporated in the thin film transistor integrated circuit device 102 and functions as a clock interface. That is,
The input clock signal φ supplied from the external timing generator 103 and its inverted input clock signal (in the figure, a bar is attached on φ to indicate that it is an inverted signal. The same applies hereinafter) are pulse-amplified. The output clock signal Q and its inverted output clock signal are generated and used as the internal clock of the thin film transistor integrated circuit device 102. Generally, the timing generator 103 is composed of, for example, a CMOS gate array, and its power supply voltage VCC is, for example, about 5V. On the other hand, the power supply voltage VDD of the thin film transistor integrated circuit device 102 is, for example, 1
It is 1V-14V. In order to adjust such a difference in power supply voltage, a level conversion circuit 101 as shown is used.

This conventional example has a flip-flop structure in which a pair of N-channel field effect type thin film transistors mn1 and mn2 and a pair of P channel field effect type thin film transistors mp1 and mp2 are connected. The input clock signal φ is applied to the gate of one N-channel transistor mn1.
Is applied, and the inverted input clock signal is applied to the gate of the other N-channel transistor mn2. The pulse-amplified output clock signal Q appears at the midpoint node of the P-channel transistor mp2 and the N-channel transistor mn2, which are connected in series, and the P-channel transistor mp2 and the P-channel transistor mn2 are also connected in series.
An inverted output clock signal is obtained at the midpoint node of the channel transistor mp1 and the N-channel transistor mn1.

FIG. 6 is a waveform diagram showing the operation of the level conversion circuit shown in FIG. Input clock signals having a peak voltage VCC and having opposite phases are supplied to a pair of input terminals of the level conversion circuit 101. One input clock signal φ
Goes high, the N-channel transistor mn1
And the P-channel transistor mp2 is turned on,
An output clock signal Q having a peak voltage VDD is obtained. Similarly, in response to the inverted input clock signal, N-channel transistor mn2 and P-channel transistor m
p1 is turned on and an inverted output clock signal is obtained.

[0005]

In the conventional example shown in FIG. 5, the level conversion circuit is operated by using two-phase input clock signals having polarities opposite to each other. Therefore, a pair of connection terminals is required as the clock interface. As the number of required clocks increases, the number of connection terminals of the clock interface increases, which complicates the wiring work and hinders the compact mounting of the device.

In view of this point, a level conversion circuit which operates by a single-phase input clock signal has been proposed, an example of which is shown in FIG. Basically, it has the same configuration as the two-phase input level conversion circuit shown in FIG. 5, and corresponding parts are designated by corresponding reference numerals to facilitate understanding. The difference is that a fixed DC bias VG is applied to the gate of the drive transistor mn2 instead of the inverted input clock signal.

The operation of the single-phase input level conversion circuit shown in FIG. 7 will be briefly described with reference to FIG. When the input clock signal φ becomes high level, the drive transistor mn1 and the load transistor mp2 are turned on, and the pulse-amplified output clock signal Q rises. Next, when the input clock signal φ becomes low level, the load transistor mp2 is turned off, and the output clock signal Q falls due to the operation of the drive transistor mn2 to which the fixed bias VG is applied. In order to perform such an operation stably, it is necessary to appropriately set the fixed bias VG based on the peak potential of the input clock signal, the threshold voltage of the drive transistor mn2, and the like. However, it is actually extremely difficult to set the fixed bias VG as an internal circuit. Further, even if the fixed bias VG is used as an external input, delicate adjustment is required, which is not practical.

[0008]

SUMMARY OF THE INVENTION In view of the above-mentioned problems of the prior art, it is an object of the present invention to provide a single-phase input level conversion circuit which is practical and capable of stable operation. The following measures were taken to achieve this purpose. That is, the single-phase input level conversion circuit according to the present invention includes the first and second drive elements, the first and second load elements, and the auxiliary element as basic constituent elements. The first drive element and the first load element are connected in series with each other between the ground line and the power supply line via the midpoint node. The second drive element and the second
The load elements are connected in series with each other via the output node between the ground line and the power supply line. The auxiliary element is interposed between the power supply line and the midpoint node. In such a configuration, the first drive element operates in response to a low-amplitude single-phase input clock pulse, suppresses the second drive element via the midpoint node, and turns on the second load element to output the output. Raise a high amplitude output clock pulse to the node.
On the other hand, the auxiliary element performs an auxiliary operation accompanying the release of the single-phase input clock pulse, restores the second drive element via the midpoint node, and cuts off the second load element to raise the output clock pulse. Lower.

According to an aspect of the present invention, each of the above elements is an insulated gate field effect thin film transistor. In this case, the first and second load elements and the auxiliary element are P-channel transistors connected to the positive power supply line side.
The second driving element is composed of an N-channel transistor connected to the ground line side. Alternatively, the first and second load elements and the auxiliary element are N-channel transistors connected to the negative power supply line side, and the first and second driving elements are P-channel transistors connected to the ground line side. May be. The single-phase input level conversion circuit having such a configuration is built in a thin film transistor integrated circuit device represented by, for example, an active matrix type liquid crystal display device, and functions as a clock interface thereof. The element constituting the single-phase input level conversion circuit according to the present invention is not limited to the thin film transistor, and may be a normal insulated gate field effect transistor formed on a bulk silicon wafer. Further, the size of the transistor used as the auxiliary element may be sufficiently smaller than the transistors used in other elements.

[0010]

According to the present invention, the first driving element is switched using the single-phase input clock pulse. An output amplified by controlling the second drive element by forming an effective inverted input clock pulse internally by using the potential appearing at the midpoint node connected to the output terminal of the first drive element. The clock pulse is rising. or,
The auxiliary element is used to control the return of the second drive element via the midpoint node to cause the output clock pulse to fall. Therefore, the level conversion circuit according to the present invention can stably and rapidly amplify the output clock pulse in response to the single-phase input clock pulse.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a circuit diagram showing a first embodiment of a single-phase input level conversion circuit according to the present invention, which is a case where a positive power supply is used. As shown, an N-channel first driving transistor mn is provided between the ground line and the midpoint node A.
1 is connected. This first drive transistor mn1
A single-phase input clock pulse φ having a predetermined pulse potential VCC (for example, 5 V) is applied to the gate of the. A P-channel first load transistor mp1 is connected between the positive power supply line and the midpoint node A. Positive power supply voltage V
DD is set to, for example, 12V. An N-channel type second drive transistor mn2 is connected between the ground line and the output node B. The gate is the midpoint node A
Connected to. A P-channel type second load transistor mp2 is connected between the positive power supply line and the output node B. The gate of this second load transistor is also connected to the midpoint node A. The amplified output clock pulse Q is obtained from the output node B. Finally, a P-channel type auxiliary transistor mp3 is connected between the positive power supply line and the midpoint node A. The aforementioned single-phase input clock pulse φ is applied to the gate of this auxiliary transistor. All of the above-mentioned five transistors are thin film transistors of the insulated gate field effect type. The first driving transistor mn1 operates in response to the low-amplitude single-phase input clock pulse φ and suppresses the second driving transistor mn2 via the midpoint node A, while the second load transistor mp1
By making 2 conductive, a high-amplitude output clock pulse Q is raised at the output node B. Auxiliary transistor mp
3 performs an auxiliary operation with the release of the single-phase input clock pulse φ, and the second drive transistor mn via the midpoint node A.
2 is restored, while the second load transistor mp2 is cut off, the output clock pulse Q falls.

FIG. 2 is a waveform diagram showing a simulation result of the single-phase input level conversion circuit shown in FIG. The operation of the single-phase input level conversion circuit will be described in detail with reference to this waveform diagram. The vertical axis of the waveform chart shows voltage, and the horizontal axis shows time. In this simulation, the amplitude (peak potential VCC) of the input clock pulse φ is set to 5V and the pulse width is set to about 1 μs. The amplitude VDD of the amplified output clock pulse Q is set to 12V. When the input clock pulse φ shifts to the high level, the N-channel first drive transistor mn1 is turned on, and the potential of the midpoint node A drops to the ground line side. At this time, a P-channel type auxiliary transistor mp3
Is applied with a voltage of about VDD-VCC = 12V-5V = 7V, which exceeds the threshold level, so that a small amount of current flows. However, since the size of the auxiliary transistor mp3 is sufficiently smaller than that of the first driving transistor mn1,
The potential of the midpoint node A drops near the ground level. When the potential of the midpoint node A drops to the ground level, the N-channel type second drive transistor mn2 is cut off, while the P-channel type second load transistor mp2 becomes conductive, and the output node B is raised to the power supply line side. So
The output clock pulse Q rises. At this time, the P-channel first load transistor mp1 is turned off. Next, when the input clock pulse φ returns to the low level, the N-channel first drive transistor mn1 is cut off, while the P-channel auxiliary transistor mp1 is cut off.
3 becomes conductive. As a result, a predetermined current flows into the midpoint node A, and its potential quickly rises to the power supply voltage level. Therefore, while the second drive transistor mn2 is switched to the ON state, the second load transistor mp2 is cut off, and the potential of the output node B drops to the ground side,
The output clock pulse Q falls. In this case, a slight delay time occurs between the input clock pulse φ and the output clock pulse Q, but this is a level that causes no practical problems.

FIG. 3 is a circuit diagram showing a second embodiment of the single-phase input level conversion circuit according to the present invention, which uses a negative power supply. P between the ground line and the midpoint node A
The channel-type first drive transistor mp1 is connected. An N-channel first load transistor mn1 and an N-channel auxiliary transistor mn3 are connected between the midpoint node A and the negative power supply line (-VSS).
First drive transistor mp1 and auxiliary transistor mn3
An input clock pulse φ is applied to the gate of the.
Further, a P-channel type second drive transistor mp2 is connected between the ground line and the output node B. The gate of this transistor is the first load transistor mn1.
Is connected to the gate. An N-channel second load transistor mn2 is provided between the output node B and the negative power supply line.
Are connected. The gate of this transistor is connected to the midpoint node A. Then, the amplified output clock pulse Q is obtained at the output terminal B. The operation of this embodiment is similar to that of the embodiment shown in FIG. 1 and will be easily understood.

FIG. 4 is a block diagram showing an application example of the single-phase input level conversion circuit according to the present invention, which is used as a clock interface of an active matrix type liquid crystal display device. As shown in the figure, the active matrix type liquid crystal display device 10 includes liquid crystal pixels LC arranged in a matrix and thin film transistors TFT for driving the individual liquid crystal pixels LC. An additional capacitance CS is connected in parallel to both ends of the liquid crystal pixel LC. The gate of the TFT is connected to the gate line 11, the source is connected to the signal line 12, and the drain is connected to the pixel electrode located at one end of the corresponding liquid crystal pixel LC. The other end of the liquid crystal pixel LC is connected to the common electrode COM in common. A vertical shift register 13 is connected to the plurality of gate lines 11. A common data line 14 is connected to each of the plurality of signal lines 12 via a switching element SW. The image signal Vsig is supplied to the data line 14. Each switching element SW is connected to the horizontal shift register 16 via the gate circuit 15.

The vertical shift register 13 selects the gate line 11 line by line. The TFT becomes conductive along the selected gate line 11. On the other hand, the horizontal shift register 16
Sequentially turns on the switching element SW through the gate circuit 15, and the image signal Vsig through the data line 14.
Are sampled and distributed to each signal line 12. The sampled image signal Vsig is written in the corresponding liquid crystal pixel LC via the TFT in the conductive state, and image display is performed. When the gate line 11 is deselected,
The TFT becomes non-conductive, and the image signal written in the liquid crystal pixel LC is held until the next selection timing.

The vertical shift register 13 is activated in response to the vertical start pulse VST, sequentially transfers the vertical start pulse VST in synchronization with a pair of vertical clock pulses VCK1 and VCK2 having opposite phases, and the gate line 12 is line-sequentially. Select with. Similarly, the horizontal shift register 16 is activated in response to the horizontal start pulse HST, sequentially transfers the horizontal start pulse HST in synchronization with a pair of mutually opposite-phase horizontal clock pulses HCK1 and HCK2, and drives the switching element SW. The vertical start pulse VST and the pair of vertical clock pulses VCK1 and VCK described above.
2. The horizontal start pulse HST and the pair of horizontal clock pulses HCK1 and HCK2 are internally generated by the corresponding single-phase input level conversion circuits 21 to 24, respectively. According to the present invention, since the single-phase input level conversion circuits 21 to 24 are used as the clock interface, the number of connection terminals is only 4, which is half that of the conventional one. When the single-phase input level conversion circuits 22 and 24 form clock pulses having mutually opposite phases, an inverter may be inserted internally. These four single-phase input level conversion circuits 2
1 to 24 are supplied with appropriate input clock pulses φ1 to φ4 from the timing generator 30, respectively. The number of output terminals of the timing generator 30 can be halved compared to the conventional one.

[0017]

As described above, according to the present invention, single-phase input can be realized by a simple structure in which an auxiliary element is added to the conventional two-phase input level conversion circuit, and stable and high-speed pulse amplification is possible. Is effective. By using the single-phase input level conversion circuit having such a configuration, it is possible to easily realize level conversion of a single-phase signal such as a start pulse of a shift register.
In addition, by using the single-phase input level conversion circuit as the clock interface, it is possible to reduce the number of connection terminals as compared with the conventional case.

[Brief description of drawings]

FIG. 1 is a first single-phase input level conversion circuit according to the present invention.
It is a circuit diagram which shows an Example.

FIG. 2 is a waveform diagram showing a simulation result of the first embodiment shown in FIG.

FIG. 3 is a second single-phase input level conversion circuit according to the present invention.
It is a circuit diagram which shows an Example.

FIG. 4 is a block diagram showing an application example of a single-phase input level conversion circuit according to the present invention.

FIG. 5 is a circuit diagram showing a conventional two-phase input level conversion circuit.

6 is an operation waveform diagram of the conventional example shown in FIG.

FIG. 7 is a circuit diagram showing a conventional single-phase input level conversion circuit.

8 is an operation waveform diagram of the conventional example shown in FIG.

[Explanation of symbols]

 mn1 first drive transistor mn2 second drive transistor mp1 first load transistor mp2 second load transistor mp3 auxiliary transistor φ input clock pulse Q output clock pulse A midpoint node B output node

Claims (5)

[Claims] 1. A first drive element and a first load element connected in series with each other through a midpoint node, a second drive element and a second load element connected in series with each other through an output node, and A single-phase input level conversion circuit having an auxiliary element connected to a point node, wherein the first driving element operates in response to a low-amplitude single-phase input clock pulse, By suppressing the second driving element and turning on the second load element, a high-amplitude output clock pulse is raised to the output node, and the auxiliary element performs an auxiliary operation accompanying release of the single-phase input clock pulse. A single-phase input level conversion circuit that causes the output clock pulse to fall by shutting off the second load element while restoring the second drive element via the midpoint node. 2. The single-phase input level conversion circuit according to claim 1, wherein each of the elements is an insulated gate field effect thin film transistor. 3. The first and second load elements and the auxiliary element are P-channel transistors connected to the positive power supply line side, and the first and second driving elements are N-channel transistors connected to the ground line side. The single-phase input level conversion circuit according to claim 2. 4. The first and second load elements and the auxiliary element are N-channel transistors connected to the negative power supply line side, and the first and second driving elements are P-channel transistors connected to the ground line side. The single-phase input level conversion circuit according to claim 2. 5. The single-phase input level conversion circuit according to claim 2, which is built in a thin film transistor integrated circuit device and functions as a clock interface thereof.