JPH06165039A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To provide the solid-state image pickup device suitable for high-speed image pickup. CONSTITUTION:Electric charges outputted from vertical transfer shift registers 20 are inputted to first electrodes at the respective bits of horizontal transfer shift registers 30-32, and charge/voltage converting amplifiers 41-42 are reset at the same time. With the next clock, electric charges are transferred from the first electrodes to second electrodes at the respective bits of horizontal transfer shift registers 30-32. In this case, the charges of final bits are transferred to the charge/voltage converting amplifiers 41-42 and converted to voltages.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device such as a CCD image sensor.

[0002]

2. Description of the Related Art FIG. 5 shows a conventional FFT method n-channel CC.
The structure of the D image sensor 100 is shown. Light receiving regions for performing photoelectric conversion are arranged in a matrix above the CCD image sensor 100, and the vertical transfer shift register 10 for serially transferring the signal charges generated in the respective light receiving regions.
Have one. In addition, the vertical transfer shift register 101
The horizontal transfer shift register 102 that inputs in parallel the signal charges output from the horizontal transfer shift register 102 and the charge-voltage conversion amplifier that converts the signal charges output from the horizontal transfer shift register 102 into a voltage, such as an FDA (floating diffusion amplifier). ) 103.

A parallel output type CCD image sensor improved from the CCD image sensor 100 is disclosed in Japanese Patent Laid-Open No. 3-22.
4371.

FIG. 6 shows a block diagram of the parallel output CCD image sensor 110. CCD image sensor 10
Although the basic configuration is the same as that of 0, the parallel output CCD image sensor 110 includes a plurality of output units 120 to 150, so that it is possible to divide and output all pixel signals by the number of output units. In this example, 1/4 of all pixels may be output from each output unit. Therefore, the parallel output CCD image sensor 110 can capture images at a higher speed than the CCD image sensor 100. For example, when reading is performed at a data rate of 10 MHz in an image sensor of 100,000 pixels, the CCD image sensor 100 has a limit of capturing 100 frames (100 frames / sec) per second. However, in the parallel output CCD image sensor 110 having the four output sections 120 to 150, it is sufficient to read out 25,000 pixels from each output section.
High-speed imaging of 0 frame / second is possible. If the number of output units is increased, it is possible to perform higher speed imaging.

FIG. 7 is a top structural view of the output section 120 of the parallel output CCD image sensor 110, and FIG. 8 is CC ′.
10 is a sectional structural view of the surface, FIG. 9 is an operation timing diagram, and FIG.
The potential diagrams of the AA ′ plane and the BB ′ plane are shown in FIG. C
The CD image sensor 110 includes a vertical transfer shift register 121 and a horizontal transfer shift register 122. Each register has a plurality of transfer electrodes 121a and 121a.
, 122a, 122b, ... are arranged side by side, and two adjacent transfer electrodes form one bit. The FDA 123 is provided at the output end of the horizontal transfer shift register 122.
Are arranged.

As shown in the sectional structure view of FIG.
23 is an OG (output gate) to which a proper bias is applied
123a, FD (floating diffusion) 123b which is in a floating state but whose potential changes due to inflow of signal charges, and RG (reset for resetting FD 123b to the potential of RD (reset drain) 123c. Gate) 123d. The potential change of the FD123b is caused by the source follower MOSF.
The impedance is converted by the ET 124 and output. The dotted line portion 125 indicates that the wiring is actually made of aluminum although it cannot be displayed on the sectional view.

Next, the operation timing chart of FIG. 9 and FIG.
CCD image sensor 11 using the potential diagram of
The operation of 0 will be described.

At time t1, the horizontal transfer shift register 1
The signal charge DL2 stored under the transfer electrode 122a of No. 22
Is transferred to the FDA 123 and converted into a voltage.

At time t2, a high level (H) voltage is applied to the RG 123d and the FDA 123 is reset. In addition, the transfer electrode 12 of the vertical transfer shift register 121
The signal charge DF2 stored under 1b is transferred to the transfer electrode 121a.
The signal charges DL1 stored in the horizontal transfer shift register 122 and below the transfer electrode 122b of the horizontal transfer shift register 122 are moved downward.
Move 2a down.

At time t3, a low level (L) voltage is applied to the RG 123d and the FDA 123 is put in a floating state.

At time t4, the signal charge D stored under the transfer electrode 122a of the horizontal transfer shift register 122 is reached.
L1 is transferred to the FDA 123 and output as a voltage signal. In addition, the transfer electrode 12 of the vertical transfer shift register 121
The signal charge DF2 stored under 1a moves under the transfer electrode 122d of the horizontal transfer shift register 122, and the signal charge DF3 stored under the transfer electrode 121c of the vertical transfer shift register 121 moves under the transfer electrode 121b.

At time t5, a high level (H) voltage is applied to the RG 123d again, and the FDA 123 is reset. Further, the signal charges stored under each transfer electrode of the horizontal transfer shift register 122 are shifted.

At time t6, a low level (L) voltage is applied to the RG 123d and the FDA 123 becomes in a floating state.

At time t7, the signal charges stored under each transfer electrode of the horizontal transfer shift register are shifted,
The signal charge DF1 is transferred to the FDA 123 and output as a voltage signal.

By repeating the above operation for the number of transfer stages of the horizontal transfer shift register, the signal charge for one line of the pixel can be read from the FDA 123. Further, by repeating this for the number of vertical pixels, the signals of all pixels can be read.

[0016]

As described above, in order to speed up the image capturing by the parallel output image sensor 110, the horizontal transfer shift register of the parallel output image sensor 110 should be divided to provide a large number of output sections. Good. However, since it is desirable that the horizontal pitch of the pixels and the horizontal transfer shift register pitch be the same, it was not possible to secure a sufficient space for forming the floating diffusion amplifier in the output section.

It is an object of the present invention to solve such a problem and to provide a solid-state image pickup device suitable for high-speed image pickup.

[0018]

In order to solve the above-mentioned problems, a solid-state image pickup device of the present invention comprises a plurality of vertical transfer shift registers for serially transferring charges generated according to the amount of incident light, and a plurality of vertical transfer shift registers. And a horizontal transfer shift register that inputs in parallel the charges output from the transfer shift register and transfers the charges in series, the horizontal transfer shift register being composed of a plurality of partial shift registers, and an output unit of the plurality of partial shift registers. Each of them is provided with a charge-voltage conversion amplifier, and the last bit of each partial shift register is the first bit.
Bits other than the last bit are composed of two adjacent electrodes, and the reset timing of the charge-voltage conversion amplifier is such that the charge output from the vertical transfer shift register is the first bit of each bit of the partial shift register. It is characterized in that the timing is the same as the timing of input under the electrode.

[0019]

According to the structure of the present invention, the charges output from the vertical transfer shift register are input to the first electrode of each bit of the horizontal transfer shift register, and at the same time, the charge-voltage conversion amplifier is reset. Then, at the next clock, charges are transferred from the first electrode of each bit of the horizontal transfer shift register to the second electrode. In this case, the charge of the final bit is transferred to the charge-voltage conversion amplifier and converted into a voltage.

According to the present invention, the second electrode of the last bit of the horizontal transfer shift register, which has been conventionally required, is unnecessary. Therefore, when the horizontal transfer shift register is composed of a plurality of partial shift registers, the charge-voltage conversion amplifier can be arranged in the second electrode portion of the final bit of each partial shift register.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the solid-state image pickup device according to the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a configuration diagram showing a parallel output CCD image sensor 10 according to the present embodiment. Parallel output CCD image sensor 1
On the upper part of 0, light receiving regions for performing photoelectric conversion are arranged in a matrix, and a plurality of vertical transfer shift registers 20 for serially transferring the signal charges generated in each light receiving region are provided. In addition, these vertical transfer shift registers 20
Is divided into a plurality of groups, and each group of vertical transfer shift registers 2
A plurality of sets of horizontal transfer shift registers 30 to 32 that input the signal charges output from 0 in parallel and transfer them in series, and an FDA (floating) that converts the signal charges output from the horizontal transfer shift registers 30 to 32 into a voltage. Diffusion amplifiers) 40 to 42.

When the CCD image sensor is classified by the pixel configuration, the light receiving portion and the transfer portion are laid out next to each other, and the IT (interline transfer) method in which the signal charges are transferred to the transfer portion at a time and then sequentially transferred and read, The transfer unit is used as it is as a MOS capacitor type light receiving unit, and is transferred to the storage unit during the vertical blanking period and is sequentially read from this storage unit. Although a frame transfer method or the like is known, an FFT method CCD image sensor is used in this embodiment.

The signal charges generated in each light receiving region are accumulated in the vertical transfer shift register 20 and transferred to the horizontal transfer shift registers 30 to 32 by serial shift. The signal charges transferred to the horizontal transfer shift registers 30 to 32 are
It is given to the FDAs 40 to 42 by serial shift and is output as a voltage signal.

Next, a parallel output CCD according to this embodiment
The upper surface structure of the output portion of the image sensor 10 will be described with reference to FIG. Horizontal transfer shift registers 30 and 31 are provided at the output terminals of each vertical transfer shift register 20,
The signal charges output from each vertical transfer shift register 20 by serial shift are transferred to the horizontal transfer shift register 30,
31 of the transfer electrodes 30a, 30e, 31a, ... The output terminals of the horizontal transfer shift registers 30 and 31 have F
DAs 40 and 41 are provided. The FDA 40 includes an OG (output gate) 40a to which an appropriate bias is applied, an FD (floating diffusion) 40b that is in a floating state but changes in potential due to the inflow of signal charges, and an RD (reset). It comprises an RG (reset gate) 40d for resetting the FD 40b to the potential of the drain 40c. The signal charges output from the horizontal transfer shift registers 30 and 31 by serial shift are given to the FDs 40b and 41b of the FDAs 40 and 41. The gate electrodes of the source follower MOSFETs 50 and 51 are connected to the FDs 40b and 41b of the FDAs 40 and 41, and the potential changes due to the inflow of signal charges into the FDs 40b and 41b are impedance-converted and output.

The vertical transfer shift register 20 and the horizontal transfer shift registers 30, 31 are both operated in two-phase drive, and the two transfer electrodes 20a, 20b, 30b to 30 are used.
One bit is formed by e, 31b .... However, the final bit of the horizontal transfer shift registers 30 and 31 is composed of one transfer electrode 30a and 31a. In the conventional example, the final bit of the horizontal transfer shift register is also composed of two transfer electrodes.
By changing the reset timing of b and 41b,
In this embodiment, the final bit of the horizontal transfer shift registers 30 and 31 can be composed of one transfer electrode 30a and 31a. As a result, it becomes possible to form the FDA 40, 41 at the position where the second transfer electrode of the final bit is arranged.

FIG. 3 shows a parallel output CCD according to this embodiment.
An operation timing chart of the image sensor 10 is shown in FIG.
The potential diagrams of the AA ′ plane and the BB ′ plane shown in the top view of FIG.

The operation of the CCD image sensor 10 according to this embodiment will be described with reference to FIGS. 3 and 4.

First, at time t1, a low level (L) voltage is applied to the RG 40d, and the FDA 40 is in a floating state. Further, since a high level (H) voltage is applied to the P1H terminal, the last signal charge D of one horizontal line is formed below the transfer electrode 30a forming the final bit.
L1 is accumulated. Further, since a low level (L) voltage is applied to the P2V terminal of the vertical transfer shift register 20, the vertical transfer shift register 20 is separated from the horizontal transfer shift register 30.

Next, at time t2, the voltage applied to the P2H terminal changes from low level (L) to high level (H),
The voltage applied to the P1H terminal changes from high level (H) to low level (L). Therefore, the last signal charge DL1 of one horizontal line is output. Also, the voltage applied to the P2V terminal changes from low level (L) to high level (H), and P1V
The voltage applied to the terminal changes from high level (H) to low level (L). Therefore, the vertical transfer shift register 20
The signal charge DF2 stored under the transfer electrode 20a of the above is transferred to below the transfer electrode 30d of the horizontal transfer shift register 30.

Next, at time t3, the RG 40d changes from the low level (L) to the high level (H), and therefore FD4
0b is reset to the potential of RD40c. Also P2V
Since the voltage applied to the terminal is changed from the high level (H) to the low level (L), the signal charges DF1 and DF2 stored under the transfer electrode 20d of each vertical transfer shift register 20,
DF3, ... Are transfer electrodes 3 of the horizontal transfer shift register 30
0a, 30c, 30e, ...

Next, at time t4, a low level (L) voltage is applied to the RG 40d, and the FDA 40 enters a floating state.

Next, at time t5, the voltage applied to the P1H terminal changes from high level (H) to low level (L),
The signal charge DF1 stored under the transfer electrode 30a of the horizontal transfer shift register 30 is output.

Next, at time t6, the high level (H) voltage is applied to the RG 40d again, and the FD 40b becomes RD 40.
It is reset to the potential of c.

At time t7, a low level (L) voltage is applied to the RG 40d, and the FDA 40 is brought into a floating state.

The above operation is performed by the horizontal transfer shift register 30.
It is possible to read out the signal charges of one line of the pixel by repeating the number of transfer stages. Furthermore, by repeating this for the number of vertical pixels, the signals of all pixels can be read.

In this embodiment, the transfer gate lengths of several bits adjacent to the FDAs 40 to 42 among the respective bits of the horizontal transfer shift registers 30 to 32 are defined as the transfer charge amount,
FD is shortened within the range that does not affect other characteristics.
It is more effective when used in combination with measures such as securing a space for incorporating A40 to A42.

In this embodiment, an FFT type n-channel CCD is assumed, but the present invention is not limited to this CCD, and an IT type or FT type CCD may be a p-channel CCD.
However, the same effect can be obtained.

Further, in the present embodiment, the case where the horizontal transfer shift registers 30 to 32 are two-phase driven has been described.
Similar effects can be obtained by phase drive, four phase drive, and the like.

[0039]

According to the solid-state image pickup device of the present invention, the second electrode of the final bit of the horizontal transfer shift register, which has been conventionally required, becomes unnecessary. Therefore, when the horizontal transfer shift register is composed of a plurality of partial shift registers, the charge-voltage conversion amplifier can be arranged at the second electrode portion of the final bit of each partial shift register.
Since a sufficient space for the charge-voltage conversion amplifier is secured in this way, it is possible to divide the horizontal transfer shift register into a large number of partial shift registers in accordance with the demand for higher speed of the solid-state imaging device.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a parallel output CCD image sensor according to an embodiment.

FIG. 2 is a top structural view of an output portion of a parallel output CCD image sensor according to the present embodiment.

FIG. 3 is an operation timing chart of the parallel output CCD image sensor 10 according to the present embodiment.

FIG. 4 is a potential diagram of AA ′ surface and BB ′ surface of the parallel output CCD image sensor 10 according to the present embodiment.

FIG. 5 is a top structural view showing a configuration of a conventional FFT type n-channel CCD image sensor.

FIG. 6 is a top structural view showing a configuration of a conventional FFT type n-channel CCD image sensor.

FIG. 7 is a top structural view of an output portion of a conventional parallel output CCD image sensor.

FIG. 8 C of a conventional parallel output CCD image sensor
It is a cross-sectional structural view of the -C 'plane.

FIG. 9 is an operation timing chart of a conventional parallel output CCD image sensor.

FIG. 10 is a potential diagram of AA ′ surface and BB ′ surface of a conventional parallel output CCD image sensor.

[Explanation of symbols]

10 ... Parallel output CCD image sensor, 20 ... Vertical transfer shift register, 30, 31, 32 ... Horizontal transfer shift register, 40, 41, 42 ... FDA, 50, 51 ...
Source follower MOSFET.

Claims (1)

[Claims] 1. A plurality of vertical transfer shift registers for serially transferring charges generated according to the amount of incident light, and charges output from the plurality of vertical transfer shift registers in parallel for serial transfer. A horizontal transfer shift register, wherein a plurality of first and second electrodes are alternately arranged in the horizontal transfer shift register, and the bit shift of the horizontal transfer shift register is reversed in phase with the first and second electrodes. In the solid-state imaging device that switches the respective voltage values for each clock by multiplying the voltage of the above, the horizontal transfer shift register includes a plurality of partial shift registers, and the output voltage of each of the plurality of partial shift registers is equal to the charge voltage. A conversion amplifier is provided, and the last bit of each partial shift register is the first electrode 1
Then, bits other than the last bit are composed of two adjacent electrodes, and at the reset timing of the charge-voltage conversion amplifier, the charge output from the vertical transfer shift register is the first bit of each bit of the partial shift register. A solid-state imaging device characterized in that the timing is the same as the timing of input under the electrode.