JPH06167951A - Display device drive circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To realize gradation without being limited by the number of levels of voltage signals prepared in advance. [Configuration] A value obtained by slightly shifting one or both of the two input voltages V _i and V _{i + 1} from an optimum value with which a desired gradation is obtained is used. Further, taking the case of two frames as an example, for example, averaging is performed for every two frames, n frame and n + 1 frame, to obtain an intermediate gradation. Therefore,
Each picture element is driven without being completely converted into an alternating current.
A value slightly deviated from the optimum value is used because the transmittance of the liquid crystal layer is determined based on the difference between one of the two voltages and the counter voltage applied to the counter electrode, and the other voltage and the counter voltage. This is because the transmittance of the liquid crystal layer, which is determined based on the difference between and, is the same.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a liquid crystal display device and an EL device.
The present invention relates to a drive circuit of a display device that drives a display device such as an (electroluminescence) display device and a plasma display.

[0002]

2. Description of the Related Art In the above-mentioned liquid crystal display device, substrates are arranged on both sides with a liquid crystal sandwiched therebetween, a pixel electrode is formed on the liquid crystal side surface of one substrate, and the liquid crystal side surface of the other substrate. A counter electrode is formed on the display panel, and display is performed by adjusting the liquid crystal molecule direction of each liquid crystal portion sandwiched by the pixel electrode and the counter electrode.

When driving such a liquid crystal display device, a special driving circuit is used because the response speed of the liquid crystal is very low as compared with the response speed of the fluorescent substance used in the CRT (cathode ray tube) display device. . That is, the drive circuit for liquid crystal display does not give the video signal sent momentarily to each picture element as it is, but the video signal sampled corresponding to each picture element within one horizontal scanning period is horizontally scanned. It is held during the period and is output all at once at the beginning of the next horizontal scanning period or at an appropriate time in the middle thereof. Then, after the output of the video signal voltage to each picture element is started, the signal voltage is held for a time sufficiently exceeding the response speed of the liquid crystal.

FIG. 5 is a block diagram showing a drive circuit for liquid crystal display when a video signal is digitally given, and shows a signal voltage output circuit (source driver) for the nth source line On. In the illustrated example, the video signal data is composed of 2 bits (D0, D1). That is, the video signal data has four values of 0 to 3, and the signal voltage applied to each picture element is any one of the four levels of V0 to V3. This circuit includes a first-stage D flip-flop (sampling flip-flop) provided for each bit D0 and D1 of video signal data.
M _SMP , a second-stage flip-flop (hold flip-flop) M _H , a decoder DEC, and a decoder DEC and a source line On are provided and are supplied with four levels of external voltages V0 to V3, respectively. It is composed of analog switches ASW0 to ASW3.

This circuit operates as follows. The video signal data D0 (or D1) is _fetched from the sampling flip-flop M _SMP to the hold flip-flop M _H at the rising time of the sampling pulse T _SMPn corresponding to the nth picture element, and held there. When the sampling for one horizontal scanning period ends, at which time, the output pulse OE is supplied to the hold flip-up M _H, hold flip-flop M _H video signals held in the data D0 (or D1) in the decoder DEC Is output. The decoder DEC decodes the 2-bit video signal data D0 (or D1) and outputs the value (0 to 3).
According to the above, one of the analog switches ASW0 to ASW3 is turned on and one of the four levels of external voltage V0 to V3 is output to the source line On.

In the example of FIG. 5, since the video signal data is 2 bits, the external voltage output to the source line On requires 4 (= 2 ² ) level, that is, V _{0 to} V ₃ . . When the video signal data is given in 3 bits, the signal voltage output circuit has a circuit configuration as shown in FIG. 6, and the external voltage requires 2 ³ = 8 levels, that is, V _{0 to} V ₇ .

[0007]

As described above,
In a conventional drive circuit for liquid crystal display corresponding to a digital video signal, if the digital video signal data is n bits, 2 ⁿ level is required as an external voltage. When the number of bits of the video signal data is increased in this way to increase the number of gradations, the types of voltage to be applied from the outside increase.

However, as the number of types of voltage to be supplied increases as described above, the voltage supply circuit becomes large and the cost also increases. Further, since the number of input terminals of the LSI used in the drive circuit including the signal voltage output circuit increases, it is difficult to mount the LSI.

Therefore, an inter-frame averaging method is considered as a method of increasing the number of gradations without increasing the number of external voltages. In this way, for example in the case of V ₀ ~V _m-1 of the liquid crystal display of m gray scale to an external voltage (LCD) panel (color m
2 for LCD panel that can display ³ gradations simultaneously
In the case of displaying with a doubled 2 × m gradation, for example, a gradation of a level between two adjacent voltages V _i and V _{i + 1} is obtained. Specifically, as shown in FIG. 8, for one picture element, for each frame, for example, n frames, n + 1 frames, n + 2 frames, and n + 3 frames have voltages V _i and −V.
By giving _{i + 1} , V _{i + 1} , and −V _i , that is, by completely alternating driving, intermediate gray scales are obtained. Therefore, the frequency of the voltage signal (AC frequency) during the AC driving is the frame frequency / 4. That is, when displaying with (2 ¹ × m) gradation, the alternating frequency is the frame frequency / 2 ^{i + 1} . The frame frequency means the frequency of the vertical synchronizing signal.

However, in the above interframe averaging method, the alternating frequency becomes lower in proportion to the factorial of 2,
In particular, when it is used for a panel having a high response speed such as a TFT-LCD panel using a thin film transistor (TFT) as a switching element, there is a problem that flicker occurs and display quality is deteriorated.

The present invention has been made to solve the above-mentioned problems of the prior art, and provides a drive circuit of a display device capable of realizing gradation without being limited by the number of levels of voltage signals prepared in advance. The purpose is to provide.

[0012]

A drive circuit for a display device according to the present invention comprises a display pixel electrode on one of two substrates facing each other with a liquid crystal layer interposed therebetween, and switching to the pixel electrode. A signal line connected through an element and a counter electrode formed on the other substrate.
[(X-1) × 2 ⁿ +1] (n is 1 or more) having the same number of types of digital video signals as that of the input voltage (an integer of 2 or more) A driving circuit of a display device for displaying the display device with (integer) gradation, wherein one of the two voltages and the counter electrode are provided for every two adjacent voltages of the X kinds of applied voltages. The transmittance of the liquid crystal layer, which is determined based on the difference between the counter voltage applied to
A voltage adjusting unit that adjusts the level of one or the other voltage or both of them so that the transmittance of the liquid crystal layer, which is determined based on the difference between the other voltage and the counter voltage, becomes the same, and outputs X kinds of adjustment voltages. And whether or not a voltage value that can obtain a gray level relating to the input digital video signal corresponds to one of the X kinds of voltages, and if so, adjust the adjustment voltage corresponding to that voltage for one frame. outputs during, if not applicable, of X species regulated voltage, the use of two regulated voltage close to the voltage value gradation is obtained about the input digital video signal, the middle of the frame of the 2 ⁿ frames Up to one of the two adjustment voltages or a voltage that is the opposite of the one of the two adjustment voltages is sent to the signal line. Voltage or the other voltage And a selection output means for sending to the signal line for each signal line Select, the objects can be achieved.

[0013]

In the present invention, for example, one or both of the two input voltages V _i and V _{i + 1} is used with a value slightly deviated from the optimum value at which a desired gradation is obtained. Further, taking the case of two frames as an example, for example, averaging is performed for every two frames, n frame and n + 1 frame, to obtain an intermediate gradation. Therefore, each picture element is driven without being completely exchanged.

A value slightly deviated from the optimum value is used because the transmittance of the liquid crystal layer is determined based on the difference between one of the two voltages and the counter voltage applied to the counter electrode.
This is because the transmittance of the liquid crystal layer, which is determined based on the difference between the other voltage and the counter voltage, is the same.

[0015]

First, the basic principle of the present invention will be described.

In the present invention, taking the case of two frames as an example, as described in the section of the operation, the values of the voltages of V _i and V _{i + 1} slightly deviated from the optimum values are used, An average gray level is obtained by averaging every two frames of the n frame and the n + 1 frame, and each pixel is driven without being completely converted to alternating current.

The reason for this will be described below, taking as an example the case of an LCD panel that displays 8 gradations for each of the RGB colors, that is, 512 colors. When the reference voltages V _{0 to} V ₇ are given from the outside and displayed with a gradation of V ₀ (black) ← → V ₇ (white), and the voltage given to the counter electrode is V _COM , the voltage applied to each pixel is It is the potential difference between one voltage selected from V _{0 to} V ₇ and V _COM . For example, FIG. 2 (b), (c), (d)
_{Assuming that} the optimum values of V ₀ , V ₁ and V _COM are set as shown in FIG. 2, the voltage applied to the picture element when V ₀ is given is shown in FIG.
For each clock signal G _ck shown in (2), V ₀ -V _COM changes as shown in (e) of FIG. On the other hand, the voltage applied to the picture element when V ₁ is applied becomes V ₁ -V _COM which changes as shown in FIG.

In [Pattern 1] and [Pattern 2] shown in (g) and (h) of FIG. 2, as shown in FIG. 3, the voltage value is averaged every two frames of n frame and n + 1 frame. In the case, the voltage applied to each picture element is shown. More specifically, [Pattern 1] is initially V ₁ -V
_It is a pattern in which driving with _COM and then driving with V ₀ -V _COM is repeated for each frame.
It is a pattern in which driving with _0- V _COM and then driving with V ₁ -V _COM are repeated for each frame.

Here, the relationship between the voltage applied to the liquid crystal and the transmittance of the liquid crystal at that time is as shown in FIG. 4 in the case of an LCD whose display mode is normally white. In this figure, [Pattern 1] and [Pattern 2] are V ₀
Compared to the optimum DC values of −V _COM and V ₁ −V _COM , [Pattern 1] is shifted in the positive direction and [Pattern 2] is shifted in the negative direction. At this time, if the relational line between the voltage and the transmittance is symmetrical with respect to the optimum DC value, [pattern 1] and [pattern 2] have the same transmittance and display unevenness does not occur. However, in reality, there is a slight difference that is not symmetrical, so that there is a difference in the transmittance between [Pattern 1] and [Pattern 2], which causes display unevenness and lowers display quality.

Therefore, in the present invention, V ₀ , V _1, etc. are set to be slightly shifted from the optimum DC value so that the transmittances of [Pattern 1] and [Pattern 2] are equal. This setting is performed, for example, by displaying [Pattern 1] and [Pattern 2] on the same screen, and finely deciding at least _one of V ₀ and V ₁ so as to obtain the same color depth and determine. be able to.

The settings made as described above are set to V _{1 to} V ₂ ,
The same applies to V _{2 to} V ₃ , V _{3 to} V ₄ , V _{4 to} V ₅ , V _{5 to} V ₆ , and V _{6 to} V ₇ . As a result, in an LCD panel that displays 8 gradations (512 colors) for each of RGB colors, 15 gradations (3375 colors) for each of RGB colors can be displayed without degrading the display quality.

The drive circuit of the display device according to the present invention will be described below.

FIG. 1 is incorporated in an LCD panel for displaying 8 gradations for each color of RGB, that is, 512 colors,
FIG. 9 is a configuration diagram of a drive circuit of a display device that displays 15 gradations (3375 colors) for each of RGB colors. FIG. 1A is a block diagram showing a signal voltage output circuit (source driver) for the nth source line On.
(B) shows a circuit diagram for shifting the 8-level reference voltages V _{0 to} V ₇ from the optimum values.

The drive circuit of this display device is provided with a plurality of the signal voltage output circuits of FIG. 1 (a), and is roughly divided into a front stage drive circuit 10 and a rear stage drive circuit 20. The drive circuit 10 in the previous stage uses the video signal data of 4 bits (D
3 bits (D0 ', D) from 0, D1, D2, D3)
1 ', D2'). Specifically, the drive circuit 10 at the preceding stage has three D flip-flops 1, 2 and 3 which function as T flip-flops. The horizontal synchronizing signal H _SYNC is input to the clock terminal of the D flip-flop 1. Further, the vertical synchronizing signal V _SYNC is input to the clock terminal of the D flip-flop 2. The clock signal ck is input to the clock terminal of the D flip-flop 3. Therefore, the output of the D flip-flop 1 is inverted every time the horizontal synchronizing signal H _SYNC is input, and the output of the D flip-flop 2 is inverted every time the vertical synchronizing signal V _SYNC is input, and the output of the D flip-flop 3 is inverted. The output is inverted every time the clock signal ck is input. The outputs of the D flip-flops 1, 2 and 3 are input to the XOR gate 4, and the output of the XOR gate 4 is given to the AND circuit 5.

On the input side of the AND circuit 5, D1, D2,
A NAND circuit 6 to which each video signal data of D3 is input is connected, and the AND circuit 5 is connected to the XOR gate 4
1 bit D0 of the video signal data in addition to the
And 3 bits D1, D2, D3 of the video signal data passed through the NAND circuit 6 are given. The signal passed through the AND circuit 5 is given to the adder 7. In this adder 7,
The 3 bits D1, D2, D3 of the video signal data are also given as they are. The adder 7 is an AND circuit 5
Output signal from 3bit D of video signal data
Based on 1, D2, D3, 3 bits (D0 ', D
1 ', D2') and output to the drive circuit 20 in the subsequent stage.

The drive circuit 20 in the subsequent stage has a D flip-flop (sampling flip-flop) M _{SMP in} the first stage and a second stage provided for each bit D0 ', D1', D2 'of the video signal data. Flip-flop (hold flip-flop) M _H , and one decoder DEC,
Each of the analog switches ASW0 to ASW7 provided between the decoder DEC and the source line On and the input external voltages V0 to V7 of eight different levels are adjusted, and the adjusted voltages V0 'to V7' are adjusted. Eight voltage adjustment circuits 31 to be applied to the analog switches ASW0 to ASW7
Composed of and.

All the voltage adjusting circuits 31 have the same structure. Taking one of these as an example,
As shown in FIG. 1B, the inverting terminal 32a of the amplifier 32
A predetermined voltage is applied to the variable resistor 33, and the variable resistor 33 is connected to the non-inverting terminal 32b. The voltage is adjusted by adjusting the position of the variable resistor 33 to determine the voltage V _Ri , and the adjusted voltage is output. It is composed. The variable resistor 33
The position adjustment is performed by displaying the corresponding two patterns on the same screen as described above and determining the same color depth.

The drive circuit 20 operates as follows.
The video signal data D0 '(or D1', D2 ') is the nth
At the rising _edge of the sampling pulse T _SMPn corresponding to the th picture _element , the sampling flip-flop M _SMP takes it into the hold flip-flop M _H and holds it there. When the sampling for one horizontal scanning period is completed, at that time, the output pulse OE is given to the hold flip flop M _H and the hold prep flop M _H.
The video signal data D0 '(or D1',
D2 ') is output to the decoder DEC. Decoder DE
C is the 2-bit video signal data D0 '(or D
1 ', D2') is decoded, and one of the analog switches ASW0 to ASW7 is turned on according to the value (0 to 7). One of the analog switches ASW0 to ASW7 that has become conductive is the corresponding voltage adjusting circuit 3
The adjusted voltage from 1 is output to the source line On.

Further, the drive circuit 20 has the above-mentioned voltage at which the gradation for the inputted digital video signal can be obtained.
A determination circuit (not shown) for determining whether or not one of the grayscale voltages is applied is provided. When this determination circuit determines that it is applicable, it outputs the adjusted voltage corresponding to the voltage for one frame. When it is determined that it does not correspond, two adjustment voltages, out of the eight gradation voltages, which are close to the voltage value at which a predetermined gradation is obtained are used. Also, in the first frame of two consecutive frames, one of the adjusted voltages is selected and output to the source line On, and in the next frame, the voltage that is the opposite of the other voltage is selected and output to the source line On. Alternatively, on the contrary, in the first frame, the positive or negative opposite voltage of the one of the two adjustment voltages is selected and output to the source line On, and in the next frame, the other voltage of the two adjustment voltages is selected. Output to the source line On.

Therefore, the drive circuit of the display device having such a configuration uses the adjustment voltages V ₀ ′ to V ₇ ′, which are obtained by shifting the 8-level reference voltages V _{0 to} V ₇ from the optimum values, and therefore, the corresponding intermediate voltage. Whichever of the two adjustment voltages sandwiching the gradation is used first, the intermediate gradation of the same voltage level can be obtained. Therefore, the number of gradations can be increased without increasing the reference voltage, and the cost can be greatly reduced. Further, the alternating frequency in the case of using this drive circuit is twice the frame frequency / 2 that in the conventional case, and the occurrence of flicker can be suppressed.

In the above embodiment, an LCD for displaying 8 gradations
The case of displaying 15 gradations on the panel has been described as an example, but the present invention is not limited to this, and an LCD that displays m gradations.
The same can be applied to the case of displaying (2 ¹ × m) gradation on the panel. Also at this time, the alternating frequency is doubled as compared with the conventional one, and it is possible to prevent the deterioration of the display quality.

In the above-mentioned embodiment, the averaging is performed for 2 frames, but the present invention is not limited to this, and averaging may be performed for 4 (= 2 ² ) frames or 2 ⁿ frames. The averaging is 2 ⁿ
Up to a frame in the middle of the frame, one of the two adjustment voltages or the positive / negative opposite voltage of the one voltage is selected, and the subsequent frames select the positive / negative opposite voltage of the other of the two adjustment voltages or the other one. Select the voltage of. This allows
By averaging in 4 (= 2 ² ) frames, it is possible to display 29 gradations (24389 colors) for each color of RGB.
Furthermore, by averaging in 2 ⁿ frames, it is possible to display (7 × 2 ⁿ +1) gradation for each color of RGB.

The present invention can be carried out without being limited to the number of gradations and the number of intermediate gradations of the LCD panel, but the display form is as follows. An LCD panel of X gradation can display [(X−1) × 2 ⁿ +1] gradation.

In the above embodiments, the matrix type liquid crystal display device has been described as an example, but the present invention is also applied to drive circuits for other types of display devices such as EL (electroluminescence) display devices and plasma displays. It is possible.

[0035]

According to the present invention, it is possible to provide a drive circuit of a display device which can realize gradation without being limited by the number of levels of voltage signals prepared in advance. Further, since it is possible to increase the number of gradations without increasing the reference voltage,
The cost can be greatly reduced. Further, since the alternating frequency in the case of using this drive circuit can be doubled to the frame frequency / 2, which is the conventional one, the occurrence of flicker can be suppressed.

[Brief description of drawings]

FIG. 1A is a block diagram showing a drive circuit of a display device of the present embodiment, and FIG. 1B is a circuit diagram showing a voltage adjustment circuit for adjusting a reference voltage.

FIG. 2 is a schematic diagram of selected voltages of each picture element of the present invention.

FIG. 3 shows an example of a pattern for applying a voltage to each picture element of the present invention.

FIG. 4 is a diagram showing the relationship between the voltage applied to the liquid crystal and the transmittance in the present invention.

FIG. 5 is a block diagram showing a drive circuit of a conventional display device (in the case of 2 bits).

FIG. 6 is a block diagram showing a drive circuit of a conventional display device (in the case of 3 bits).

FIG. 7 shows an example of a conventional voltage pattern to be selectively applied to each picture element.

[Explanation of symbols]

 10 Front-stage drive circuit 20 Rear-stage drive circuit 31 Voltage adjustment circuit

Claims (1)

[Claims] 1. A picture element electrode for display and a signal line connected to the picture element electrode via a switching element are provided on one of two substrates facing each other with a liquid crystal layer interposed therebetween. It is attached to a display device in which a counter electrode is formed on the other substrate, is applied with X (integer of 2 or more) types of voltage, and is the same number as the type of input digital video signal.
A driving circuit of a display device for displaying the display device at a gradation of [(X-1) × 2 ⁿ +1] (n is an integer of 1 or more) having an intermediate gradation, wherein: For every two of the voltages approaching,
The transmittance of the liquid crystal layer, which is determined based on the difference between one of the two voltages and the counter voltage applied to the counter electrode, and the transmittance of the liquid crystal layer, which is determined based on the difference between the other voltage and the counter voltage. So as to be the same, one or the other or both of the voltage levels are adjusted to output X kinds of adjustment voltages, and a voltage value for obtaining a gradation for the input digital video signal is the X value. Determine whether one of the seed voltage
When it corresponds, the adjustment voltage corresponding to the voltage is output for one frame, and when it does not correspond, it is close to the voltage value of the X kinds of adjustment voltages at which the gradation for the input digital video signal is obtained. 2 adjustment voltages are used and 2
Up to a frame in the middle of ⁿ frames, one of the two adjustment voltages or a voltage having a positive / negative reversal of the one voltage is selected and transmitted to the signal line, and in the subsequent frames, the other of the two adjustment voltages is selected. A drive circuit for a display device, which includes, for each signal line, a selection output unit that selects a voltage that is the opposite of the positive or negative voltage or the other voltage and sends the selected voltage to the signal line.