JPH06161972A - Multiprocessor system - Google Patents

Abstract

(57) [Abstract] [Purpose] To improve the execution efficiency without reducing the data transfer capability between boards. [Configuration] The processor board, memory board, and input / output board can be electrically connected to either a tightly coupled bus or a loosely coupled bus. Connect the relay board only to loosely coupled buses. Data transfer by the loosely coupled bus is performed via the relay board, the control board constantly monitors the data transfer status on the tightly coupled bus and the loosely coupled bus, and depending on the transfer status, the processor board Among the memory board and the input / output board, the board of the group having the electrical connection to the tightly coupled bus and the board of the group having the electrical connection to the loosely coupled bus are changed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system in which a plurality of microprocessors are combined to perform distributed processing.

[0002]

2. Description of the Related Art In a processing system using a microprocessor, it is useful to distribute the processing to a plurality of processors to distribute the functions and loads in order to improve the processing capacity. Therefore, a multiprocessor system is constructed.

In such a multiprocessor system, in order to exchange data between the processors, as shown in FIG. 4, each board 401 mounting each processor is connected by a shared bus 402. To be Note that the configuration in which this shared bus is used is called tight coupling.

In order to cope with a further increase in load, a system in which the units of tight coupling shown in FIG. 4 are further coupled by some sort of relay board is adopted. This configuration is shown in FIG. In FIG. 5, processor boards 401 belonging to different shared buses 402 are relay boards 403.
A structure that is connected through is called loose coupling.

In FIGS. 4 and 5, the type of board connected to the shared bus is not limited to the processor board, but may be a memory board or an input / output board.

[0006]

However, as shown in FIG.
The conventional multiprocessor shown in FIG. 5 has the following problems to be solved.

In the tightly coupled multiprocessor system shown in FIG. 4, the number of boards that can transfer data through the shared bus at a certain time point is limited to one pair. Therefore, when another board tries to transfer data, it is necessary to wait until bus allocation is obtained. This becomes more significant as the number of boards coupled to the shared bus increases, and the processing capability of the entire system decreases accordingly.

In the loosely-coupled multiprocessor system shown in FIG. 5, for example, when a data transfer amount increases between loosely-coupled boards as a program is executed, a high speed is achieved because a relay board is used. Can't handle. Further, from the software side, it is necessary to perform programming so as to minimize the data transfer between the boards that are in a tightly coupled relationship, and there is a large restriction from the hardware configuration.

The present invention has been made in order to solve the above problems, and tightly couples the boards in correspondence with the time change of the data transfer amount between the boards accompanying the execution of the program. , A loose-coupling relation is changed so that the data transfer capability between boards is not deteriorated, and a multiprocessor system with high execution efficiency is provided.

[0010]

A multiprocessor system according to the present invention has at least one multiprocessor system as shown in FIG.
The above processor boards 101, 102, 103 ... At least one or more memory boards 201 ... At least one
Input / output board 301 ... One control board 4, one relay board 5, one tightly coupled bus 6 and 1
A multiprocessor system comprising two loosely coupled buses 7, said processor boards 101, 102, 10
3, the memory board 201, the input / output board 301, and the control board 4 have mechanical coupling by connectors with both the tightly coupled bus 6 and the loosely coupled bus 7, and the relay board 5 has the loosely coupled bus 7. And a mechanical connection by a connector only, and the processor boards 101, 102,
103, memory board 201, input / output board 301
Some of all the boards of ... have electrical connection only with said tightly coupled bus 6 at some point in time,
All other processor boards 101, 102, 103
..., the memory board 201, the input / output board 301, ... have electrical connection only with the loosely coupled bus 7 at that time, and the control board 4 always has the tightly coupled bus 6,
The relay board 5 has an electrical connection with both the loosely coupled buses 7, and the relay board 5 always has an electrical connection only with the loosely coupled bus 7. Data transfer by the loosely coupled bus 7 is performed via the relay board 5. The control board 4 constantly monitors the data transfer status on the tightly coupled bus 6 and the loosely coupled bus 7, and depending on the transfer status, the processor board 1
Of the 01, 102, 103, ..., Memory boards 201, ..., I / O boards 301 ..., the boards of the groups having the electrical connection to the tightly coupled bus 6 and the boards of the groups having the electrical connection to the loosely coupled bus 7. It is characterized by changing each.

[0011]

The multiprocessor system configured as described above operates as follows. The control board 4 constantly monitors the data transfer status between the respective boards through the tightly coupled bus 6 and the loosely coupled bus 7 so that the group of boards having electrical connection to the tightly coupled bus 6 and the loosely coupled bus 7 are connected to each other. It is possible to change each of the boards of the group having the electrical connection.

The number of boards belonging to the tightly-coupled bus 6 and the loosely-coupled bus 7 and what kind of trigger changes a board between the tightly-coupled bus and the loosely-coupled bus depends on the control board 4. It is determined by a tightly coupled bus / loosely coupled bus connection decision circuit installed inside. This allows

(1) It is assumed that the degree of data transfer between the boards changes as the program is executed. For example, in FIG. 1, the data transfer between the processor boards 101 and 102 is frequent at one execution stage of the program, while the processor board 10 is at another stage.
It is assumed that the transfer between 1 and 103 has changed so as to become frequent.
In such a situation change, if the operation algorithm of the tightly coupled bus / loosely coupled bus connection determination circuit is appropriately configured, the connection boards to the tightly coupled bus 6 having a high data transfer rate can be connected to the processor boards 102 to 103. By replacing with, the program execution is continued without lowering the processing speed.

(2) It is possible that the absolute number of boards that require mutual data transfer may change as the program is executed. In such a case, by appropriately configuring the operation algorithm of the bus connection determination circuit,
A board whose frequency of data transfer via the tightly coupled bus 6 has become less frequent can be removed from the electrical connection of the tightly coupled bus and routed to the loosely coupled bus 7. By doing so, the number of boards connected to the tightly coupled bus 6 can be suppressed to a necessary minimum, and a decrease in data transfer efficiency via the same bus can be prevented.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a multiprocessor system according to the present invention will be described below with reference to the drawings. 1, the processor boards 101, 102, 103 ..., The memory boards 201 ..., The input / output boards 301 ... And the control board 4 have both the tightly coupled bus 6 and the loosely coupled bus 7 and mechanical coupling by connectors. The relay board 5 has a mechanical connection by a connector only with the loosely coupled bus 7.

Processor boards 101, 102, 103
,, memory board 201, input / output board 301, ..., Some boards have electrical connection only with said tightly coupled bus 6 at one point in time, and all other processor boards 101. , 102, 103 ..., Memory board 201 ..., Input / output board 301 ... Have electrical connection only to the loosely coupled bus 7 at that time,
The control board 4 always has electrical connection with both the tightly coupled bus 6 and the loosely coupled bus 7, and the relay board 5 always has electrical connection only with the loosely coupled bus 7.

Data transfer by the loosely coupled bus 7 is
It is performed via the relay board 5. That is, the board that has issued the data must always write the data to the relay board 5, and the board that receives the data must always read the data from the relay board 5. Therefore, the data transfer rate by the loosely coupled bus 7 is slower than that by the tightly coupled bus 6. Which bus is used for transfer depends on the tightly coupled bus / loosely coupled bus connection control signal 8 from the control board 4 in each case. That is, the control board 4 constantly monitors the data transfer status on the tightly coupled bus 6 and the loosely coupled bus 7. Depending on the transfer status, among the processor boards 101, 102, 103, ..., Memory boards 201, ..., Input / output boards 301 ..., Boards of a group having electrical connection to the tightly coupled bus 6 and electrically connected to the loosely coupled bus 7. The board of the group having the physical connection is changed.

FIG. 2 illustrates for each board how the electrical connections to the tightly coupled buses 6 and loosely coupled buses 7 are controlled. Which board is electrically connected to the tightly coupled bus 6 and which board is electrically connected to the loosely coupled bus 7 by the tightly coupled bus / loosely coupled bus connection determination circuit 41 in the control board 4. Can be decided Then, this result is transmitted to each board by the tightly coupled bus / loosely coupled bus connection control signal 8. This connection control signal 8 is supplied to each board one by one. For example, in the case of LOW level, electrical connection with the tightly coupled bus 6, HI
In the case of the GH level, it is defined as an electrical connection with the loosely coupled bus 7. Therefore, this connection control signal 8 needs to be as many as all the boards except the relay board 5 and the control board 4. The connection control signal 8 is
In FIG. 1 and FIG. 2, the power is supplied through the tightly coupled bus 6, but it may be supplied through the loosely coupled bus 7.

Each board receiving the supply of the connection control signal 8 uses this signal to input / output the interface 1011 with the tightly coupled bus 6 in the board or the loosely coupled bus 7.
By separately enabling the input / output interfaces 1012 of and, the electrical connection with the tightly coupled bus 6 or the loosely coupled bus 7 is realized. Regarding the input / output interface 1011 with the tightly coupled bus 6 and the input / output interface 1012 with the loosely coupled bus 7, when these blocks function as an output interface from the board, a line driver, when they function as an input interface, a receiver, When including both output interface functions, a hardware element such as a bus transceiver may be used.

FIG. 3 is a diagram for explaining the operation of the tightly coupled bus / loosely coupled bus connection determining circuit 41 for each board.
In FIG. 3, the numbers in the squares in the leftmost column and the top row indicate the boards in FIG. 1, for example, each processor board 10
.., 102, 103 ... The number in the square in the leftmost column corresponds to the master operation of the board indicated by each symbol, for example, the processor boards 101, 102, 103 .... The numbers in the squares on the top line correspond to the slave operations of the boards indicated by the respective symbols, for example, the processor boards 101, 102, 103. A master is a board that actively initiates bus cycles for exchanging data between itself and a slave. A slave is a board that detects a data transfer bus cycle initiated by the master and passively exchanges data with the master. For example, in FIG. 1, when the processor board 101 executes a data write instruction to the processor board 102, the processor board 101 is a master and the processor board 102 is a slave. The processor board 102 is the processor board 103.
When a data read instruction is executed from the processor board 102,
3 is a slave.

The cells with R and W from the second column onward from the left and from the second row onward hold the cumulative number of data transfers between the boards. R reads, W
Means write. The tightly coupled bus / loosely coupled bus connection determination circuit 41 is provided with a counter corresponding to each R and W of the cell, and the cumulative number of data transfers between the boards is determined by the tightly coupled bus 6 or the loosely coupled bus 7. It is held by this counter regardless of the data transfer through. For example, when a write command is executed from the processor board 101 to the processor board 102, W indicated by reference numeral 411 in FIG.
The counter value corresponding to is incremented by one. When the processor board 102 executes a read instruction from the processor board 103, the value of the counter corresponding to R indicated by reference numeral 412 in FIG. 3 increases by one.

1, 2, and 3, the master operation board monitor signal 9 on the tightly coupled bus, the master operation board monitor signal 10 on the loosely coupled bus, the address monitor signal 11 on the tightly coupled bus, and the loosely coupled bus. The address monitor signal 12 on the coupled bus, the read / write bus cycle identification signal 13 on the tightly coupled bus, and the read / write bus cycle identification signal 14 on the loosely coupled bus are used for updating the counter value. It These 9 to 14 signals are tightly coupled bus 6
Alternatively, each time a data transfer bus cycle through the loosely coupled bus 7 is performed, it is input to the connection determination circuit 41 and processed as follows.

(1) The monitor signal 9 or the monitor signal 10 is decoded to identify the board functioning as the master. During the data transfer cycle, the master board outputs the coded signal corresponding to itself as the monitor signal 9 or the monitor signal 10. The number M of bits required for this identification is obtained from the relationship of 2 ^M = N, where N is the number of all boards except the relay board 5 and the control board 4. That is, the monitor signal 9 and the monitor signal 10 are M-bit signals.

(2) The address monitor signal 11 or 12 is decoded to identify the board functioning as a slave.

(3) Whether the bus cycle performed is a read cycle or a write cycle is judged by the recognition signal 13 or 14.

By the processes (1) to (3), it is possible to specify the master, the slave, and the read / write for the data transfer bus cycle performed immediately before. Therefore, in the connection determining circuit 41 of FIG. The counter value of R or W corresponding to the cell can be incremented by one.

Each square in the second column from the right is a register that holds the total number of bus cycles performed by each board as a master. For example, in the square indicated by reference numeral 413 in FIG. 3, the accumulated value of all read and write bus cycles performed by the processor board 101 as a master is stored. In terms of hardware, this register is configured as the sum of all R and W counter values of the row to which it belongs.

Each square in the second row from the bottom is a register for holding the total number of bus cycles performed by each board as a master. For example, the cumulative number of all read and write cycles in which the processor board 102 is involved as a slave is stored in the square indicated by reference numeral 414 in FIG. In terms of hardware, this register is configured as the sum of all R and W counter values of the column to which it belongs.

Each cell in the rightmost column is a counter that holds the number of "vacant" continuations in which each board is not performing a bus cycle as a master. For example, in FIG.
In the square counter indicated by reference numeral 415, the number of “vacant” continuations in which the processor board 101 is not involved in the bus cycle as the master is held. In terms of hardware, this counter increases by 1 in synchronization with the update of all R and W counter values other than the column to which the counter belongs. Then, if the value of any one of the R and W counters in the column to which it belongs is updated, it is cleared to "0".

Each cell in the bottom row is a counter that holds the number of "vacant" continuations in which each board does not participate in the bus cycle as a slave. For example, reference numeral 41 in FIG.
The 6th counter has the processor board 10
2 holds the number of "free" continuations not involved in the bus cycle as a slave. In terms of hardware, this counter is used for all R, W except the column to which it belongs.
As the counter value is updated, 1 increases in synchronization. Then, if the value of any one of the R and W counters in the column to which it belongs is updated, it is cleared to "0".

The tightly coupled bus / loosely coupled bus connection determining circuit 41 for each board operates as described above. By utilizing this operation, the logic for determining the electrical connection to the tightly coupled bus 6 and the electrical connection to the loosely coupled bus 7 of each board should be configured in several ways as follows. Is possible.

(1) The number of boards that can belong to the tightly coupled bus is determined in advance. When a data transfer bus cycle is performed and the bus cycle is through a loosely coupled bus, both the master and slave boards involved in this bus cycle are immediately connected to the tightly coupled bus. Instead, two boards out of the boards that previously belonged to the tightly coupled bus are removed from the tightly coupled side and passed to the loosely coupled bus side. Which board is excluded from the tightly coupled side depends on the value of the bus cycle “vacant” continuation number holding counter in the connection determination circuit 41 of FIG. That is, it is only necessary to eliminate two boards whose holding amount in this counter is large on both the master side and the slave side. This is because it is considered that a board having a larger holding amount is less likely to be involved in the bus cycle for the time being.

(2) The same logic as that of (1) is used except that the judgment criterion for selecting a board to be excluded from the tightly coupled bus side is that of the bus cycle total number holding register in the connection determination circuit 41. In other words, this is a method in which the amount held in this register is eliminated from the board having the smaller sum of the master side and the slave side. By taking this logic, boards that have participated frequently in bus cycles in the past will always be connected to tightly coupled buses, and boards that have rarely participated in bus cycles will always be connected to loosely coupled buses. It can be expected that the data transfer efficiency of the entire multiprocessor system will not decrease.

(3) In both of the logics described in (1) and (2) above, the number of boards that can belong to the tightly coupled bus is fixed. It can also be configured. In this case, according to the judgment criterion described in (2), the logical configuration is such that the chances of connection to the tightly coupled bus are narrowed down to the board that has frequently participated in the bus cycle in the past. For example, after the program execution is started, a write bus cycle from the processor board 101 to the processor board 102, which is indicated by the counter 411 in FIG. 3, and the processor board 103 to the processor board 1, which is indicated by the counter 412.
Assume that the frequency of only two read bus cycles to 02 becomes particularly large. As a result, the tightly coupled bus 6 is exclusively used by the processor boards 101, 102, 103, and these three processor boards 101, 10
2, 103 can use the tightly coupled bus 6 to continue high-speed data transfer bus cycles.

The logics described in (1) to (3) above can be easily realized in hardware by a digital circuit and can be incorporated in the connection determining circuit 41.

FIG. 6 shows an example of a logic circuit function block diagram for realizing the logic (1). In FIG. 6, reference numeral 61 is a master board determination circuit, 62 is a slave board determination circuit, 63 is a register, 64 is a counter, and 65 is a tightly coupled bus / loosely coupled bus board allocation determination circuit. Signal M
BEi (i = 101, 102, 103 ..., and so on))
Is the number of empty bus cycles on the master side of board i, SBE
i is the number of idle bus cycles on the slave side of board i.

The master board determination circuit 61 functions as follows. Processor boards 101, 102 ... (FIG. 1)
When each of the boards becomes a master and a READ / WRITE cycle using the loosely coupled bus 7 is performed,
In the bus cycle, the MBi signal that specifies the board that has operated as the master becomes active and is output. For example, it is output when each of the boards 101, 102 ... Operates as a master. Monitor signal 10 for each board 1
01 and 102 are coded as shown in FIG. Therefore, it suffices to configure a decoding circuit that outputs only one of MBi active for the monitor signal 10.

The slave board determination circuit 62 operates as follows. Processor boards 101, 102 ... (FIG. 1)
When a READ / WRITE cycle using the loosely coupled bus 7 is performed for the addresses assigned to the respective boards, the SBi signal that specifies the board operating as the slave in the bus cycle is activated and output. It For example, it is assumed that addresses are assigned to the boards 101, 102, ... As shown in FIG.
In this case, if the address in the area is accessed,
SB102 when the address of the area is accessed
A logic such that a signal becomes active (hereinafter, similarly, SB103, SB104 (not shown) ... become active in the area of ...) Is configured.

The register 63 is used for each board N in FIG.
o. Holds the number of continuous "busy" bus cycles on the master side and the number of continuous "busy" bus cycles on the slave side corresponding to. For example, in the case of FIG. 6, it represents a register that holds the contents of 415 and 416 in FIG.

The counter 64 is incremented by 1 each time either MBi or SBi is increased. MBi, S
When either Bi is cleared to 0, the output BEi is also cleared to 0. As a result, the signal BEi is transmitted to each board No. Each time, it represents the cumulative number that the board has not been continuously involved in the bus cycle.

In the tightly coupled bus / loosely coupled bus board allocation determining circuit 65, the number of outputs CBi that are outputs "L" (tightly coupled bus connection) is predetermined.
When SBi or MBi is input as active, the corresponding CBi becomes “L” unconditionally. (Of course, what was originally “L” remains “L”.) Instead, CBi corresponding to the two higher-ranked ones in BEi become “H”. That is, it goes around the loosely coupled bus connection.

FIG. 9 shows an example of a functional block diagram of a logic circuit for realizing the logic (2). In FIG. 9, reference numeral 91 is a master board determination circuit, 92 is a slave board determination circuit, 93 is a register, 94 is an adder, and 95 is a tightly coupled bus / loosely coupled bus board allocation determination circuit. Signal MB
Ti (i = 101, 102, 103 ..., Same below)) is the total number of bus cycles operating as a master of board i, and SBTi is the total number of bus cycles operating as a slave of board i.

The master board determination circuit 91 functions as follows. Processor boards 101, 102 ... (FIG. 1)
When each of the boards becomes a master and a READ / WRITE cycle using the loosely coupled bus 7 is performed,
In the bus cycle, the MBi signal that specifies the board that has operated as the master becomes active and is output. For example, it is output when each of the boards 101, 102 ... Operates as a master. Monitor signal 10 for each board 1
The codes 01 and 102 are coded as shown in FIG. 7 in the same manner as the logic (1). Therefore, for this monitor signal 10, M
It suffices to configure a decoding circuit in which only one of Bi is activated and output.

The slave board determination circuit 92 operates as follows. Processor boards 101, 102 ... (FIG. 1)
When a READ / WRITE cycle using the loosely coupled bus 7 is performed for the addresses assigned to the respective boards, the SBi signal that specifies the board operating as the slave in the bus cycle is activated and output. It For example, it is assumed that addresses are assigned to the boards 101, 102, ... As shown in FIG.
In this case, if the address in the area is accessed,
SB102 when the address of the area is accessed
A logic such that a signal becomes active (hereinafter, similarly, SB103, SB104 (not shown) ... become active in the area of ...) Is configured.

The register 93 is used for each board N in FIG.
o. The bus cycle total as a master and the bus cycle total as a slave corresponding to are held. For example, in the case of FIG. 9, it represents a register that holds the contents of 413 and 414 of FIG.

The adder 94 outputs the value of MBTi + SBTi. As a result, the signal BTi is transmitted to each board No.
Each will represent the total number of bus cycles involved by the board.

In the tightly coupled bus / loosely coupled bus board allocation determining circuit 95, the number of outputs CBi that are outputs "L" (tightly coupled bus connection) is predetermined.
When SBi or MBi is input as active, the corresponding CBi becomes “L” unconditionally. (Of course, what was originally "L" remains "L".) Instead, CBi corresponding to the lower two of BTi having smaller values becomes "H". That is, it goes around the loosely coupled bus connection.

FIG. 10 shows an example of a functional block diagram of a logic circuit for realizing the logic (3). In FIG. 10, 10
Reference numeral 03 is a register, 1004 is an adder, 1005 is a tightly coupled bus / loosely coupled bus board allocation determination circuit, and 1006 is a tightly coupled bus / loosely coupled bus connection control signal. Signal MB
Ti (i = 101, 102, 103 ..., Same below)) is the total number of bus cycles operating as a master of board i, and SBTi is the total number of bus cycles operating as a slave of board i.

The register 1003 is for each board No. in FIG. The bus cycle total as a master and the bus cycle total as a slave corresponding to are held. For example, in the case of FIG. 10, it represents a register that holds the contents of 413 and 414 of FIG.

The adder 1004 outputs the value of MBTi + SBTi. As a result, the signal BTi is transmitted to each board N
o. Each will represent the total number of bus cycles involved by the board.

In the tightly coupled bus / loosely coupled bus board allocation determining circuit 1005, a certain time interval T is divided into
Count the total number of each BTi within that time. As a result, for example, as shown in FIG. 11, BT103, BT10
6 of BT101 and BT109, 90 of ΣBTi
If it occupies more than%, the next section T allocates tightly coupled buses to these four boards 101, 103, 106, 109. That is, CB101, CB103, C
B106 and CB109 are set to "L". In this case, the tightly coupled bus 6 is assigned to a board that occupies a bus cycle number of up to 90%, but a value suitable for the convenience of the system may be adopted as this value. The value of T is also the same. The clock in the control board 4 is used to divide this T time interval.

In the logic described in the above (1) to (3), it may not be necessary to hold all the data transfer histories between the boards from the initial stage of program execution. That is, it is a case where the logical determinations of (1) to (3) may be performed based on the data transfer history at a certain time interval traced back in the past.
In such a case, each counter and each register in the connection determining circuit 41 will be cleared at each time interval. The clock signal 42 in the control board in FIGS. 2 and 3 is used by the connection determining circuit 41 to detect this time interval.

In addition to the above (1) to (3), various logics can be considered by using the connection determining circuit 41, but an appropriate one may be constructed depending on the purpose of use of the multiprocessor system. .

[0054]

As described above, according to the present invention, in a multiprocessor system, in order to cope with the time change of the data transfer amount between the boards due to the execution of the program, the close coupling between the boards, Since the loose coupling relationship can be changed, a multiprocessor system with high execution efficiency can be obtained without reducing the data transfer capability between the boards.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a multiprocessor system according to the present invention.

FIG. 2 is a connection diagram illustrating a tightly coupled bus / loosely coupled bus connection control for each board.

FIG. 3 is a diagram illustrating a configuration of a tightly coupled bus / loosely coupled bus connection determination circuit for each board.

FIG. 4 illustrates a tightly coupled multiprocessor system.

FIG. 5 is a diagram illustrating a loosely coupled multiprocessor system.

FIG. 6 is a functional block diagram of a logic circuit for realizing logic (1).

FIG. 7 is a diagram illustrating coding of a monitor signal.

FIG. 8 is a diagram illustrating an address of an area.

FIG. 9 is a functional block diagram of a logic circuit for realizing logic (2).

FIG. 10 is a functional block diagram of a logic circuit for realizing logic (3).

FIG. 11 is a diagram illustrating an exclusive state of a bus cycle.

[Explanation of symbols]

101, 102, 103 Processor board 1011 I / O interface with tightly coupled bus 1012 I / O interface with loosely coupled bus 201 Memory board 301 I / O board 4 Control board 41 Tightly coupled bus / loosely coupled bus connection decision circuit 411, 412 Counter 413,414 registers 415,416 counter 42 clock signal in control board 5 relay board 6 tightly coupled bus 7 loosely coupled bus 8 tightly coupled bus / loosely coupled bus connection control signal 9 master operation on tightly coupled bus monitor signal 10 loosely coupled Master operation on bus Board monitor signal 11 Address monitor signal on tightly coupled bus 12 Address monitor signal on loosely coupled bus 13 Reading on tightly coupled bus /
Write bus cycle recognition signal 14 Reading / reading on loosely coupled bus
Write bus cycle identification signal

Claims (1)

[Claims] 1. At least one or more processor boards,
A multiprocessor system comprising at least one or more memory boards, at least one or more input / output boards, one control board, one relay board, one tightly coupled bus and one loosely coupled bus, the processor board comprising: The memory board, the input / output board and the control board have mechanical coupling by connectors with both the tightly coupled bus and the loosely coupled bus, and the relay board has mechanical coupling by the connector only with the loosely coupled bus, Some of all boards, processor boards, memory boards, and I / O boards, have electrical connections only to the tightly coupled buses at one point in time, and all other boards The output board now has electrical connections only to the loosely coupled buses, and the control board Has an electrical connection with both a tightly coupled bus and a loosely coupled bus at all times, and the relay board has an electrical connection only with a loosely coupled bus at all times, and data transfer by the loosely coupled bus is via the relay board. The control board constantly monitors the data transfer status on the tightly coupled bus and the loosely coupled bus, and selects the tightly coupled bus among the processor board, the memory board, and the input / output board according to the transfer status. A multiprocessor system characterized in that a group of boards having electrical connections and a group of boards having electrical connections on loosely coupled buses are changed.