JPH06177251A - Wiring structure of semiconductor device - Google Patents
Wiring structure of semiconductor deviceInfo
- Publication number
- JPH06177251A JPH06177251A JP32637192A JP32637192A JPH06177251A JP H06177251 A JPH06177251 A JP H06177251A JP 32637192 A JP32637192 A JP 32637192A JP 32637192 A JP32637192 A JP 32637192A JP H06177251 A JPH06177251 A JP H06177251A
- Authority
- JP
- Japan
- Prior art keywords
- conductor layer
- wiring
- signal wiring
- control signal
- test mode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 34
- 239000004020 conductor Substances 0.000 claims abstract description 60
- 230000002093 peripheral effect Effects 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 abstract description 60
- 239000011229 interlayer Substances 0.000 abstract description 8
- 238000009792 diffusion process Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の配線構造
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure for a semiconductor device.
【０００２】[0002]
【従来の技術】近年の半導体装置の設計手法では、設計
した半導体装置の本来の使用目的のために動作させる実
動作モードと、設計した半導体装置内部の機能ブロック
単位が正常動作することをテストするためのテストモー
ドが存在する。ここでいうテストモードとは、複数のブ
ロックからなる半導体装置内部の機能ブロック単位の入
出力端子を、半導体装置外周部の入出力端子にそれぞれ
割り当てる制御をする回路を構成することによって、半
導体装置外部から半導体装置内部のブロック単位での入
力情報を操作し、出力情報を観察できるモードのことを
いう。2. Description of the Related Art In recent semiconductor device designing methods, the actual operation mode in which the designed semiconductor device is operated for the intended purpose and the normal operation of functional block units inside the designed semiconductor device are tested. There is a test mode for The test mode here means that a circuit for controlling the input / output terminals of the functional block unit inside the semiconductor device consisting of a plurality of blocks to the input / output terminals of the outer peripheral portion of the semiconductor device is configured to Is a mode in which input information can be operated in block units inside the semiconductor device and output information can be observed.
【０００３】このテストモードの機能を構成するため
に、半導体装置の外周部の入出力制御回路には、本来の
半導体装置の実動作モード時の端子制御用の入出力信号
配線に加えて、テストモード用に各ブロックから入出力
信号配線と、テストするブロックの数だけのテストモー
ドを切り換える制御信号配線が存在する。In order to configure the function of this test mode, the input / output control circuit in the outer peripheral portion of the semiconductor device is provided with the test signal in addition to the input / output signal wiring for controlling the terminal in the actual operation mode of the original semiconductor device. For each mode, there are input / output signal wirings from each block and control signal wirings for switching the test mode by the number of blocks to be tested.
【０００４】また、入出力できるテスト用の信号配線数
は多ければ多いほどテスト性が向上するので、各ブロッ
クごとに半導体装置の外周部入出力回路の最大本数分ま
で利用できるように四辺に均等に振り分けられる。この
テストモード制御信号配線は、テストモード設定時に変
化するだけで半導体装置の動作時には一定状態の信号を
通すものなので、配線部の抵抗による信号遅延が大きく
てよく、テストモードは一般のユーザーには開放してい
ないので信号遅延が大きくても問題にならない。Further, the greater the number of input / output test signal wirings, the better the testability. Therefore, each block is evenly distributed on all four sides so that the maximum number of peripheral input / output circuits of the semiconductor device can be used. Be assigned to. Since this test mode control signal wiring only passes a signal in a constant state when the semiconductor device is operating, it changes only when the test mode is set. Since it is not opened, it does not matter even if the signal delay is large.
【０００５】また、従来の半導体装置の配線は、図２の
ＭＯＳ構造の半導体装置の例に示すように半導体装置基
板（図示していない）状を基板に近い方から、第１導体
層２６と、第１導体層との間に層間絶縁膜を介して設け
た第２導体層２１，２２で構成され、例えば縦方向の配
線群から任意の配線を横方向へ引き出すためには、縦方
向に並列に配線してある別の導体層と短絡しないよう
に、層間絶縁膜を開口して導体層を変えて配線する。そ
の配線は、配線抵抗の低い導体層を用いることにより配
線データの変化時間を保証している。また同一方向に延
びている配線群から任意の配線を任意の場所で垂直に引
き出すことを可能にするため、同一方向の配線群は同一
導体層で平行に配線されている。Further, the wiring of the conventional semiconductor device is such that the semiconductor device substrate (not shown) is connected to the first conductor layer 26 from the side closer to the substrate as shown in the example of the semiconductor device having the MOS structure of FIG. , The second conductor layers 21, 22 provided between the first conductor layer and the first conductor layer with an interlayer insulating film interposed therebetween. For example, in order to draw out any wiring from the wiring group in the vertical direction in the horizontal direction, In order not to short-circuit with another conductor layer that is wired in parallel, the interlayer insulating film is opened and the conductor layer is changed to perform wiring. The wiring uses a conductor layer having a low wiring resistance to guarantee the change time of the wiring data. Further, in order to allow any wiring to be vertically drawn out at any place from the wiring group extending in the same direction, the wiring groups in the same direction are wired in parallel in the same conductor layer.
【０００６】[0006]
【発明が解決しようとする課題】半導体装置に前記した
テストモード制御の機能を搭載することにより、テスト
モード制御用の信号配線が半導体装置外周部の四辺にテ
ストの種類分だけ配線されるので、テストモードを持た
ない同機能の半導体装置と比べて半導体装置の配線本数
が増加する。By mounting the above-described test mode control function in the semiconductor device, the signal wiring for the test mode control is wired on the four sides of the outer peripheral portion of the semiconductor device for each type of test. The number of wiring lines of the semiconductor device is increased as compared with the semiconductor device of the same function having no test mode.
【０００７】また、同一方向の複数の本数からなる配線
群は同一導体層で平行に配線されているため、その配線
が多ければ多いほど配線面積が増大してしまい、半導体
装置自体の面積を大きくしてしまうという問題点があ
る。Further, since a wiring group consisting of a plurality of wirings in the same direction are wired in parallel in the same conductor layer, the wiring area increases as the number of wirings increases, and the area of the semiconductor device itself increases. There is a problem that it does.
【０００８】[0008]
【課題を解決するための手段】本発明の半導体装置の配
線構造は、テストモード制御信号配線を第１導体層で形
成し、それと平行に配線される第２導体層で形成される
外周部トランジスタへの電源供給用配線の下にテストモ
ード制御信号配線を配置する。テストモード制御信号配
線と垂直に交差する信号配線がある部分は、交差する信
号配線を第１導体層で形成し、テストモード制御信号配
線を交差部分のみ高抵抗導体層で接続している。According to the wiring structure of a semiconductor device of the present invention, a test mode control signal wiring is formed of a first conductor layer and an outer peripheral transistor formed of a second conductor layer which is wired in parallel with the test mode control signal wiring. The test mode control signal wiring is arranged below the power supply wiring to the. In a portion where there is a signal wiring that intersects the test mode control signal wiring vertically, the intersecting signal wiring is formed by the first conductor layer, and the test mode control signal wiring is connected only by the high resistance conductor layer.
【０００９】[0009]
【実施例】次に本発明について図面を参照して説明す
る。図１は本発明の一実施例であるメタリ・オキサイド
・セミコンダクタ（Ｍｅｔａｌ・Ｏｘｉｄｅ．Ｓｅｍｉ
ｃｏｎｄｕｃｔｏｒ、以下ＭＯＳとする）構造の半導体
装置の外部出力バッファ部分の模式図である。ＭＯＳト
ランジスタ１２は、半導体基板（図示しない）に拡散層
１０ａ，１０ｂを形成し、ＭＯＳの電源供給部すなわち
ソース部は、第１コンタクト８ａにより層間絶縁膜を開
口し第１導体層１５ａに接続され、第１導体層１５ａと
第２導体層１の間の層間絶縁膜を開口する第２コンタク
ト１６ａにより、電源配線である第２導電層１と接続し
て形成される。ＭＯＳトランジスタ１２の出力部すなわ
ちドレイン部は、拡散層１０ｂと第１導体層１５ｂを層
間絶縁膜の開口を通して第１コンタクト８ｂにより接続
し、第１導体層１５ｂと半導体装置の外部と接続するた
めの端子であるパッド１１を層間絶縁膜の開口を通して
第２コンタクト１６ｂによって接続して構成される。Ｍ
ＯＳの制御ゲート層を構成するゲート用高抵抗導体層９
は第３コンタクト７によりゲート制御信号配線の第１導
体層５に接続される。The present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention, which is a metal oxide semiconductor (Metal Oxide. Semi).
FIG. 3 is a schematic view of an external output buffer portion of a semiconductor device having a structure of a capacitor (hereinafter referred to as a MOS). The MOS transistor 12 has diffusion layers 10a and 10b formed on a semiconductor substrate (not shown), and a power supply portion, that is, a source portion of the MOS is connected to the first conductor layer 15a by opening the interlayer insulating film by the first contact 8a. It is formed by being connected to the second conductive layer 1 which is the power supply wiring by the second contact 16a which opens the interlayer insulating film between the first conductor layer 15a and the second conductor layer 1. The output portion, that is, the drain portion of the MOS transistor 12 is for connecting the diffusion layer 10b and the first conductor layer 15b through the opening of the interlayer insulating film by the first contact 8b and connecting the first conductor layer 15b and the outside of the semiconductor device. The pad 11 which is a terminal is connected through the opening of the interlayer insulating film by the second contact 16b. M
High resistance conductor layer 9 for gate constituting OS control gate layer
Is connected to the first conductor layer 5 of the gate control signal wiring by the third contact 7.
【００１０】前述の電源供給用の第２導体層１は、外周
部ＭＯＳトランジスタ１２を並列に複数個分を同時に充
放電する可能性があるので、通常配線よりも幅を太くし
て電流容量を確保している。その電源供給用の第２導体
層１の下を、テストモード制御信号配線である第１導体
層２が通過している。第１導体層２と第２導体層１の間
は層間絶縁膜により絶縁されている。そのテストモード
制御信号配線の第１導体層２が同じく第１導体層からな
るＭＯＳのゲート制御をする通常信号配線の第１導体層
５と短絡しないように、第４コンタクト４で高抵抗導体
層３に接続して第１導体層５の下を非接触で通過する。Since the second conductor layer 1 for power supply described above may charge and discharge a plurality of peripheral MOS transistors 12 in parallel at the same time, the second conductor layer 1 should be thicker than the normal wiring to increase the current capacity. Have secured. The first conductor layer 2, which is a test mode control signal wire, passes under the second conductor layer 1 for power supply. The first conductor layer 2 and the second conductor layer 1 are insulated by an interlayer insulating film. In order to prevent the first conductor layer 2 of the test mode control signal wiring from short-circuiting with the first conductor layer 5 of the normal signal wiring that also controls the gate of the MOS formed of the first conductor layer, the high resistance conductor layer is formed by the fourth contact 4. 3 and passes under the first conductor layer 5 in a non-contact manner.
【００１１】以上のようにテストモード制御信号配線を
第１導体層２によって構成することにより、電源供給用
の第２導体層１と同一位置にテストモード制御信号配線
を通過させることができる。また、テストモード制御信
号配線を半導体装置内部に引き出すには、テストモード
制御信号配線の第１導体層２により第５コンタクト１３
で高抵抗導体層１４に接続して半導体装置内部に取り込
むことができる。By configuring the test mode control signal wiring by the first conductor layer 2 as described above, the test mode control signal wiring can be passed at the same position as the second conductor layer 1 for power supply. Further, in order to draw out the test mode control signal wiring into the semiconductor device, the fifth contact 13 is formed by the first conductor layer 2 of the test mode control signal wiring.
Can be incorporated into the semiconductor device by being connected to the high resistance conductor layer 14.
【００１２】[0012]
【発明の効果】以上説明したように本発明の半導体装置
の配線構造は、テストモード制御信号配線を第１導体層
で形成し、それと平行に配線される第２導体層で形成さ
れる外周部トランジスタへの電源供給用配線の下にテス
トモード制御信号配線を配置することにより、テストモ
ード制御信号配線部分の面積を小さくできるという効果
がある。また、これらの配線と垂直に交差する通常信号
配線がある場合には、その交差部分でテストモード制御
信号配線を高抵抗導体層で形成することにより通常配線
信号の抵抗を増加させることなく、従来と同様の配線が
できる。As described above, in the wiring structure of the semiconductor device of the present invention, the test mode control signal wiring is formed of the first conductor layer and the outer peripheral portion is formed of the second conductor layer which is wired in parallel with the test mode control signal wiring. By arranging the test mode control signal wiring under the power supply wiring to the transistor, there is an effect that the area of the test mode control signal wiring portion can be reduced. Also, if there is a normal signal wiring that intersects these wirings vertically, the test mode control signal wiring is formed of a high resistance conductor layer at the crossing portion without increasing the resistance of the normal wiring signal. Wiring similar to can be done.
【図１】本発明の一実施例のＭＯＳ型半導体装置の外部
出力回路部分の平面図である。FIG. 1 is a plan view of an external output circuit portion of a MOS semiconductor device according to an embodiment of the present invention.
【図２】従来のＭＯＳ型半導体装置の外部出力回路部分
の平面図である。FIG. 2 is a plan view of an external output circuit portion of a conventional MOS semiconductor device.
１ 電源用第２導体層 ２ テストモード制御信号用第１導体層 ３，１４ 高抵抗導体層 ４ 第４コンタクト ５ ゲート信号用第１導体層 ７ 第３コンタクト ８ａ，８ｂ 第１コンタクト ９ ゲート用高抵抗導体層 １０ａ，１０ｂ 拡散層 １１ パッド １２ ＭＯＳトランジスタ １５ａ，１５ｂ 第１導体層 １６ａ，１６ｂ 第２コンタクト 1 2nd conductor layer for power supply 2 1st conductor layer for test mode control signal 3,14 High resistance conductor layer 4 4th contact 5 1st conductor layer for gate signal 7 3rd contact 8a, 8b 1st contact 9 Gate height Resistance conductor layer 10a, 10b Diffusion layer 11 Pad 12 MOS transistor 15a, 15b First conductor layer 16a, 16b Second contact
Claims (2)
導体層、高抵抗導体層の多層構造を少なくとも有し、層
間に絶縁膜を有して開口部を通して各々接続される多層
積層配線型の半導体装置において、データ伝播遅延時間
が問題にならない制御信号配線を第１導体層で形成し、
これと平行に配線される外周部トランジスタの電源供給
配線を第２導体層で形成し、該電源供給配線の下にデー
タ伝播遅延時間が問題にならない制御信号配線を配置す
ることを特徴とする半導体装置の配線構造。1. A semiconductor device comprising a first conductor layer, a second conductor layer and a first conductor layer.
In a multi-layer laminated wiring type semiconductor device which has at least a multi-layer structure of a conductor layer and a high resistance conductor layer and which has an insulating film between layers and is connected to each other through an opening, control signal wiring in which a data propagation delay time does not matter Is formed of the first conductor layer,
A semiconductor characterized in that a power supply wiring of an outer peripheral transistor which is wired in parallel with this is formed of a second conductor layer, and a control signal wiring which does not pose a problem of data propagation delay time is arranged under the power supply wiring. Device wiring structure.
がある場合は、交差する信号配線を第１導体層で形成
し、制御信号配線を交差部分のみ高抵抗導体層で接続す
ることを特徴とする請求項１記載の半導体装置の配線構
造。2. When there is a signal wiring that intersects the control wiring vertically, the intersecting signal wiring is formed by a first conductor layer, and the control signal wiring is connected only by a high resistance conductor layer at the intersection. The wiring structure for a semiconductor device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32637192A JP2919207B2 (en) | 1992-12-07 | 1992-12-07 | Wiring structure of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32637192A JP2919207B2 (en) | 1992-12-07 | 1992-12-07 | Wiring structure of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06177251A true JPH06177251A (en) | 1994-06-24 |
| JP2919207B2 JP2919207B2 (en) | 1999-07-12 |
Family
ID=18187056
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32637192A Expired - Fee Related JP2919207B2 (en) | 1992-12-07 | 1992-12-07 | Wiring structure of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2919207B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7741862B2 (en) | 2006-12-14 | 2010-06-22 | Elpida Memory, Inc. | Semiconductor device including a signal generator activated upon occurring of a timing signal |
-
1992
- 1992-12-07 JP JP32637192A patent/JP2919207B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7741862B2 (en) | 2006-12-14 | 2010-06-22 | Elpida Memory, Inc. | Semiconductor device including a signal generator activated upon occurring of a timing signal |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2919207B2 (en) | 1999-07-12 |
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