JPH06177276A - Multilayer wiring board - Google Patents
Multilayer wiring boardInfo
- Publication number
- JPH06177276A JPH06177276A JP32635992A JP32635992A JPH06177276A JP H06177276 A JPH06177276 A JP H06177276A JP 32635992 A JP32635992 A JP 32635992A JP 32635992 A JP32635992 A JP 32635992A JP H06177276 A JPH06177276 A JP H06177276A
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring board
- hole
- multilayer wiring
- lower layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置を実装する際
に用いられる多層配線基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board used when mounting a semiconductor device.
【０００２】[0002]
【従来の技術】従来の多層配線基板について図２
（ａ），（ｂ）に示す平面図とＢ−Ｂ線断面図を用いて
説明する。2. Description of the Related Art A conventional multilayer wiring board is shown in FIG.
This will be described with reference to the plan views shown in FIGS.
【０００３】まず、アルミナセラミック（または金属や
半導体等）基板１上に第１絶縁膜としてエポキシ（また
はシリコン，ポリイミド等）樹脂膜２（または無機絶縁
膜）をスピンコート，デイップ，印刷法等により設け、
その上に第１密着金属としてＴｉ（またはＣｒ−Ｐｄ，
Ｔｉ−Ｗ等）膜３Ａと第１導体膜としてＡｕ膜４Ａを、
蒸着，スパッター，メッキ等の方法により形成したの
ち、リソグラフィー技術等を用いて下層の回路パターン
を形成する。その後、第２絶縁膜としてエポキシ（また
はシリコン，ポリイミド等）樹脂膜５Ａをスピンコー
ト，デイップ，印刷法等により設ける。First, an epoxy (or silicon, polyimide, etc.) resin film 2 (or an inorganic insulating film) is formed as a first insulating film on an alumina ceramic (or metal, semiconductor, etc.) substrate 1 by spin coating, dipping, printing or the like. Provided,
On top of that, Ti (or Cr-Pd,
Ti—W) film 3A and Au film 4A as the first conductor film,
After forming by a method such as vapor deposition, sputtering and plating, a lower layer circuit pattern is formed by using a lithography technique or the like. After that, an epoxy (or silicon, polyimide, etc.) resin film 5A is provided as a second insulating film by spin coating, dipping, printing or the like.
【０００４】次にこのエポシキ樹脂膜５Ａにスルーホー
ル６Ａをリソグラフィー技術により形成する。次に第２
密着金属膜として、例えば、Ｔｉ膜７Ａと第２導体膜と
してのＡｕ膜８Ａを蒸着，スパッタ，メッキ等の方法に
より設け、リソグラフィー技術によりパターニングして
上層配線を設ける。以上の操作を繰り返すことにより所
望の多層配線基板が完成する。Next, through holes 6A are formed in the epoxy resin film 5A by a lithography technique. Second
As the adhesion metal film, for example, a Ti film 7A and an Au film 8A as a second conductor film are provided by a method such as vapor deposition, sputtering and plating, and patterned by a lithography technique to provide an upper layer wiring. A desired multilayer wiring board is completed by repeating the above operation.
【０００５】ここで第１密着金属膜，第２密着金属膜，
第１導体膜および第２導体膜のパターン化と第２絶縁膜
へのスルーホールの形成には、パターンマスク（メタル
マスク，ガラスマスク，フィルムマスク等）とリソグラ
フィー技術が用いられる。従って密着金属膜および導体
膜のパターン寸法とスルーホールの寸法は、パターンマ
スク寸法によって決定されており、スルーホール６Ａの
寸法Ｘ２×Ｙ２はＡｕ膜４Ａの寸法ｘ２×ｙ２よりも小
さくなっている。Here, the first adhesion metal film, the second adhesion metal film,
A pattern mask (metal mask, glass mask, film mask, etc.) and a lithography technique are used for patterning the first conductor film and the second conductor film and forming a through hole in the second insulating film. Therefore, the pattern size of the contact metal film and the conductor film and the size of the through hole are determined by the pattern mask size, and the size X2 × Y2 of the through hole 6A is smaller than the size x2 × y2 of the Au film 4A.
【０００６】[0006]
【発明が解決しようとする課題】この従来の多層配線基
板では、下層配線のスルーホール部のパターン寸法より
もその上のスルーホールの寸法が小さくなっているた
め、下層配線のスルーホール部のパターンの周辺部には
第２絶縁膜としてのエポキシ樹脂膜が密着することにな
る。有機系または無機系の絶縁膜と導体膜としてＡｕ膜
を用いると密着性が良好でないため、図３に示すよう
に、例えばポリイミド樹脂膜５Ａに剥れが発生して下層
配線と上層配線とが短絡する。In this conventional multilayer wiring board, since the size of the through hole above it is smaller than the pattern size of the through hole portion of the lower layer wiring, the pattern of the through hole portion of the lower layer wiring is smaller. The epoxy resin film as the second insulating film is adhered to the peripheral portion of the. When an Au film is used as an organic or inorganic insulating film and a conductor film, the adhesion is not good. Therefore, as shown in FIG. 3, for example, peeling occurs in the polyimide resin film 5A and the lower layer wiring and the upper layer wiring are separated from each other. Short circuit.
【０００７】このように下層導体膜のスルーホール部の
パターン部と絶縁膜との剥れが発生することによって、
スルーホール部における電気・機械的接続が損なわれ多
層配線基板の信頼性及び歩留りが低下するという問題点
があった。As a result of the peeling between the insulating film and the pattern portion of the through-hole portion of the lower conductor film,
There is a problem that the electrical / mechanical connection in the through-hole portion is impaired and the reliability and yield of the multilayer wiring board are reduced.
【０００８】[0008]
【課題を解決するための手段】本発明の多層配線基板
は、基板上に絶縁層を介して設けられた複数層の配線を
有し、下層配線と上層配線とがスルーホールを介して接
続された多層配線基板において、スルーホール部におけ
る前記下層配線の接続用パターンの寸法がスルーホール
の寸法より小さく形成されていることを特徴とするもの
である。A multilayer wiring board of the present invention has a plurality of layers of wiring provided on the board via insulating layers, and the lower layer wiring and the upper layer wiring are connected via through holes. In the multi-layer wiring board, the dimension of the connection pattern of the lower layer wiring in the through hole portion is smaller than the dimension of the through hole.
【０００９】[0009]
【実施例】次に本発明について図面にもとづき説明す
る。図１（ａ），（ｂ）は本発明の一実施例を示す平面
図及びＡ−Ａ線断面図である。The present invention will be described below with reference to the drawings. 1 (a) and 1 (b) are a plan view and a sectional view taken along line AA showing an embodiment of the present invention.
【００１０】まずアルミナセラミック基板１（または金
属，半導体基板など）上に第１絶縁膜としてエポキシ
（またはシリコン，ポリイミド）樹脂膜２をスピコー
ト，印刷，デイップ等の方法を用いて所定の厚さ（例え
ば１．０〜２０μｍ）に形成する。次でこのエポキシ樹
脂膜２上に第１密着金属として厚さ１０〜１００ｎｍの
Ｔｉ膜３，第１導体膜として厚さ０．５〜１０μｍの金
（Ａｕ）膜４を順次、蒸着，スパッター，メッキ等の方
法により設け、更にリソグラフィー技術により所望の下
層回路パターンを形成する。この時後工程で形成するス
ルーホール部におけるパターン寸法はスルーホールの寸
法より小さいｘ１×ｙ１とする。次で密着性向上のため
一般的には密着強化剤，イオンビームエッチングおよび
プラズマアッシング等の各種前処理を実施する。First, an epoxy (or silicon, polyimide) resin film 2 as a first insulating film is formed on an alumina ceramic substrate 1 (or metal, semiconductor substrate, etc.) by a method such as spin coating, printing, or dipping to a predetermined thickness ( The thickness is, for example, 1.0 to 20 μm. Next, a Ti film having a thickness of 10 to 100 nm as a first adhesion metal 3 and a gold (Au) film 4 having a thickness of 0.5 to 10 μm as a first conductor film are sequentially deposited on the epoxy resin film 2 by vapor deposition, sputtering, It is provided by a method such as plating, and a desired lower layer circuit pattern is formed by a lithographic technique. At this time, the pattern size in the through hole portion formed in the subsequent process is set to x1 × y1 which is smaller than the size of the through hole. Next, various pretreatments such as adhesion enhancer, ion beam etching, and plasma ashing are generally performed to improve adhesion.
【００１１】その後第２絶縁膜として酸化シリコン膜５
（またはエポキシ系樹脂，シリコン系樹脂，ポリイミド
系樹脂，Ａｌ2 Ｏ3 膜等の無機系絶縁膜）を熱酸化（ま
たはスピンコート，印刷，デイップ，スパッター等）の
方法により形成する。更にＡｕ膜４との電気的・機械的
接続用のスルーホール６をＡｕ膜４の寸法ｘ１×ｙ１よ
り大きい寸法Ｘ１×Ｙ１で所望の場所にリソグラフィー
技術を用いて形成する。After that, a silicon oxide film 5 is formed as a second insulating film.
(Or an epoxy resin, a silicon resin, a polyimide resin, an inorganic insulating film such as an Al 2 O 3 film) is formed by a method of thermal oxidation (or spin coating, printing, dipping, sputtering, etc.). Further, a through hole 6 for electrical / mechanical connection with the Au film 4 is formed in a desired place by a lithography technique with a size X1 × Y1 larger than the size x1 × y1 of the Au film 4.
【００１２】次に密着強化剤，イオンビームエッチング
およびプラズマアッシング等の前処理を実施した後、速
やかに第２密着金属膜としてＴｉ膜７および第２導体膜
としてＡｕ膜８を蒸着，スパッター，メッキ等の方法に
より形成する。その後、リソグラフィー技術を用いてパ
ターン化し上層配線を形成する。Next, after performing a pretreatment such as an adhesion enhancer, ion beam etching and plasma ashing, a Ti film 7 as a second adhesion metal film and an Au film 8 as a second conductor film are immediately deposited, sputtered and plated. And the like. After that, the upper wiring is patterned by using the lithography technique.
【００１３】以上説明した工程を経過して１つのスルー
ホール接続構造が完成する。尚、多層配線基板について
は以上述べた工程の繰り返しにより必要な導体層数を形
成する。One through-hole connection structure is completed after the above-described steps. For the multilayer wiring board, the required number of conductor layers is formed by repeating the above-mentioned steps.
【００１４】このように構成された本実施例によれば、
下層配線を構成するＡｕ膜４のスルーホール部のパター
ン寸法ｘ１×ｙ１はスルーホールの寸法Ｘ１×Ｙ１より
小さくなっているため、酸化シリコン膜５が下層配線を
構成するＡｕ膜４のスルーホール部のパターン上に乗る
ようになることはほとんどなくなる。従って従来のよう
に、スルーホール部で酸化シリコン膜５が剥れることは
ない。このためスルーホール部における下層配線と上層
配線との電気的・機械的な断線等の不具合は防止され、
安定した信頼性の高いスルーホール接続が得られる。According to the present embodiment thus constructed,
Since the pattern dimension x1 × y1 of the through hole portion of the Au film 4 forming the lower layer wiring is smaller than the dimension X1 × Y1 of the through hole, the silicon oxide film 5 forms the through hole portion of the Au film 4 forming the lower layer wiring. You almost never get on the pattern. Therefore, unlike the conventional case, the silicon oxide film 5 is not peeled off at the through holes. Therefore, problems such as electrical / mechanical disconnection between the lower layer wiring and the upper layer wiring in the through hole portion are prevented,
A stable and reliable through-hole connection can be obtained.
【００１５】またスルーホール部の形状が本実施例では
正方形となっているが、長方形，円形，多角形（各々図
示せず）に於いても以上述べた効果が得られ実施が可能
である。基板として金属，アルミナセラミック，半導体
を、第１絶縁膜にポリイミド樹脂膜を、第１導体膜とし
てＡｕ膜を、第２絶縁膜にポリイミド樹脂膜を、そして
第２導体膜にＡｕ膜をそれぞれ用いた場合、特に本発明
の効果が発揮される。Although the shape of the through hole is square in this embodiment, the effect described above can be obtained and practiced in the case of a rectangle, a circle, or a polygon (each not shown). The substrate is made of metal, alumina ceramic, or semiconductor, the first insulating film is a polyimide resin film, the first conductive film is an Au film, the second insulating film is a polyimide resin film, and the second conductive film is an Au film. If so, the effect of the present invention is particularly exerted.
【００１６】これは、第１絶縁膜のポリイミド樹脂膜と
第２絶縁膜のポリイミド樹脂膜間の密着性向上は、第１
絶縁膜としてのポリイミド樹脂膜の表面処理（例えばプ
ラズマ処理，密着強化剤処理等）により容易に可能であ
る。しかしながら第１導体膜としてのＡｕ膜と第２絶縁
膜としてのポリイミド樹脂膜間の密着性向上策として、
Ａｕ膜の表面処理（例えばプラズマ処理，密着強化剤処
理，イオンビームエッチング等）が実施されているが非
常に不安定であり、難しい工程管理とチェックが必要で
あるのが現状である。これは導体層として使用する金が
安定であり、ポリイミドと例えば、界面反応を起こすこ
とがないという本質上の理由からである。This is because the adhesion between the polyimide resin film of the first insulating film and the polyimide resin film of the second insulating film is improved by the first
This can be easily performed by surface treatment (for example, plasma treatment, adhesion enhancer treatment, etc.) of the polyimide resin film as the insulating film. However, as a measure for improving the adhesion between the Au film as the first conductor film and the polyimide resin film as the second insulating film,
The surface treatment of the Au film (for example, plasma treatment, adhesion enhancer treatment, ion beam etching, etc.) is carried out, but it is very unstable, and it is the current situation that difficult process control and check are required. This is because the gold used as the conductor layer is stable and does not cause an interfacial reaction with the polyimide, for example.
【００１７】[0017]
【発明の効果】以上説明したように本発明は、下層配線
のスルーホール部のパターン寸法よりもその上に設けら
れる絶縁膜のスルーホールの寸法が小さくなっているた
め、下層配線のスルーホール部には絶縁膜がほとんど付
着しないことになる。従ってスルーホール部に於いて下
層配線と絶縁膜間の密着が不安定な組み合わせを実施し
ても下層配線と絶縁膜間の剥れは発生しない。その結
果、スルーホール部における上層配線と下層配線の接続
は安定したものとなるため、信頼性及び歩留りの向上し
た多層配線基板が得られるという効果がある。As described above, according to the present invention, the dimension of the through hole of the insulating film provided thereon is smaller than the pattern dimension of the through hole portion of the lower layer wiring, so that the through hole portion of the lower layer wiring is formed. Almost no insulating film is attached to the. Therefore, even if a combination in which the adhesion between the lower layer wiring and the insulating film is unstable in the through hole portion is carried out, peeling between the lower layer wiring and the insulating film does not occur. As a result, the connection between the upper layer wiring and the lower layer wiring in the through-hole portion becomes stable, so that there is an effect that a multilayer wiring board with improved reliability and yield can be obtained.
【図１】本発明の一実施例の平面図及び断面図。FIG. 1 is a plan view and a sectional view of an embodiment of the present invention.
【図２】従来の多層配線基板の平面図及び断面図。2A and 2B are a plan view and a cross-sectional view of a conventional multilayer wiring board.
【図３】従来の多層配線基板の欠点を説明するための断
面図。FIG. 3 is a sectional view for explaining a defect of a conventional multilayer wiring board.
１ アルミナセラミック基板 ２ エポキシ樹脂膜 ３，３Ａ Ｔｉ膜 ４，４Ａ Ａｕ膜 ５，５Ａ 酸化シリコン膜 ６，６Ａ スルーホール ７，７Ａ Ｔｉ膜 ８，８Ａ Ａｕ膜 1 Alumina Ceramic Substrate 2 Epoxy Resin Film 3, 3A Ti Film 4, 4A Au Film 5, 5A Silicon Oxide Film 6, 6A Through Hole 7, 7A Ti Film 8, 8A Au Film
Claims (3)
層の配線を有し、下層配線と上層配線とがスレーホール
を介して接続された多層配線基板において、スルーホー
ル部における前記下層配線の接続用パターンの寸法がス
ルーホールの寸法より小さく形成されていることを特徴
とする多層配線基板。1. A multilayer wiring board having a plurality of layers of wiring provided on a substrate via an insulating layer, wherein the lower layer wiring and the upper layer wiring are connected via a sleyhole, and the lower layer wiring in a through hole portion. The multilayer wiring board is characterized in that the size of the connection pattern is formed smaller than the size of the through hole.
載の多層配線基板。2. The multilayer wiring board according to claim 1, wherein the main material of the lower layer wiring is gold.
形，円形または多角形である請求項１記載の多層配線基
板。3. The multilayer wiring board according to claim 1, wherein the planar shape of the through hole is a square, a rectangle, a circle or a polygon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32635992A JP2825050B2 (en) | 1992-12-07 | 1992-12-07 | Multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32635992A JP2825050B2 (en) | 1992-12-07 | 1992-12-07 | Multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06177276A true JPH06177276A (en) | 1994-06-24 |
| JP2825050B2 JP2825050B2 (en) | 1998-11-18 |
Family
ID=18186918
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32635992A Expired - Fee Related JP2825050B2 (en) | 1992-12-07 | 1992-12-07 | Multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2825050B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998027795A1 (en) * | 1996-12-17 | 1998-06-25 | Hokuriku Electric Industry Co., Ltd. | Circuit board having electric component and its manufacturing method |
-
1992
- 1992-12-07 JP JP32635992A patent/JP2825050B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998027795A1 (en) * | 1996-12-17 | 1998-06-25 | Hokuriku Electric Industry Co., Ltd. | Circuit board having electric component and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2825050B2 (en) | 1998-11-18 |
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|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19980811 |
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