JPH06180332A - Current detection circuit - Google Patents
Current detection circuitInfo
- Publication number
- JPH06180332A JPH06180332A JP4332586A JP33258692A JPH06180332A JP H06180332 A JPH06180332 A JP H06180332A JP 4332586 A JP4332586 A JP 4332586A JP 33258692 A JP33258692 A JP 33258692A JP H06180332 A JPH06180332 A JP H06180332A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- current
- current detection
- output
- active load
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 title claims description 24
- 238000010276 construction Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0027—Measuring means of, e.g. currents through or voltages across the switch
Landscapes
- Measurement Of Current Or Voltage (AREA)
- Emergency Protection Circuit Devices (AREA)
- Electronic Switches (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】大電流を流す電力用トランジスタ
の負荷電流の検出方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for detecting a load current of a power transistor that allows a large current to flow.
【0002】[0002]
【従来の技術】従来のこの種の検出回路は、図5
(a),(b)に示す通り主電流(出力電流Ioのほと
んど)を出力するトランジスタQ1(またはQ1b)
と、それにドレイン(またはコレクタ)および制御電極
(ゲートまたはベース)が共通接続され、前記トランジ
スタQ1(またはQ1b)と特性相似な小さい電流検出
用トランジスタQ2(またはQ2b)とで構成され、ド
レイン(またはコレクタ)は出力端子に接続され、制御
電極(ゲートまたはベース)は制御入力端子に接続さ
れ、トランジスタQ2のソース(またはトランジスタQ
2bのエミッタ)とトランジスタQ1のドレイン(また
はトランジスタQ1bのエミッタ)の間に電流検出用抵
抗Rsが接続され、トランジスタQ1のソース(または
トランジスタQ1bのエミッタ)はGNDに接続されて
いた。2. Description of the Related Art A conventional detection circuit of this type is shown in FIG.
A transistor Q1 (or Q1b) that outputs a main current (most of the output current Io) as shown in (a) and (b).
And a drain (or collector) and a control electrode (gate or base) connected in common to the transistor Q1 (or Q1b) and a small current detecting transistor Q2 (or Q2b) having similar characteristics, and a drain (or The collector) is connected to the output terminal, the control electrode (gate or base) is connected to the control input terminal, and the source of transistor Q2 (or transistor Q2).
The current detection resistor Rs was connected between the emitter of 2b) and the drain of the transistor Q1 (or the emitter of the transistor Q1b), and the source of the transistor Q1 (or the emitter of the transistor Q1b) was connected to GND.
【0003】この動作は電流検出用抵抗Rsが小さい
時、トランジスタQ1とトランジスタQ2(またはトラ
ンジスタQ1bとトランジスタQ2b)はカレントミラ
ー動作となり、出力端に流れる電流Ioはトランジスタ
Q1(またはQ1b)、トランジスタQ2(またはQ2
b)の相対比をN:1とするとトランジスタQ2(また
はQ2b)には、Io/(N+1)の電流が流れる。こ
こでNが1に比べて非常に大きいときは、Io/Nとな
る。In this operation, when the current detecting resistor Rs is small, the transistors Q1 and Q2 (or the transistors Q1b and Q2b) become a current mirror operation, and the current Io flowing through the output terminal is the transistor Q1 (or Q1b) and the transistor Q2. (Or Q2
When the relative ratio of b) is N: 1, a current of Io / (N + 1) flows in the transistor Q2 (or Q2b). Here, when N is much larger than 1, it becomes Io / N.
【0004】電流検出用抵抗Rsの両端には検出電圧
(Vs) Vs=Io・1/N・Rs が得られることになる。A detection voltage (Vs) Vs = Io.1 / N.Rs is obtained across the current detection resistor Rs.
【0005】[0005]
【発明が解決しようとする課題】図5の従来例によると
電流検出用トランジスタQ2(またはQ2b)に流れる
電流はRs=0の時に出力電流Ioに比例することにな
り、検出電圧Vsを大きくしたい場合Rsは実用的な値
をてることになり、比例関係が崩れ、検出制度が悪いと
いう欠点を有していた。According to the conventional example of FIG. 5, the current flowing through the current detecting transistor Q2 (or Q2b) is proportional to the output current Io when Rs = 0, and it is desired to increase the detection voltage Vs. In this case, Rs had a practical value, and the proportional relationship was broken and the detection accuracy was poor.
【0006】これはトランジスタQ2のゲート・ソース
電位またはトランジスタQ2bのベース・エミッタ間電
位が電流検出電圧Vs分低くなるためである。This is because the gate-source potential of the transistor Q2 or the base-emitter potential of the transistor Q2b is lowered by the current detection voltage Vs.
【0007】[0007]
【課題を解決するための手段】この発明ではトランジス
タQ1(またはQ1b)とQ2(またはQ2b)の動作
条件、すなわちゲート・ソース間(またはベース・エミ
ッタ間)電圧およびドレイン・ソース間(またはコレク
タ・エミッタ間)電圧が等しくなるよう作用する能動負
荷をトランジスタQ2(またはQ2b)の負荷とし、能
動負荷の出力電流が出力電流に比例する構成とし、その
電流を電流検出抵抗に流し電流検出電圧を得る構成とし
た。According to the present invention, the operating conditions of the transistors Q1 (or Q1b) and Q2 (or Q2b), that is, the gate-source (or base-emitter) voltage and the drain-source (or collector- An active load that acts so as to make the voltages between the emitters equal is used as the load of the transistor Q2 (or Q2b), and the output current of the active load is proportional to the output current. It was configured.
【0008】[0008]
【作用】上記構成によるとトランジスタQ1(またはQ
1b)とトランジスタQ2(またはQ2b)の相対比1
/Nのほぼ完全に比例した大きな検出電圧を電流検出用
抵抗両端に発生できる。According to the above structure, the transistor Q1 (or Q
1b) and the transistor Q2 (or Q2b) relative ratio 1
A large detection voltage which is almost completely proportional to / N can be generated across the current detection resistor.
【0009】[0009]
【実施例】図1(a)に第1の実施例を示す。Q1は主
電流出力用NチャンネルMOSトランジスタ、Q2は電
流検出用NチャンネルMOSトランジスタであり、相対
比はN:1に設定されている。ドレインは共通接続され
電源端子に、ゲートは共通接続され制御入力端に、トラ
ンジスタQ1のソースは出力端に接がれ,外部でGND
との間に負荷が接がれてる。トランジスタQ2のソース
には能動負荷Aの電流を出力するNチャンネルのMOS
トランジスタQ3のドレインが接続され、トランジスタ
Q3のソースは電流検出用抵抗Rsを介しGNDに接続
されている。EXAMPLE FIG. 1A shows a first example. Q1 is an N-channel MOS transistor for main current output, Q2 is an N-channel MOS transistor for current detection, and the relative ratio is set to N: 1. The drain is commonly connected to the power supply terminal, the gate is commonly connected to the control input terminal, and the source of the transistor Q1 is connected to the output terminal.
There is a load between and. The source of the transistor Q2 is an N-channel MOS that outputs the current of the active load A.
The drain of the transistor Q3 is connected, and the source of the transistor Q3 is connected to GND through the current detection resistor Rs.
【0010】トランジスタQ3のゲートは演算増幅器O
Pの出力が接がれ、演算増幅器OPの+入力端はトラン
ジスタQ2のソース、−入力端はトランジスタQ1のソ
ースに接続されている。The gate of the transistor Q3 is an operational amplifier O.
The output of P is connected, the + input terminal of the operational amplifier OP is connected to the source of the transistor Q2, and the − input terminal of the operational amplifier OP is connected to the source of the transistor Q1.
【0011】本構成によれば、外部負荷による負荷電流
Ilが変化し、トランジスタQ1のドレイン・ソース間
電圧変化しても、トランジスタQ1とQ2のソース電位
が常に等しくなるように演算増幅器OPはトランジスタ
Q3のゲートを制御するので、トランジスタQ1,Q2
は理想に近いカレントミラー動作をし、トランジスタQ
2にIL /Nなる電流を流すことができる。従って電流
検出抵抗Rsの両端には検出電圧(Vs)として Vs=IL /N×RS が得られる。According to this structure, even if the load current Il due to the external load changes and the drain-source voltage of the transistor Q1 changes, the source potentials of the transistors Q1 and Q2 are always equal to each other. Since the gate of Q3 is controlled, transistors Q1 and Q2
Performs a current mirror operation close to ideal, and transistor Q
A current of I L / N can be applied to 2. Therefore, Vs = I L / N × RS is obtained as a detection voltage (Vs) across the current detection resistor Rs.
【0012】図1(b)はNチャンネルMOSトランジ
スタQ1,Q2にかえてNPNトランジスタQ1b,Q
2bを用いた例である。In FIG. 1B, NPN transistors Q1b and Q1 are used instead of N channel MOS transistors Q1 and Q2.
This is an example using 2b.
【0013】動作については図1(a)に示す例と類似
するので説明は略す。Since the operation is similar to that of the example shown in FIG. 1A, the description thereof will be omitted.
【0014】[0014]
【実施例2】図2(a),(b)に第2の実施例を示す
が、(a)はPチャンネルMOSトランジスタQ1,Q
2のソースが共通接続され、電源にドレインがそれぞれ
出力端および能動負荷Aの電流出力用トランジスタQ3
のドレインに接続される点が異なり、この場合はトラン
ジスタQ1,Q2のドレイン電圧が等しくなるよう演算
増幅器OPおよびトランジスタQ3が作用することにな
る。[Embodiment 2] FIGS. 2A and 2B show a second embodiment, in which FIG. 2A shows P channel MOS transistors Q1 and Q.
The two sources are connected in common, and the drain is connected to the power source at the output terminal and the current output transistor Q3 of the active load A, respectively.
Of the operational amplifier OP and the transistor Q3 so that the drain voltages of the transistors Q1 and Q2 are equal to each other.
【0015】同図bはPチャンネルMOSトランジスタ
Q1,Q2をPNPトランジスタQ1b,q2bとした
例で、動作は図2(a)の例と類似するので説明は省略
する。FIG. 2B shows an example in which the P-channel MOS transistors Q1 and Q2 are PNP transistors Q1b and q2b. The operation is similar to the example of FIG.
【0016】[0016]
【実施例3】図3(a),(B)に第3の実施例を示
す。実施例1,2と違う点はトランジスタQ1(または
Q1b)、Q2(またはQ2b)がGND側に配された
点およびそれに伴い能動負荷Aを構成する電流出力用ト
ランジスタQ3がPチャンネルMOSトランジスタにな
り、電流検出用対向Rsが電源側に接続された点であ
る。動作については同様であるので省略する。[Third Embodiment] FIGS. 3A and 3B show a third embodiment. The difference from the first and second embodiments is that the transistors Q1 (or Q1b) and Q2 (or Q2b) are arranged on the GND side, and accordingly, the current output transistor Q3 forming the active load A is a P-channel MOS transistor. The point where the counter Rs for current detection is connected to the power supply side. Since the operation is similar, it will be omitted.
【0017】[0017]
【実施例4】図4に第4の実施例を示す。本回路は第1
の実施例の能動負荷Aの電流出力用トランジスタQ3の
ソースを直接GNDに結び、トランジスタQ3とゲート
およびソースが共通接続されたトランジスタQ4を設
け,Q4のドレインと電源の間に電流検出用抵抗Rsを
挿入した例でトランジスタQ3に流れる電流に比例した
電流がトランジスタQ4より得られる構成を取ったもの
である。Fourth Embodiment FIG. 4 shows a fourth embodiment. This circuit is the first
The source of the current output transistor Q3 of the active load A of the above embodiment is directly connected to GND, and a transistor Q4 having a gate and a source commonly connected to the transistor Q3 is provided. In the example in which is inserted, a current proportional to the current flowing in the transistor Q3 is obtained from the transistor Q4.
【0018】本構成は第2〜第4の実施例においても同
様に構成することができる。This construction can be similarly constructed in the second to fourth embodiments.
【0019】[0019]
【発明の効果】以上説明したように、本発明による構成
を取ることにより高効率かつ構成度で負荷電流に比例し
た電流検出電圧を取り出すことができる。As described above, by adopting the configuration according to the present invention, the current detection voltage proportional to the load current can be taken out with high efficiency and degree of configuration.
【図1】 第1の実施例FIG. 1 is a first embodiment.
【図2】 第2の実施例[FIG. 2] Second embodiment
【図3】 第3の実施例FIG. 3 Third embodiment
【図4】 第4の実施例FIG. 4 is a fourth embodiment.
【図5】 従来例FIG. 5 Conventional example
Q1,Q1b 出力トランジスタ Q2,Q2b 電流検出用トランジスタ Q3 能動負荷電流出力トランジスタ Q4 能動負荷電流分流トランジスタ OP 演算増幅回路 A 能動負荷回路 Rs 電流検出用抵抗 Q1, Q1b output transistor Q2, Q2b current detection transistor Q3 active load current output transistor Q4 active load current shunt transistor OP operational amplifier circuit A active load circuit Rs current detection resistor
Claims (3)
さいがそれに特性相似な電流検出用の第2のトランジス
タを有し、前記両トランジスタは制御電極(ゲートまた
はベース)が共通接続され、ドレイン(またはコレク
タ)かソース(またはエミッタ)かの一方が共通接続さ
れて電源の一方に接続され、前記第1のトランジスタの
他方は負荷を介して電源の他方に接続され、前記第2の
トランジスタの他方は能動負荷を介して電源の他方に接
続されてなり、前記能動負荷は前記第2のトランジスタ
の他方の電位を前記第1のトランジスタの他方の電位と
等しくするものであることを特徴とする電流検出回路。1. A first transistor that outputs a main current, and a second transistor for current detection that is small but similar in characteristics to the first transistor. The second transistor has a control electrode (gate or base) commonly connected and a drain. (Or collector) or source (or emitter) is commonly connected to one of the power supplies, the other of the first transistors is connected to the other of the power supplies via a load, and The other is connected to the other of the power supply through an active load, and the active load makes the other potential of the second transistor equal to the other potential of the first transistor. Current detection circuit.
ジスタと電源がわに配置した電流検出用抵抗との直列回
路である請求項1の電流検出回路。2. The current detection circuit according to claim 1, wherein the active load is a series circuit of a third transistor for current output and a current detection resistor arranged in the power source.
とミラー接続する相似な第4のトランジスタを設け、第
4のトランジスタの出力端子に能動負荷出力電流検出用
抵抗を挿入した請求項1に記載の電流検出回路。3. A third transistor for current output of an active load, a similar fourth transistor mirror-connected to the third transistor is provided, and an active load output current detection resistor is inserted in the output terminal of the fourth transistor. The described current detection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4332586A JPH06180332A (en) | 1992-12-14 | 1992-12-14 | Current detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4332586A JPH06180332A (en) | 1992-12-14 | 1992-12-14 | Current detection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06180332A true JPH06180332A (en) | 1994-06-28 |
Family
ID=18256594
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4332586A Pending JPH06180332A (en) | 1992-12-14 | 1992-12-14 | Current detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06180332A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1298106C (en) * | 2003-07-16 | 2007-01-31 | 恩益禧电子股份有限公司 | Power supply control apparatus including highly-reliable overcurrent detecting circuit |
| JP2007174788A (en) * | 2005-12-21 | 2007-07-05 | Denso Corp | Current detector and current controller |
| US7245116B2 (en) | 2004-04-14 | 2007-07-17 | Renesas Technology Corp. | Power supply device and switching power supply device |
| US7248452B2 (en) | 2002-07-12 | 2007-07-24 | Yazaki Corporation | Method of protecting semiconductor device and protection apparatus for semiconductor device using the same |
| JP2008112251A (en) * | 2006-10-30 | 2008-05-15 | Ricoh Co Ltd | Current detection circuit and voltage regulator having current detection circuit |
| JP2009075957A (en) * | 2007-09-21 | 2009-04-09 | Renesas Technology Corp | Power circuit and semiconductor device |
| CN102539887A (en) * | 2012-01-18 | 2012-07-04 | 范示德汽车技术(上海)有限公司 | Fan current detection method |
| CN105450022A (en) * | 2016-01-15 | 2016-03-30 | 上海铄梵电子科技有限公司 | Difference PWM modulator and current-mode DC-DC converter based on the modulator |
| WO2020095561A1 (en) * | 2018-11-06 | 2020-05-14 | 日立オートモティブシステムズ株式会社 | Load driving device, and transmission drive system |
-
1992
- 1992-12-14 JP JP4332586A patent/JPH06180332A/en active Pending
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7248452B2 (en) | 2002-07-12 | 2007-07-24 | Yazaki Corporation | Method of protecting semiconductor device and protection apparatus for semiconductor device using the same |
| US7626792B2 (en) | 2003-07-16 | 2009-12-01 | Nec Electronics Corporation | Power supply control apparatus including highly-reliable overcurrent detecting circuit |
| CN1298106C (en) * | 2003-07-16 | 2007-01-31 | 恩益禧电子股份有限公司 | Power supply control apparatus including highly-reliable overcurrent detecting circuit |
| US7245116B2 (en) | 2004-04-14 | 2007-07-17 | Renesas Technology Corp. | Power supply device and switching power supply device |
| US7342391B2 (en) | 2004-04-14 | 2008-03-11 | Renesas Technology Corp. | Power supply device and switching power supply device |
| US7550959B2 (en) | 2004-04-14 | 2009-06-23 | Renesas Technology Corp. | Power supply device and switching power supply device |
| JP2007174788A (en) * | 2005-12-21 | 2007-07-05 | Denso Corp | Current detector and current controller |
| JP2008112251A (en) * | 2006-10-30 | 2008-05-15 | Ricoh Co Ltd | Current detection circuit and voltage regulator having current detection circuit |
| JP2009075957A (en) * | 2007-09-21 | 2009-04-09 | Renesas Technology Corp | Power circuit and semiconductor device |
| CN102539887A (en) * | 2012-01-18 | 2012-07-04 | 范示德汽车技术(上海)有限公司 | Fan current detection method |
| CN105450022A (en) * | 2016-01-15 | 2016-03-30 | 上海铄梵电子科技有限公司 | Difference PWM modulator and current-mode DC-DC converter based on the modulator |
| WO2020095561A1 (en) * | 2018-11-06 | 2020-05-14 | 日立オートモティブシステムズ株式会社 | Load driving device, and transmission drive system |
| JPWO2020095561A1 (en) * | 2018-11-06 | 2021-09-24 | 日立Astemo株式会社 | Load drive and transmission drive system |
| US11881846B2 (en) | 2018-11-06 | 2024-01-23 | Hitachi Astemo, Ltd. | Load drive device and transmission drive system |
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