JPH061832B2 - Input/Output Protection Device - Google Patents
Input/Output Protection DeviceInfo
- Publication number
- JPH061832B2 JPH061832B2 JP56162261A JP16226181A JPH061832B2 JP H061832 B2 JPH061832 B2 JP H061832B2 JP 56162261 A JP56162261 A JP 56162261A JP 16226181 A JP16226181 A JP 16226181A JP H061832 B2 JPH061832 B2 JP H061832B2
- Authority
- JP
- Japan
- Prior art keywords
- igfet
- voltage
- protection
- gate
- protective
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
- H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
Landscapes
- Amplifiers (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Protection Of Static Devices (AREA)
Description
【発明の詳細な説明】 本発明は絶縁ゲート型電界効果トランジスタ(以下IGFE
Tという)の保護装置の改良に関するものである。Detailed Description of the Invention The present invention relates to an insulated gate field effect transistor (hereinafter referred to as IGFE
This concerns improvements to protective devices for the EV-100 (called T).
IGFETの閾値電圧及び電圧利得の如き電気的性能を良く
するにはゲート絶縁膜を薄くする方が良い。しかしゲー
ト絶縁膜を薄くすると絶縁耐圧が低下し、例えばゲート
絶縁膜として500Å程度のシリコン酸化膜を用いた場
合には60V程度の電圧により永久的な破壊を受けるよ
うになる。このような破壊からゲート絶縁膜を保護する
ものとして例えば第1図の保護装置が従来使用されてき
た。To improve the electrical performance of an IGFET, such as its threshold voltage and voltage gain, it is better to make the gate insulating film thinner. However, making the gate insulating film thinner reduces the dielectric strength, and for example, when a silicon oxide film of about 500 Å is used as the gate insulating film, it will be permanently destroyed by a voltage of about 60 V. To protect the gate insulating film from such destruction, a protection device such as that shown in Fig. 1 has been used in the past.
最初に第1図の従来例について働きを説明する。以下、
Nチャンネルの入力保護装置として説明する。First, the operation of the conventional example shown in FIG.
It will be described as an N-channel input protection device.
第1図において被保護用IGFET101のゲートは保護用I
GFET102のソースに接続されその保護用IGFET102
のドレインが抵抗体111を介して入力端子11に接続さ
れている。保護用IGFET102は通常は被保護用IGFET1
01と同じ製法で製造されゲート絶縁膜厚は被保護用IG
FET101のそれと等しい。保護用IGFET102のゲート
は定電源電圧供給用配線13に接続点12で接続されて
いる。この第1図の従来例の保護装置においては、入力
端子11に印加された電圧が定電源電圧供給用配線13
の電位から保護用IGFET102の閾値電圧を引いた電圧
よりも小さい時には保護用IGFET102ソース・ドレイ
ン間は導通状態となり被保護用IGFET101は正常に動作す
る。逆に入力端子11に印加された電圧が定電源電圧供
給用配線13の電位から保護用IGFET102の閾値電圧を引
いた電圧よりも大きい場合には、保護用IGFET102はゲー
ト・ソース間の電位差が減少し非導通状態に近づく為被
保護用IGFET101のゲートには定電源電圧供給用配線13
の電位より保護用IGFET102の閾値電圧を引いた値しか印
加されず、入力端子に過大電圧が印加された場合でも被
保護用IGFET101はゲート膜破壊から保護される。また、
保護用、IGFET102のドレインとゲート間にかかる電圧は
入力端子に印加された電圧から定電源電圧供給用配線1
3の電位を引いたものとなり、その結果従来例の第1図
の保護回路の破壊電圧は、IGFET101のゲートに直接
電圧が印加された場合よりも13の電位分だけ上昇す
る。しかしながら、この第1図の従来例の保護装置で
は、スパイク状のパルス電圧が印加された場合には保護
用IGFET102のゲート絶縁膜がドレイン近傍で破壊さ
れてしまうという欠点があった。例えば、ゲート酸化膜
500Åのシリコン酸化膜を用いた第1図の従来例の保
護装置では、抵抗体111の抵抗値を1kΩとして、2
00pFの容量に高電圧を充電し、この電圧を水銀接点
リレーを用いて印加した場合に150V程度のスパイク
状電圧で保護用、IGFETが破壊してしまうことがわ
かった。In FIG. 1, the gate of the protected IGFET 101 is connected to the protective I
A protective IGFET 102 is connected to the source of the GFET 102.
The drain of the protective IGFET 102 is connected to the input terminal 11 via a resistor 111.
Manufactured using the same manufacturing method as 01, the gate insulating film thickness is IG
The gate of the protection IGFET 102 is connected to the constant power supply voltage supply line 13 at a connection point 12. In the protection device of the conventional example shown in FIG.
When the voltage applied to the input terminal 11 is smaller than the voltage obtained by subtracting the threshold voltage of the protection IGFET 102 from the potential of the constant power supply voltage supply wiring 13, the source-drain of the protection IGFET 102 becomes conductive and the protected IGFET 101 operates normally. Conversely, when the voltage applied to the input terminal 11 is larger than the voltage obtained by subtracting the threshold voltage of the protection IGFET 102 from the potential of the constant power supply voltage supply wiring 13, the potential difference between the gate and source of the protection IGFET 102 decreases and approaches a non-conductive state, so that the gate of the protected IGFET 101 is connected to the constant power supply voltage supply wiring 13.
Therefore, even if an excessive voltage is applied to the input terminal, the protected IGFET 101 is protected from gate film destruction.
For protection, the voltage applied between the drain and gate of IGFET 102 is determined by the voltage applied to the input terminal and the constant power supply voltage supply line 1.
As a result, the breakdown voltage of the conventional protection circuit of Fig. 1 is higher by a potential of 13 than when a voltage is applied directly to the gate of IGFET 101. However, the conventional protection device of Fig. 1 has a drawback in that the gate insulating film of protection IGFET 102 is broken down near the drain when a spike-like pulse voltage is applied. For example, in the conventional protection device of Fig. 1 using a silicon oxide film with a gate oxide film of 500 Å, the resistance value of resistor 111 is set to 1 kΩ, and
It was found that when a high voltage was charged to a capacitance of 0.00 pF and this voltage was applied using a mercury contact relay, a spike voltage of about 150 V destroyed the protective IGFET.
本発明は前述した従来例における保護用IGFET102の
破壊を防止する手段を設けることにより従来の保護装置
の場合より更に高いスパイク状の過大電圧の入力まで耐
えることのできる保護装置を提供することを目的として
いる。An object of the present invention is to provide a protection device which can withstand even higher spike-like overvoltage inputs than the conventional protection devices by providing a means for preventing breakdown of the protection IGFET 102 in the above-mentioned conventional example.
本発明による絶縁ゲート型電界効果トランジスタの保護
装置は、例えばソースが被保護用絶縁ゲート型電界効果
型トランジスタのゲートあるいはドレインに電気的に接
続され、ドレインが入力又は出力端子に抵抗体を介して
接続された第1の保護用絶縁ゲート型電界効果トランジ
スタと、ソースが前記保護用絶縁ゲート型電界効果トラ
ンジスタのゲートを抵抗性素子を介して電圧源に接続し
たことを特徴とする。The protection device for an insulated gate field effect transistor according to the present invention is characterized by comprising, for example, a first protective insulated gate field effect transistor having a source electrically connected to the gate or drain of a protected insulated gate field effect transistor and a drain connected to an input or output terminal via a resistor, and a source connecting the gate of the protective insulated gate field effect transistor to a voltage source via a resistive element.
以下、本発明の一実施例である第2図を用いて本発明を
入力保護装置に適用した場合の構成及び効果を詳細に説
明する。The configuration and effects of the present invention when applied to an input protection device will be described in detail below with reference to FIG. 2 which shows one embodiment of the present invention.
第2図において、被保護用IGFET201のゲートは第1の保
護用IGFET202のソースに接続され、第1の保護用IGFET2
02のドレインは抵抗体211を介して入力端子21に接
続されている。第1の保護用IGFET202のゲートは第2の
保護用ディプリーション型IGFET203のソースに接続さ
れ、第2の保護用ディプリーション型IGFET203のゲート
及びドレインは電源電圧供給用配線23と接続点22で
接続されている。In FIG. 2, the gate of the protected IGFET 201 is connected to the source of the first protective IGFET 202.
The drain of the first protection IGFET 202 is connected to the input terminal 21 via a resistor 211. The gate of the first protection IGFET 202 is connected to the source of the second protection depletion-mode IGFET 203, and the gate and drain of the second protection depletion-mode IGFET 203 are connected to the power supply voltage supply wiring 23 at a connection point 22.
次に第2図に示した実施例の入力保護装置の動作につい
て説明する。入力端子21に印加される電圧が直流の電
圧である場合には、第1の保護用IGFET202は導通状態に
あり、第1図の従来の保護装置と同一動作をし、保護能
力も第1図の保護装置とほぼ等しい。しかし、実際の自
然の状態での静電破壊につながるスパイク状のパルス電
圧の印加では、本発明実施例の第2図の保護装置が従来
の第1図の保護装置より格段に保護能力が大きい。即
ち、第1図の従来の保護装置では入力端子11にスパイ
ク状の高電圧が印加された場合に保護用IGFET102のドレ
インには高い電圧がほぼそのまま印加され、保護用IGFE
T102のゲートの電圧は定電源電圧供給用配線13と同電
位であり、定電源電圧供給用配線13の電位は、半導体
集積回路が動作している状態で数ボルト程度で非動作状
態でほぼ接地電位であるから、保護用IGFET102のゲート
絶縁膜はドレイン近傍で破壊されてしまうのである。し
かしながら、本発明実施例の第2図の保護装置において
は、保護用IGFET202のゲートと定電源電圧供給用配線2
3との間に第2の保護用ディプリーション型IGFET20
3が、ソースは第1の保護用IGFET202のゲート側に、第
2の保護用ディプリーション型IGFET203のゲート及びド
レインは電源電圧供給用配線23との接続点22側にし
て挿入されているので、スパイク状の高電圧が入力端子
21に印加された場合には保護用IGFET202のドレイ
ン電位が高くなると共に保護用IGFET202のゲート−
ドレイン間の容量により保護用IGFET202のゲート電
位も同時に高くなるが電源電圧供給用配線23と保護用
IGFET202のゲート間に第2の保護用ディプリーショ
ン型IGFET203が挿入されているので、この第2の保
護用IGFET203が抵抗として働き、保護用IGFET202の
ゲート容量の充電電流を制限するので、保護用IGFET2
02のゲート電位は高電圧の印加直後、瞬時には低くな
らない。すなわち、保護用IGFET202のゲート電位は
保護用ディプリーション型IGFET203の抵抗成分と保
護用IGFET202のゲート容量とにより決まる時定数を
もって低くなり、やがて配線23の電源電圧と同じにな
る。しかしながら、保護用IGFET202のゲート電位が
配線23の電源電圧になるまえに、保護用IGFET202
のドレインと基板とのPN接合が降伏して保護用IGFET2
02ドレイン電圧は基板電位とほぼ等しくなるので、結
局、保護用IGFET202のドレインとゲート間の電位差は基
板と配線23との電位差となり、従来の第1図の保護装
置の場合より小さくなって、保護用IGFET202自体の
ゲート絶縁膜を破壊から保護することができる。本発明
の保護装置によれば従来の保護装置がゲート酸化膜厚5
00Åにおいて抵抗体111を1kΩとすると150V
程度のスパイク状パルス電圧でゲート酸化膜破壊が生ず
るのに対して300V以上のスパイク状パルス電圧に対
しても保護効果があり、従来の保護装置に対し本発明の
保護装置の優位性は明らかである。Next, the operation of the input protection device of the embodiment shown in Fig. 2 will be described. When the voltage applied to the input terminal 21 is a DC voltage, the first protection IGFET 202 is in a conductive state, and operates in the same manner as the conventional protection device of Fig. 1, and the protection capability is also approximately equal to that of the protection device of Fig. 1. However, when a spike-like pulse voltage that leads to electrostatic breakdown is applied in an actual natural state, the protection device of Fig. 2 according to the embodiment of the present invention has a significantly greater protection capability than the conventional protection device of Fig. 1. That is, in the conventional protection device of Fig. 1, when a spike-like high voltage is applied to the input terminal 11, the high voltage is applied almost as it is to the drain of the protection IGFET 102, and the protection IGFET
The voltage of the gate of T102 is the same potential as the constant power supply voltage supply wiring 13, and the potential of the constant power supply voltage supply wiring 13 is about several volts when the semiconductor integrated circuit is in operation and is approximately the ground potential when it is not in operation, so the gate insulating film of the protective IGFET 102 is destroyed near the drain.
3, a second protective depletion-mode IGFET 20
The source of the second protection depletion-type IGFET 203 is inserted on the gate side of the first protection IGFET 202, and the gate and drain of the second protection depletion-type IGFET 203 are inserted on the connection point 22 side with the power supply voltage supply wiring 23. Therefore, when a spike-like high voltage is applied to the input terminal 21, the drain potential of the protection IGFET 202 becomes high and the gate potential of the protection IGFET 202 becomes low.
The gate potential of the protective IGFET 202 also increases at the same time due to the capacitance between the drains.
Since the second protective depletion-type IGFET 203 is inserted between the gates of the IGFET 202, this second protective IGFET 203 acts as a resistor and limits the charging current of the gate capacitance of the protective IGFET 202.
The gate potential of the protection IGFET 202 does not drop instantly immediately after the application of the high voltage. That is, the gate potential of the protection IGFET 202 drops with a time constant determined by the resistance component of the protection depletion-mode IGFET 203 and the gate capacitance of the protection IGFET 202, and eventually becomes the same as the power supply voltage of the wiring 23. However, before the gate potential of the protection IGFET 202 becomes the power supply voltage of the wiring 23, the protection IGFET 202
The PN junction between the drain and the substrate of the protection IGFET 2 breaks down.
Since the drain voltage of the protective IGFET 202 is approximately equal to the substrate potential, the potential difference between the drain and gate of the protective IGFET 202 is equal to the potential difference between the substrate and the wiring 23, which is smaller than that of the conventional protective device shown in FIG. 1, and the gate insulating film of the protective IGFET 202 itself can be protected from destruction.
If the resistor 111 is 1 kΩ at 0.00 Å,
While gate oxide film breakdown occurs at a spike-like pulse voltage of about 300 V, the protective effect is observed even at a spike-like pulse voltage of 300 V or more, and the superiority of the protective device of the present invention over conventional protective devices is clear.
尚、本発明の保護装置を出力回路に適用した場合にも、
保護効果においては入力回路に適用した第2図の実施例
の場合と同様に従来例に比して2倍以上の耐破壊電圧を
得た。In addition, even when the protection device of the present invention is applied to an output circuit,
In terms of protective effect, a breakdown voltage more than twice as high as that of the prior art was obtained, similar to the embodiment of FIG. 2 applied to the input circuit.
以上、本発明についてNチャンネルのIGFETを例にって
説明したがPチャンネルのIGFETでも本発明の保護装置
が有効であることはもちろんである。Although the present invention has been described above by taking an N-channel IGFET as an example, it goes without saying that the protection device of the present invention is also effective for a P-channel IGFET.
第1図は従来例の保護装置の構成を示す回路図第2図は
本発明の実施例の構成を示す回路図である。 なお図において、11……入力端子、13……定電源電
圧供給用配線、101……被保護用IGFET、102
……保護用IGFET、111…抵抗体、21……入力
端子、23……定電源電圧供給用配線、201……被保
護用IGFET、202……保護用IGFET、203
……保護用ディプリーション型IGFET、211……
抵抗体、である。 FIG. 1 is a circuit diagram showing the configuration of a conventional protection device, and FIG. 2 is a circuit diagram showing the configuration of an embodiment of the present invention. In the figure, 11 ... input terminal, 13 ... constant power supply voltage supply wiring, 101 ... protected IGFET, 102
...Protection IGFET, 111...Resistor, 21...Input terminal, 23...Wiring for constant power supply voltage supply, 201...IGFET to be protected, 202...Protection IGFET, 203
...Protective depletion-type IGFET, 211...
A resistor.
Claims (1)
スタが接続された回路節点と入力端子または出力端子と
の間ソース・ドレイン電流路が接続され、定電流電圧供
給用配線にゲートが接続された保護用絶縁ゲート型電界
効果トランジスタを有し、前記入力端子または出力端子
に前記定電源電圧供給用配線の定電圧よりも高い電圧が
印加されたときに当該電圧に対し前記回路節点の電圧を
前記定電圧から前記保護用絶縁ゲート型電界効果トラン
ジスタのしきい値電圧だけ異なる電圧にクランプして前
記保護すべき絶縁ゲート型電界効果トランジスタを保護
する入出力保護装置において、前記保護用絶縁ゲート型
電界効果トランジスタと前記定電源電圧供給用配線との
間に抵抗性素子を挿入したことを特徴とする入出力保護
装置。[Claim 1] An input/output protection device which has a source-drain current path connected between a circuit node to which an insulated gate field effect transistor to be protected is connected and an input terminal or an output terminal, and which has a protective insulated gate field effect transistor with its gate connected to a constant current voltage supply wiring, and which protects the insulated gate field effect transistor to be protected by clamping the voltage of the circuit node to a voltage which differs from the constant voltage by the threshold voltage of the protective insulated gate field effect transistor when a voltage higher than the constant voltage of the constant power supply voltage supply wiring is applied to the input terminal or output terminal, wherein a resistive element is inserted between the protective insulated gate field effect transistor and the constant power supply voltage supply wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56162261A JPH061832B2 (en) | 1981-10-12 | 1981-10-12 | Input/Output Protection Device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56162261A JPH061832B2 (en) | 1981-10-12 | 1981-10-12 | Input/Output Protection Device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5863172A JPS5863172A (en) | 1983-04-14 |
| JPH061832B2 true JPH061832B2 (en) | 1994-01-05 |
Family
ID=15751074
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56162261A Expired - Lifetime JPH061832B2 (en) | 1981-10-12 | 1981-10-12 | Input/Output Protection Device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH061832B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6154468A (en) * | 1984-08-25 | 1986-03-18 | Fujitsu Ltd | Semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5435756B2 (en) * | 1974-02-04 | 1979-11-05 | ||
| JPS5510144B2 (en) * | 1974-11-25 | 1980-03-14 | ||
| JPS5563871A (en) * | 1978-11-06 | 1980-05-14 | Nec Corp | Protector for field-effect transistor with insulated gate |
-
1981
- 1981-10-12 JP JP56162261A patent/JPH061832B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5863172A (en) | 1983-04-14 |
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