JPH06196598A - Mounting structure for semiconductor chip - Google Patents
Mounting structure for semiconductor chipInfo
- Publication number
- JPH06196598A JPH06196598A JP4346311A JP34631192A JPH06196598A JP H06196598 A JPH06196598 A JP H06196598A JP 4346311 A JP4346311 A JP 4346311A JP 34631192 A JP34631192 A JP 34631192A JP H06196598 A JPH06196598 A JP H06196598A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- circuit board
- heat
- compression spring
- screw
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 150000001875 compounds Chemical class 0.000 abstract description 10
- 230000006835 compression Effects 0.000 abstract description 9
- 238000007906 compression Methods 0.000 abstract description 9
- 230000017525 heat dissipation Effects 0.000 abstract description 6
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 abstract description 6
- 230000005855 radiation Effects 0.000 description 21
- 229910000679 solder Inorganic materials 0.000 description 8
- 239000010410 layer Substances 0.000 description 5
- 239000012790 adhesive layer Substances 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Cooling Or The Like Of Electrical Apparatus (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】従来、特に大量の熱を発生する半
導体を基板に実装するための構造に関し、特に放熱部材
を設けたパッケージ構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure for mounting a semiconductor that generates a large amount of heat on a substrate, and more particularly to a package structure provided with a heat dissipation member.
【０００２】[0002]
【従来の技術】従来、特に放熱効率の高さを求められる
この種の実装構造としては、たとえば特開平2-244661号
公報、あるいは特開平2-246141号公報に示されるものが
あった。図において、1は半導体チップ、2はセラミック
多層基板等の回路基板、3はセラミックあるいは金属か
ら成るキャップ、４は放熱フィン、5は半田あるいは樹
脂から成る接着層、6は半田あるいは銀含有接着材から
成る熱伝導部材、8は接続ピン、11は半田バンプであ
る。半導体チップ1は回路基板2に搭載され、半田バンプ
11を介して回路基板2上の図示しない回路パターンに電
気的に接続されている。この半導体チップ1を覆うよう
に、キャップ3が接着層5によって回路基板に接着され
て、半導体チップ1を封止している。2. Description of the Related Art Conventionally, as a mounting structure of this type which is required to have a particularly high heat dissipation efficiency, there has been one disclosed in, for example, Japanese Patent Application Laid-Open No. 2-244661 or Japanese Patent Application Laid-Open No. 2-246141. In the figure, 1 is a semiconductor chip, 2 is a circuit board such as a ceramic multi-layer substrate, 3 is a cap made of ceramic or metal, 4 is a radiation fin, 5 is an adhesive layer made of solder or resin, 6 is an adhesive material containing solder or silver. Is a heat conducting member, 8 is a connecting pin, and 11 is a solder bump. The semiconductor chip 1 is mounted on the circuit board 2 and solder bumps
It is electrically connected to a circuit pattern (not shown) on the circuit board 2 via 11. A cap 3 is adhered to the circuit board by an adhesive layer 5 so as to cover the semiconductor chip 1 and seal the semiconductor chip 1.
【０００３】キャップ3によって密閉された空間に封止
された半導体チップ1は、熱源となる。この熱を効果的
に逃がすために、半導体チップ1の背面側には熱伝導部
材6が装填され、この熱伝導部材6は他方でキャップ3の
内側表面に接触している。これにより、半導体チップ1
から発生する熱の一部は、熱伝導部材6を通じてキャッ
プ３に伝達され、そこから放出される。The semiconductor chip 1 sealed in the space sealed by the cap 3 serves as a heat source. In order to effectively dissipate this heat, a heat conducting member 6 is loaded on the back side of the semiconductor chip 1, and the heat conducting member 6 is in contact with the inner surface of the cap 3 on the other hand. This allows the semiconductor chip 1
A part of the heat generated from the heat transfer member 6 is transferred to the cap 3 through the heat transfer member 6 and is discharged from the cap 3.
【０００４】[0004]
【発明が解決しようとする課題】しかし、以上のような
構成では、半導体チップ１の高さ、キャップ3の高さ、
接着層5の厚さ、半田バンプ11の高さなどの誤差が熱伝
導部材6の厚さに影響するため、熱伝導部材6の厚さには
100μｍないし300μｍと大きなばらつきを生じていた。
このために、熱伝導部材6の熱抵抗の増大を避けられな
かった。さらに、半導体チップ1、キャップ3、接着層
5、半田バンプ11の各々の熱膨張係数が異なるため、半
導体チップ1の大型化の傾向に対して、各部の信頼性が
低下していた。このような問題を解決して、放熱フィン
4の効率を向上させるとともに、信頼性の高い実装構造
を提供することが、本願発明の目的とするところであ
る。However, in the above structure, the height of the semiconductor chip 1, the height of the cap 3,
Errors such as the thickness of the adhesive layer 5 and the height of the solder bumps 11 affect the thickness of the heat conductive member 6.
There was a large variation of 100 μm to 300 μm.
For this reason, an increase in the thermal resistance of the heat conducting member 6 cannot be avoided. Furthermore, semiconductor chip 1, cap 3, adhesive layer
5. Since the thermal expansion coefficients of the solder bumps 11 are different, the reliability of each part is lowered against the tendency of the semiconductor chip 1 to be upsized. Solving such problems, the heat dissipation fin
It is an object of the present invention to improve the efficiency of 4 and provide a highly reliable mounting structure.
【０００５】[0005]
【課題を解決するための手段】上述の課題を解決するた
めに、本発明においては、半導体チップ1の周辺部のみ
封止して、半導体チップ1の上面にサーマル・コンパウ
ンドを塗布したのちに、スプリングを介して放熱フィン
を加圧固定したものである。In order to solve the above-mentioned problems, in the present invention, only the peripheral portion of the semiconductor chip 1 is sealed, and after applying a thermal compound to the upper surface of the semiconductor chip 1, A heat radiation fin is pressed and fixed via a spring.
【０００６】[0006]
【作用】上記の構成によれば、放熱フィンは、スプリン
グの押圧力によって半導体チップの上面、厳密には同上
面に塗布されたサーマル・コンパウンドに一定の力をも
って押圧され、密着する。このスプリングの押圧力は、
スプリングの弾性定数によって決定されるが、この弾性
定数は放熱フィンなどの弾性定数に比べて著しく小さい
ために、放熱フィンなどの部品の寸法誤差や熱膨張など
の影響を受けても、押圧力の変化は小さい。According to the above construction, the heat radiation fin is pressed against the upper surface of the semiconductor chip, strictly speaking, the thermal compound applied on the upper surface with a constant force by the pressing force of the spring, and is brought into close contact with the thermal compound. The pressing force of this spring is
It is determined by the elastic constant of the spring.Since this elastic constant is significantly smaller than the elastic constants of the heat radiation fins, etc., even if it is affected by dimensional errors or thermal expansion of parts such as the heat radiation fins, the pressing force The change is small.
【０００７】[0007]
【実施例】以下、本発明の一実施例について、図1を参
照しつつ説明する。図において、既に説明した従来の構
成と同じ構成要件については、図2と同じ参照符号を付
して、その説明を省略する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. In the figure, the same components as those of the conventional configuration described above are designated by the same reference numerals as those in FIG. 2, and the description thereof will be omitted.
【０００８】図において、9はサーマル・コンパウン
ド、10は台座、20はねじ、21は圧縮スプリングである。
サーマル・コンパウンド9は、組立時に半導体チップ1の
上面に塗布され、図に示す組立状態では、放熱フィン4
の下面にも密着している。台座10は、回路基板2の上面
に、接着あるいはブレージングによって、強固に固定さ
れている。この台座10の上面には、ねじ20の外径よりも
大きな内径を有するねじ穴が設けられている。このねじ
穴には、ねじ20が締め込まれている。このねじ20は、放
熱フィン4を貫通して台座10に締め込まれ、放熱フィン4
を回路基板2に固定する。この放熱フィン4に設けられた
貫通穴の内径は、ねじ20の呼び径よりも大きい。したが
って、放熱フィン4は、このねじ20によって回路基板2に
完全に固定されることはなく、ねじ20と貫通穴との隙間
の範囲内で、任意の方向にわずかに動くことが可能であ
る。また、ねじ20の頭部と放熱フィン4との間には、圧
縮スプリング21が挿入されている。この圧縮スプリング
21は、放熱フィン4を図における下方、すなわち回路基
板2に向けて押圧している。このため、放熱フィン4は、
既に述べたように半導体チップ1の上面に塗布されたサ
ーマル・コンパウンド9に密着することになる。In the figure, 9 is a thermal compound, 10 is a pedestal, 20 is a screw, and 21 is a compression spring.
The thermal compound 9 is applied to the upper surface of the semiconductor chip 1 during assembly, and in the assembled state shown in the figure, the heat dissipation fin 4
It also adheres to the bottom surface of. The pedestal 10 is firmly fixed to the upper surface of the circuit board 2 by adhesion or brazing. A screw hole having an inner diameter larger than the outer diameter of the screw 20 is provided on the upper surface of the pedestal 10. A screw 20 is tightened in this screw hole. The screw 20 penetrates the heat radiation fin 4 and is fastened to the pedestal 10 so that the heat radiation fin 4
Is fixed to the circuit board 2. The inner diameter of the through hole provided in the heat radiation fin 4 is larger than the nominal diameter of the screw 20. Therefore, the radiation fin 4 is not completely fixed to the circuit board 2 by the screw 20, but can be slightly moved in any direction within the range of the gap between the screw 20 and the through hole. A compression spring 21 is inserted between the head of the screw 20 and the heat radiation fin 4. This compression spring
21 presses the radiation fin 4 downward in the figure, that is, toward the circuit board 2. Therefore, the radiation fin 4
As described above, it comes into close contact with the thermal compound 9 applied to the upper surface of the semiconductor chip 1.
【０００９】ところで、この状態で、たとえば半導体チ
ップ1や半田バンプ11が熱膨張したり、あるいは回路基
板2などに歪みを生じたりしていると、半導体チップ1が
放熱フィン4を押し上げようとしたり、逆に半導体チッ
プ1と放熱フィン4との間に隙間が開いたりする。ところ
が、いずれの場合でも、放熱フィンにかかる力は、結局
圧縮スプリング21に伝えられ、圧縮スプリング21の伸縮
に変わる。このため、放熱フィン4から半導体チップ1に
はたらく力は、常にこの圧縮スプリング21によって一定
に保たれる。この押圧力は、出願人の検討によれば、20
0〜600グラム／平方センチ程度であると、半導体チップ
1に損傷を与えることなく、熱抵抗を充分に低減させる
ことができる。この時のサーマル・コンパウンド9の層
厚は、50マイクロメートル程度になる。In this state, if the semiconductor chip 1 and the solder bumps 11 are thermally expanded or the circuit board 2 is distorted, the semiconductor chip 1 tries to push up the heat radiation fins 4. On the contrary, a gap may be opened between the semiconductor chip 1 and the radiation fin 4. However, in any case, the force applied to the radiating fin is eventually transmitted to the compression spring 21 and is changed into expansion and contraction of the compression spring 21. Therefore, the force acting from the radiation fin 4 to the semiconductor chip 1 is always kept constant by the compression spring 21. According to the applicant's consideration, this pressing force is 20
A semiconductor chip with 0 to 600 grams / square centimeter
The thermal resistance can be sufficiently reduced without damaging 1. At this time, the layer thickness of the thermal compound 9 is about 50 μm.
【００１０】また、この半導体チップ1と放熱フィン4
は、この両者がサーマル・コンパウンド9を介して接触
する面内、たとえば図における左右の方向に相対運動を
行なう、すなわち慴動することも、可能である。また、
サーマル・コンパウンド9に代えて、展性に富む金属、
例えば半田などを薄いシート状に成型したものを、半導
体チップ1の上面に貼付してもよい。いずれの方法にし
ても、求められる条件としては、半導体チップ1と放熱
フィン4との間に空気層またはボイドを残さないことが
挙げられる。この点に関して、上記の方法は有効であ
る。Further, the semiconductor chip 1 and the radiation fin 4
It is also possible to perform relative movement, that is, slid, in a plane in which the two come into contact with each other via the thermal compound 9, for example, in the left and right directions in the drawing. Also,
Instead of thermal compound 9, a metal with rich malleability,
For example, a thin sheet of solder or the like may be attached to the upper surface of the semiconductor chip 1. Whichever method is used, the required condition is that no air layer or void is left between the semiconductor chip 1 and the heat radiation fin 4. In this respect, the above method is effective.
【００１１】[0011]
【発明の効果】以上に説明したように、本発明によれ
ば、半導体チップ1と放熱フィン4との間に熱伝導性の良
い物質を間挿して、空気層を形成しないようにし、かつ
間挿した物質の層厚を小さく抑制するようにしたので、
放熱フィン、回路基板、半導体チップなどの熱膨張係数
が調和していなくても、半導体チップには熱応力が発生
しないか、発生しても応力が非常に小さくなる。また、
半導体チップから放熱フィンへの熱伝導の効率が高くな
り、熱膨張そのものが発生しにくくなる。As described above, according to the present invention, a substance having good thermal conductivity is inserted between the semiconductor chip 1 and the heat radiation fins 4 so as not to form an air layer, and Since the layer thickness of the inserted substance was suppressed to a small level,
Even if the thermal expansion coefficients of the radiating fins, the circuit board, the semiconductor chip, etc. are not matched, no thermal stress is generated in the semiconductor chip, or even if they are generated, the stress becomes very small. Also,
The efficiency of heat conduction from the semiconductor chip to the heat radiation fins is increased, and thermal expansion itself is less likely to occur.
【００１２】このため、装置全体の信頼性ならびに性能
の向上が実現する。さらに、放熱フィンの材質として、
安価で熱伝導性に優れていながら、半導体チップと熱膨
張係数が大きく異なるために従来は採用を見送られるこ
とがあったアルミニウムなどを、積極的に採用すること
が可能になる。このため、放熱フィンのコストを低減
し、装置の性能を一層向上させることが可能になる。Therefore, the reliability and performance of the entire device are improved. Furthermore, as the material of the radiation fin,
Although it is inexpensive and has excellent thermal conductivity, it is possible to positively adopt aluminum or the like, which has conventionally been postponed due to a large difference in thermal expansion coefficient from the semiconductor chip. Therefore, it is possible to reduce the cost of the radiation fins and further improve the performance of the device.
【図１】本発明の実施例の実装構造を示す一部断面図で
ある。FIG. 1 is a partial cross-sectional view showing a mounting structure of an embodiment of the present invention.
【図２】従来の実装構造を示す一部断面図である。FIG. 2 is a partial cross-sectional view showing a conventional mounting structure.
１ 半導体チップ ２ 回路基板 ４ 放熱フィン １０ 台座 ２０ ねじ ２１ 圧縮スプリング 1 semiconductor chip 2 circuit board 4 radiating fin 10 pedestal 20 screw 21 compression spring
Claims (1)
る付勢手段とを有することを特徴とする、半導体チップ
の実装構造。1. A circuit board on which a semiconductor chip is mounted, a radiating fin swingably locked to the circuit board, and urging means for urging the radiating fin to bring it into close contact with the semiconductor chip. A semiconductor chip mounting structure, characterized by having.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4346311A JPH06196598A (en) | 1992-12-25 | 1992-12-25 | Mounting structure for semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4346311A JPH06196598A (en) | 1992-12-25 | 1992-12-25 | Mounting structure for semiconductor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06196598A true JPH06196598A (en) | 1994-07-15 |
Family
ID=18382546
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4346311A Pending JPH06196598A (en) | 1992-12-25 | 1992-12-25 | Mounting structure for semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06196598A (en) |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000022059A (en) * | 1998-07-07 | 2000-01-21 | Fujitsu Ltd | Electronic equipment |
| JP2001057490A (en) * | 1999-08-17 | 2001-02-27 | Toshiba Corp | Cooling device and electronic equipment for circuit parts |
| KR20020001492A (en) * | 2000-06-24 | 2002-01-09 | 이형도 | Heat sink |
| JP2002093960A (en) * | 2000-09-12 | 2002-03-29 | Nec Corp | Cooling structure of multichip module and its manufacturing method |
| US6374337B1 (en) | 1998-11-17 | 2002-04-16 | Lexar Media, Inc. | Data pipelining method and apparatus for memory control circuit |
| US6411546B1 (en) | 1997-03-31 | 2002-06-25 | Lexar Media, Inc. | Nonvolatile memory using flexible erasing methods and method and system for using same |
| JP2002520627A (en) * | 1998-07-14 | 2002-07-09 | インフィネオン テクノロジース アクチエンゲゼルシャフト | Biometric sensor and method of manufacturing the sensor |
| US6567307B1 (en) | 2000-07-21 | 2003-05-20 | Lexar Media, Inc. | Block management for mass storage |
| US6728851B1 (en) | 1995-07-31 | 2004-04-27 | Lexar Media, Inc. | Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices |
| US6757800B1 (en) | 1995-07-31 | 2004-06-29 | Lexar Media, Inc. | Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices |
| US6801979B1 (en) | 1995-07-31 | 2004-10-05 | Lexar Media, Inc. | Method and apparatus for memory control circuit |
| US6813678B1 (en) | 1998-01-22 | 2004-11-02 | Lexar Media, Inc. | Flash memory system |
| JP2009059760A (en) * | 2007-08-30 | 2009-03-19 | Toshiba Corp | Electronic circuit board heat dissipation structure |
| US7983048B2 (en) | 2007-02-15 | 2011-07-19 | Nec Corporation | Structure for mounting semiconductor package |
| JP2018073864A (en) * | 2016-10-24 | 2018-05-10 | 日本電気株式会社 | Cooling device, mounting method |
-
1992
- 1992-12-25 JP JP4346311A patent/JPH06196598A/en active Pending
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6801979B1 (en) | 1995-07-31 | 2004-10-05 | Lexar Media, Inc. | Method and apparatus for memory control circuit |
| US6757800B1 (en) | 1995-07-31 | 2004-06-29 | Lexar Media, Inc. | Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices |
| US6728851B1 (en) | 1995-07-31 | 2004-04-27 | Lexar Media, Inc. | Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices |
| US6411546B1 (en) | 1997-03-31 | 2002-06-25 | Lexar Media, Inc. | Nonvolatile memory using flexible erasing methods and method and system for using same |
| US6587382B1 (en) | 1997-03-31 | 2003-07-01 | Lexar Media, Inc. | Nonvolatile memory using flexible erasing methods and method and system for using same |
| US6813678B1 (en) | 1998-01-22 | 2004-11-02 | Lexar Media, Inc. | Flash memory system |
| JP2000022059A (en) * | 1998-07-07 | 2000-01-21 | Fujitsu Ltd | Electronic equipment |
| JP2002520627A (en) * | 1998-07-14 | 2002-07-09 | インフィネオン テクノロジース アクチエンゲゼルシャフト | Biometric sensor and method of manufacturing the sensor |
| US6374337B1 (en) | 1998-11-17 | 2002-04-16 | Lexar Media, Inc. | Data pipelining method and apparatus for memory control circuit |
| JP2001057490A (en) * | 1999-08-17 | 2001-02-27 | Toshiba Corp | Cooling device and electronic equipment for circuit parts |
| KR20020001492A (en) * | 2000-06-24 | 2002-01-09 | 이형도 | Heat sink |
| US6567307B1 (en) | 2000-07-21 | 2003-05-20 | Lexar Media, Inc. | Block management for mass storage |
| JP2002093960A (en) * | 2000-09-12 | 2002-03-29 | Nec Corp | Cooling structure of multichip module and its manufacturing method |
| US7983048B2 (en) | 2007-02-15 | 2011-07-19 | Nec Corporation | Structure for mounting semiconductor package |
| JP2009059760A (en) * | 2007-08-30 | 2009-03-19 | Toshiba Corp | Electronic circuit board heat dissipation structure |
| JP2018073864A (en) * | 2016-10-24 | 2018-05-10 | 日本電気株式会社 | Cooling device, mounting method |
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