JPH06196661A - NOR-X type mask ROM of diffusion layer rewriting method - Google Patents

Abstract

PURPOSE:To maintain the operation speed of a NOR-X type mask ROM by a method wherein a plurality of bit lines and ground lines are formed on diffused layers which are selectively formed on a substrate and a plurality of gate lines which cross those lines are formed and the existence of data is shown by the existence of a diffused layer. CONSTITUTION:Bit lines 2 and ground lines 4 are alternately provided in a ROM and polycrystalline silicon layers 6 which are to be gates are provided between them. Diffused layers 8 are provided on the bit lines 2 and the ground lines 4 respectively. The polycrystalline silicon layers 6 which are provided horizontally are word lines. The bit lines 2 and the ground lines 4 which are provided vertically are made of metal. In this ROM, the formation of a device is controlled by the existence of a diffused layer 10 on a part which connects the bit line 2 and the ground line 4 with an angle of 45 deg. and 0/1 of the data is determined. Therefore, the diffused layer 10 is used as a ROM rewriting layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a NOR-X type mask R
It is about OM.

[0002]

2. Description of the Related Art Mask ROM in a semiconductor integrated circuit
Stores information by distinguishing 0 or 1 according to the voltage level of the bit line at the time of reading. This difference in voltage level is usually caused by the presence or absence of a device corresponding to the address to be read or the difference in the threshold voltage of the device.

There are a NAND type and a NOR type in the mask ROM. In both of them, the threshold voltage Vth of the device is changed by ion implantation during the manufacturing process to distinguish 0 or 1, but the NAND type is a depletion type. However, in the NOR type, a device having a high threshold voltage Vth is used. Similarly, in a NOR-X type mask ROM, which is one type of NOR type, a device with a high Vth is used.

With the increase in the function of electronic circuits and the increase in system scale due to complexity, the speed of semiconductor integrated circuits, which are components, is also increasing. In particular, it is a storage element including a non-volatile memory and a mask ROM that controls the speed in the system, and even if the element that performs arithmetic processing or the like is speeded up, data cannot be stored or read. In some cases, the operating speed must be reduced. Even if a memory exists inside the semiconductor integrated circuit, this often determines the speed of the entire chip.

Generally, in a NOR-X type mask ROM, 0/1 of data called a ROM code depends on whether the level of a precharged bit line is held or discharged by turning on / off a device for a selected word line. To distinguish. Therefore, the memory cell may be configured so that the device can be turned on / off. Therefore, the rewriting method by ion implantation is to separately create a device that is turned on at the voltage level of the selected word line and a device that is not turned on by changing the Vth of the MOS.

[0006]

If the voltage level of the selected word line is the power supply voltage, the Vth of the device that does not turn on when reading 1 must be higher than that. However, in the current LSI, the power supply voltage is set to 5V, so that it is difficult in the process to make a device having Vth higher than this. Therefore, if the selection level of the word line is set to, for example, 3V, this Vth can be 3.5V. In this case, the voltage level is limited to set the word line level to 3V.
The operating speed of the OM is often slow.

[0007]

In order to solve the above problems, the present invention uses the presence or absence of device formation by a diffusion layer in the rewriting method of a NOR-X type mask ROM.

That is, according to the present invention, the diffusion layer is partially formed on the substrate, the plurality of bit lines and the plurality of ground lines are formed on the diffusion layer, and the plurality of bit lines and the ground lines are crossed. Multiple gate lines are formed,
NOR- that distinguishes the presence or absence of data by the presence or absence of the diffusion layer
An X-type mask ROM is provided.

[0009]

The operation of the present invention will be described below. Unlike the rewriting method by the ion implantation, the rewriting method by the diffusion layer distinguishes the ROM code 0/1 depending on whether or not a device is formed. That is, if a device exists at the position corresponding to the selected address, the precharged bit line is discharged by turning on the device. If there is no device at the selected address, the bit line level is retained.

As described above, when 1 is read, the device does not exist, and the selected word line can be set to the power supply voltage level regardless of the Vth of the device. Therefore, it is not necessary to use an extra circuit and the operation speed is not affected.

[0011]

EXAMPLES Examples of the present invention are shown below.

FIG. 1 shows an embodiment of a NOR-X type mask ROM according to the present invention. The figure shows a NOR-X type mask R
This is a layout example in the case where 0/1 of the ROM code is distinguished by the diffusion layer rewriting method in the OM. In this ROM, bit lines 2 and ground lines 4 are alternately arranged, and the gap between them serves as a polysilicon 6 serving as a gate.
Is passing. Diffusion layers 8 are arranged on the bit lines 2 and the ground lines 4, respectively.

The polysilicon 6 arranged in the horizontal direction is a word line, and the bit line 2 and the ground line 4 arranged in the vertical direction are formed by Metall.

In this ROM, the formation of the device is controlled depending on whether or not the diffusion layer 10 exists at the portion connecting the bit line 2 and the ground line 4 at an angle of 45 degrees, and 0/1 of the data is determined. To be done. Therefore, the diffusion layer 10 here becomes a ROM rewriting layer.

According to such a NOR-X type mask ROM, unlike the rewriting method by ion implantation, the ROM code 0/1 is distinguished by the presence or absence of the formation of the device. That is, if a device exists at the position corresponding to the selected address, the precharged bit line is discharged by turning on the device. If there is no device at the selected address, the bit line level is retained.

As described above, when 1 is read, the device does not exist, and the selected word line can be set to the power supply voltage level regardless of the Vth of the device. Therefore, since it is not necessary to use an extra circuit, a clamp circuit or the like is not required inside, and the operation speed can be increased.

[0017]

According to the present invention, the NOR-X type mask R
Since the OM does not need a clamp circuit or the like inside, the operating speed can be increased.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a NOR-X type mask ROM according to the present invention.

[Explanation of symbols]

 2 Bit line 4 Ground line 6 Polysilicon 8, 10 Diffusion layer

Claims (1)

[Claims] 1. A diffusion layer is partially formed on a substrate, a plurality of bit lines and a plurality of ground lines are formed on the diffusion layer, and a plurality of gates intersecting the plurality of bit lines and the ground lines. A line is formed, and the presence or absence of data is distinguished by the presence or absence of the diffusion layer.
R-X type mask ROM.