JPH0621657A - Checking pattern for layer organization of multilayer print wiring board - Google Patents
Checking pattern for layer organization of multilayer print wiring boardInfo
- Publication number
- JPH0621657A JPH0621657A JP4178653A JP17865392A JPH0621657A JP H0621657 A JPH0621657 A JP H0621657A JP 4178653 A JP4178653 A JP 4178653A JP 17865392 A JP17865392 A JP 17865392A JP H0621657 A JPH0621657 A JP H0621657A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- inner layer
- substrate
- knitting
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】
【目的】 多層プリント配線板における層編成チェック
用パターンに関し、確実に基板の層編成の誤りを発見す
ることのできる層編成チェック用パターンを提供するこ
とを目的とする。
【構成】 表層基板1から各内層基板2,3,…の中間
厚さ位置までの深さに穿設された複数のIVH11,1
2,…と、上記表層基板1及びと各内層基板2,3,…
の表面に形成された内層チェックパターン32,33,
…とからなり、上記IVH11,12,…と内層チェッ
クパターン32,33,…とが、正規の層編成では、上
記各内層チェックパターン32,33,…が、順に異な
るIVH11,12,…で、他の唯一の内層チェックパ
ターンに接続されるように配設される構成とする。
(57) [Abstract] [Purpose] It is an object of the present invention to provide a layer knitting check pattern for a layered knitting check pattern in a multilayer printed wiring board, which is capable of surely detecting an error in the layer knitting of a substrate. [Structure] A plurality of IVHs 11, 1 drilled at a depth from the surface layer substrate 1 to the intermediate thickness position of each inner layer substrate 2, 3 ,.
2, ..., the surface layer substrate 1 and the inner layer substrates 2, 3 ,.
Inner layer check patterns 32, 33 formed on the surface of the
, And the inner layer check patterns 32, 33, ... In the regular layer knitting, the inner layer check patterns 32, 33 ,. It is arranged so as to be connected to the only other inner layer check pattern.
Description
【0001】[0001]
【産業上の利用分野】本発明は、多層プリント配線板に
おける層編成チェック用パターンに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layer knitting check pattern for a multilayer printed wiring board.
【0002】[0002]
【従来の技術】多層プリント配線板は、複数の内層基板
及び表層基板を所定の順に積み重ね、圧着してなり、各
基板の表面あるいは両面に形成された回路パターンが、
スルーホールやIVH等によって互いに接続される。2. Description of the Related Art A multilayer printed wiring board is formed by stacking a plurality of inner layer substrates and surface layer substrates in a predetermined order and press-bonding them, and a circuit pattern formed on the front surface or both surfaces of each substrate.
They are connected to each other by through holes or IVH.
【0003】上記内層基板及び表層基板の積み重ねの順
序、すなわち基板の層編成は、所期の回路設計に基づく
正規の編成になければならない。ところが通常、各基板
の積み重ねは手作業で行われるところから、各基板の積
層順を間違えたり、同じ基板を重複して積み重ねたりす
る等の人為的なミスの生じる余地があり、従来は各基板
にマークや番号を印刷し、積層工程以後にそのマークや
番号を目で見て層編成に誤りがないかをチェックしてい
る。The stacking order of the inner layer substrate and the surface layer substrate, that is, the layer knitting of the substrate must be a regular knitting based on the intended circuit design. However, since each board is usually stacked manually, there is room for human error such as making a mistake in the stacking order of each board or stacking the same board in duplicate. Marks and numbers are printed on the label, and after the lamination process, the marks and numbers are visually checked to see if the layer composition is correct.
【0004】例えば図3に示すように、2枚の表層基板
1a,1bと、3枚の内層基板2,3,4を積層した多
層プリント配線板において、上記各基板の側端面に位置
を層方向に順次ずらせて印刷したマーク50を設けてい
る。このような各基板の積層が完了した時点で側方向か
ら観察すると、正規の層編成の場合に限って、各マーク
50が階段状に配列され、誤った層編成で表れるマーク
50の配列との区別ができ、層編成の正誤が判別でき
る。For example, as shown in FIG. 3, in a multilayer printed wiring board in which two surface layer substrates 1a and 1b and three inner layer substrates 2, 3 and 4 are laminated, the positions are arranged on the side end faces of the respective substrates. Marks 50 are provided which are printed while being sequentially shifted in the direction. When observed from the side when the stacking of the respective substrates is completed, the marks 50 are arranged in a stepwise pattern only in the case of regular layer formation, and the marks 50 appearing in the wrong layer formation are arranged. Can be distinguished, and correctness of layer formation can be determined.
【0005】また、例えば図4に示すように、上記各基
板が透明あるいは半透明であることを利用して、上記各
基板の回路パターン領域外に、積み重ね順を示す番号5
1を各基板毎に印刷位置をずらせた番号51と、該番号
51に続く領域に番号51と色違いで各々面積の異なる
不透明な遮光パターン52を形成しておく。Further, as shown in FIG. 4, for example, by utilizing the fact that each substrate is transparent or semi-transparent, the number 5 indicating the stacking order is placed outside the circuit pattern region of each substrate.
1 is formed by shifting the printing position for each substrate, and an opaque light shielding pattern 52 having a different area from that of the number 51 is formed in a region subsequent to the number 51.
【0006】上記各基板を積層した状態で上方から観察
すると、上記番号51は遮光パターン52よりも上層に
ある場合は判読できるが、遮光パターン52よりも下層
になると隠蔽されて判読できなくなる。従って、正規の
層編成で積層された場合には、図4(a) に示すように、
『1』から昇順に並んだ番号51の配列が確認できる
が、それ以外の誤った層編成では図4(b) に示すように
上記遮光パターン52で一部の番号51が隠蔽され、上
記順列と異なる順列が表れるところから(図示の例では
内層基板2の番号『2』が内層基板3の遮光パターン5
2で隠蔽され、番号の欠落が生じる)、層編成の正誤が
判別できる。When the above-mentioned substrates are stacked and observed from above, the number 51 can be read when it is above the light-shielding pattern 52, but is hidden when it is below the light-shielding pattern 52 and cannot be read. Therefore, when they are stacked in a regular layer formation, as shown in Fig. 4 (a),
Although the arrangement of the number 51 arranged in ascending order from "1" can be confirmed, as shown in Fig. 4 (b), a part of the number 51 is concealed by the light-shielding pattern 52 in the wrong layer formation, and the above-mentioned permutation is performed. (In the illustrated example, the number "2" of the inner layer substrate 2 is the light shielding pattern 5 of the inner layer substrate 3).
2 is concealed, and a missing number occurs), and correctness of layer formation can be determined.
【0007】[0007]
【発明が解決しようとする課題】しかしながら、上記各
基板の端面に印刷したマーク50で層編成のチェックを
行う場合でも、結局肉眼での判別に頼ることになり、し
かも表層基板及び内層基板の板厚が小さいこともあっ
て、マーク50自体が見にくく、層編成の誤りを見逃す
ことがある。However, even when the layer knitting is checked by the marks 50 printed on the end faces of the above-mentioned respective substrates, the judgment of the naked eye is ultimately required, and the plates of the surface layer substrate and the inner layer substrate are also decided. Since the thickness is small, the mark 50 itself is difficult to see, and an error in layer formation may be overlooked.
【0008】また、基板表面に印刷した番号51と遮光
パターン52とで層編成のチェックを行う場合でも、上
記同様肉眼での判別に頼るので、見逃しの可能性があ
り、しかも層数の大きい多層プリント配線板では、表層
基板1aから下層の基板の番号が透明度の低下により確
認がしにくくなるので、チェックが困難になる欠点があ
る。Further, even when checking the layer knitting with the number 51 and the light shielding pattern 52 printed on the surface of the substrate, since the judgment depends on the naked eye similarly to the above, there is a possibility that it may be overlooked and the number of layers is large. In the printed wiring board, it is difficult to check the numbers of the lower layer substrate and the surface layer substrate 1a due to the decrease in transparency, and thus there is a drawback that the check becomes difficult.
【0009】本発明は上記の事情に鑑み提案されたもの
であって、確実に基板の層編成の誤りを発見することの
できる層編成チェック用パターンを提供することを目的
とするものである。The present invention has been proposed in view of the above circumstances, and it is an object of the present invention to provide a layer knitting check pattern capable of surely detecting an error in the layer knitting of a substrate.
【0010】[0010]
【課題を解決するための手段】上記の目的を達成するた
めに本発明は以下の手段を採用する。すなわち、例えば
図1乃至図2に示すように、表層基板1(1a,1b)
から各内層基板2,3,…の中間厚さ位置までの深さに
穿設された複数のIVH11,12,…と、上記表層基
板1及び各内装基板2,3,…の表面に形成された内層
チェックパターン32,33,…とからなり、上記IV
H11,12,…と内層チェックパターンとが、正規の
層編成では、上記各内層チェックパターン32,33,
…が、順に異なるIVH11,12,…で、他の唯一の
内層チェックパターンに接続されるように配設された基
板の層編成チェック用パターンである。In order to achieve the above object, the present invention employs the following means. That is, for example, as shown in FIGS. 1 and 2, the surface layer substrate 1 (1a, 1b)
To a plurality of IVHs 11, 12, ... Perforated at a depth from the inner layer substrates 2, 3, ... to the intermediate thickness position, and on the surface of the surface layer substrate 1 and each of the interior substrates 2, 3 ,. And inner layer check patterns 32, 33, ...
H11, 12, ... And the inner layer check pattern are the above-mentioned inner layer check patterns 32, 33, in the regular layer knitting.
Are the IVHs 11, 12, ... Which are different in order, and are the layer knitting check patterns of the substrate arranged so as to be connected to the only other inner layer check pattern.
【0011】[0011]
【作用】上記の構成によれば、正規の層編成の場合に限
って、全てのIVH11,12,…が、内層チェックパ
ターン32,33,…によって電気的に接続されるの
で、例えば製品パターンの導通試験と同時に適当に選定
した2本のIVH間が導通されているか否かを検出する
ことにより、層編成の正誤を判定できる。According to the above construction, all IVHs 11, 12, ... Are electrically connected by the inner layer check patterns 32, 33, .. At the same time as the continuity test, it is possible to determine whether the layer knitting is correct by detecting whether or not there is continuity between two appropriately selected IVHs.
【0012】[0012]
【実施例】図1は本発明に係る一実施例の断面図であ
り、この実施例では表層基板1a(1)、内層基板2,
3,4、表層基板1b(1)の、合計5枚の基板が順に
積層された多層プリント配線板に本発明を適用してい
る。1 is a sectional view of an embodiment according to the present invention. In this embodiment, a surface layer substrate 1a (1), an inner layer substrate 2,
The present invention is applied to a multilayer printed wiring board in which a total of five substrates 3, 4, and the surface layer substrate 1b (1) are sequentially laminated.
【0013】この実施例は、正規の層編成では、図1
(a) に示すように、表層基板1a(1)の回路パターン
領域外の表面から内層基板2,3,4の中間厚さ位置ま
での異なる深さで穿設されている3本のIVH11,1
2,13と、表層基板1b(1)の回路パターン領域外
の表面から内層基板3,4の中間厚さ位置までの異なる
深さで穿設されている2本のIVH14,15とを有
し、上記表層基板1b(1)及び内層基板2〜4の表面
に形成した内層チェックパターン32〜35で、上記全
てのIVH11〜15を電気的に接続するようにしてい
る。In this embodiment, in the regular layer knitting, FIG.
As shown in (a), three IVHs 11, which are drilled at different depths from the surface outside the circuit pattern area of the surface layer substrate 1a (1) to the intermediate thickness position of the inner layer substrates 2, 3 and 4, 1
2 and 13 and two IVHs 14 and 15 drilled at different depths from the surface outside the circuit pattern region of the surface layer substrate 1b (1) to the intermediate thickness position of the inner layer substrates 3 and 4. All the IVHs 11 to 15 are electrically connected by the inner layer check patterns 32 to 35 formed on the surfaces of the surface layer substrate 1b (1) and the inner layer substrates 2 to 4.
【0014】上記各内層チェックパターン32〜35
は、内層基板2,3,4及び表層基板1bの表面に回路
パターンのパターニングと同時に形成するようにしてい
るので、層編成に対応してその板厚方向の位置が変動
し、上記穿設深さの異なるIVH11〜15との接続・
非接続の状態が変わることになり、正規の層編成におい
てのみ、隣接するIVH同士が唯一の内層チェックパタ
ーンで接続されることになる。Each inner layer check pattern 32 to 35 described above
Is formed simultaneously with the patterning of the circuit pattern on the surfaces of the inner layer substrates 2, 3, 4 and the surface layer substrate 1b, the position in the plate thickness direction changes corresponding to the layer knitting, and Connection with IVHs 11-15 with different height
The state of non-connection will change, and only in the regular layer formation, adjacent IVHs will be connected by a unique inner layer check pattern.
【0015】従って、例えば図1(b) に示すように、内
層基板2と内層基板3とを誤って入れ替えて積み重ねた
場合には、IVH11とIVH12との間を正規の層編
成では接続するはずの内層チェックパターン32は、I
VH11に接続しないことになり、IVH11とIVH
12との間が絶縁状態になる。Therefore, for example, as shown in FIG. 1B, when the inner layer substrate 2 and the inner layer substrate 3 are mistakenly replaced and stacked, the IVH 11 and the IVH 12 should be connected by a regular layer formation. The inner layer check pattern 32 of
No connection to VH11, IVH11 and IVH
The insulation between 12 and 12 is established.
【0016】以上のように、本実施例においては誤った
層編成では、2個のIVHを1組とする組合せのうちで
内層チェックパターン32〜35で導通されない組が、
少なくとも1組生じることになり、この実施例では上記
複数のIVH11〜15のうちIVH11とIVH15
との間を、例えば抵抗検知器で導通試験を行うことによ
り、正規の層編成にあるか否かが確認できることにな
る。As described above, in the present embodiment, in the wrong layer formation, among the combinations having two IVHs as one set, the set which is not conducted by the inner layer check patterns 32 to 35 is
At least one set is generated, and in this embodiment, IVH11 and IVH15 among the plurality of IVHs 11 to 15 are generated.
By conducting a continuity test with a resistance detector, for example, it is possible to confirm whether or not there is a regular layer knitting.
【0017】また図2は本発明に係る他の実施例の断面
図であり、この実施例においては、内層チェックパター
ン32〜35を上記各基板の図1に示す実施例と同じ位
置に設ける一方、5本のIVH11〜15は表層基板1
a側の回路パターン領域外から穿設している。従って、
図2(a) に示す正規の層編成の場合では、全てのIVH
11〜15が内層チェックパターン32〜35により電
気的に接続されていることになる。FIG. 2 is a sectional view of another embodiment according to the present invention. In this embodiment, inner layer check patterns 32 to 35 are provided at the same positions as those of the embodiment shown in FIG. The five IVHs 11 to 15 are surface layers 1
The holes are formed from outside the circuit pattern region on the a side. Therefore,
In the case of regular layer formation shown in Fig. 2 (a), all IVH
11 to 15 are electrically connected by the inner layer check patterns 32 to 35.
【0018】一方、図2(b) に示すように内層基板2と
内層基板3とを誤って入れ替えて積み重ねた場合には、
正規の層編成ではIVH11とIVH12との間を接続
する内層チェックパターン32は、IVH11と接続し
ないことになり、IVH11とIVH12との間が絶縁
され、IVH11とIVH15との間は不導通となる。On the other hand, as shown in FIG. 2 (b), when the inner layer substrate 2 and the inner layer substrate 3 are mistakenly replaced and stacked,
In the regular layer formation, the inner layer check pattern 32 connecting between IVH11 and IVH12 is not connected to IVH11, so that IVH11 and IVH12 are insulated and IVH11 and IVH15 are not electrically connected.
【0019】尚、上記2つの実施例においては、各基板
の積み重ね順を誤った場合だけを例示したが、例えば同
じ基板を重複して積み重ねた場合でも、上記内層チェッ
クパターンの板厚方向の位置は正規の層編成の位置から
ずれることになり、隣接する2本のIVHからなる組み
合わせのうち電気的に接続されない組み合わせを生じる
ことになるので、上記と同様に層編成のチェックができ
ることになる。In the above two embodiments, only the case where the stacking order of the respective substrates is wrong is illustrated. However, even when the same substrates are stacked in duplicate, the position of the inner layer check pattern in the plate thickness direction will be described. Will shift from the position of the regular layer knitting, and a combination of two adjacent IVHs that is not electrically connected will be produced, so that the layer knitting can be checked in the same manner as described above.
【0020】さらに、上記実施例ではIVHは穿設深さ
順に横一列に配置しているが、これに限定されるもので
はなく、例えば環状に配置することも可能で内層チェッ
クパターンの形成位置との組合せに応じて任意とするこ
とができる。Further, in the above-mentioned embodiment, the IVHs are arranged in a horizontal row in the order of the drilling depth, but the invention is not limited to this. For example, the IVHs can be arranged in an annular shape and the position where the inner layer check pattern is formed. It can be arbitrary according to the combination of.
【0021】またさらに、上記層編成チェック用パター
ンは、上記実施例のように回路パターンの領域外に形成
することは必須ではなく、所期の回路設計の段階で上記
条件を満たす導体パターン及びIVHをパターン領域内
に形成しておき、層編成チェック用パターンとして利用
することもできる。Furthermore, it is not essential that the layer formation check pattern is formed outside the area of the circuit pattern as in the above embodiment, and the conductor pattern and IVH satisfying the above conditions at the stage of the intended circuit design. Can be formed in the pattern area and used as a layer knitting check pattern.
【0022】[0022]
【発明の効果】以上のように本発明によれば、多層プリ
ント配線板の層編成の正誤を肉眼でなく、電気的な導通
・不導通でチェックすることができるので、層編成の誤
りを以後の工程に移行する前に確実に発見することがで
きるので、工程ロスを低減することができる効果があ
る。As described above, according to the present invention, it is possible to check the correctness of the layer knitting of the multilayer printed wiring board by electrical conduction / non-conduction without the naked eye, so that the error of the layer knitting can be prevented. Since it can be surely found before shifting to the process of 1, there is an effect that the process loss can be reduced.
【図1】本発明に係る一実施例の断面図である。FIG. 1 is a sectional view of an embodiment according to the present invention.
【図2】本発明に係る他の実施例の断面図である。FIG. 2 is a sectional view of another embodiment according to the present invention.
【図3】従来例の斜視図である。FIG. 3 is a perspective view of a conventional example.
【図4】他の従来例の概念図である。FIG. 4 is a conceptual diagram of another conventional example.
1(1a,1b) 表層基板 2,3,… 内層基板 11,12,… IVH 32,33,… 内層チェックパターン 1 (1a, 1b) surface layer substrate 2, 3, ... inner layer substrate 11, 12, ... IVH 32, 33, ... inner layer check pattern
Claims (1)
の中間厚さ位置までの深さに穿設された複数のIVH(1
1),(12),…と、上記表層基板(1) 及び各内層基板(2),
(3),…の表面に形成された内層チェックパターン(32),
(33),…とからなり、 上記IVH(11),(12),…と内層チェックパターン(32),
(33),…とが、正規の層編成では、上記各内層チェック
パターン(32),(33),…が、順に異なるIVH(11),(12),
…で、他の唯一の内層チェックパターンに接続されるよ
うに配設された多層プリント配線板の層編成チェック用
パターン。1. The surface layer substrate (1) to each inner layer substrate (2), (3), ...
Of multiple IVHs (1
1), (12), ..., and the above surface layer substrate (1) and each inner layer substrate (2),
(3), inner layer check pattern formed on the surface of (32),
(33), ... and the above IVH (11), (12), ... and inner layer check pattern (32),
(33), ... In the regular layer knitting, the above-mentioned inner layer check patterns (32), (33), ... are different IVH (11), (12),
The pattern for checking the layer knitting of the multilayer printed wiring board arranged so as to be connected to the only other inner layer check pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4178653A JPH0621657A (en) | 1992-07-06 | 1992-07-06 | Checking pattern for layer organization of multilayer print wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4178653A JPH0621657A (en) | 1992-07-06 | 1992-07-06 | Checking pattern for layer organization of multilayer print wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0621657A true JPH0621657A (en) | 1994-01-28 |
Family
ID=16052229
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4178653A Withdrawn JPH0621657A (en) | 1992-07-06 | 1992-07-06 | Checking pattern for layer organization of multilayer print wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0621657A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101876687A (en) * | 2010-06-04 | 2010-11-03 | 深南电路有限公司 | A method for testing the back-drilling depth of a PCB board |
| JP2011240688A (en) * | 2010-05-21 | 2011-12-01 | Mitsubishi Electric Corp | Laminated structure |
| CN110267437A (en) * | 2019-06-27 | 2019-09-20 | 深圳市兴森快捷电路科技股份有限公司 | A kind of printed circuit board harmomegathus management-control method and device |
-
1992
- 1992-07-06 JP JP4178653A patent/JPH0621657A/en not_active Withdrawn
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011240688A (en) * | 2010-05-21 | 2011-12-01 | Mitsubishi Electric Corp | Laminated structure |
| CN101876687A (en) * | 2010-06-04 | 2010-11-03 | 深南电路有限公司 | A method for testing the back-drilling depth of a PCB board |
| CN101876687B (en) | 2010-06-04 | 2012-10-03 | 深南电路有限公司 | Test method for back drilling depth of PCB plate |
| CN110267437A (en) * | 2019-06-27 | 2019-09-20 | 深圳市兴森快捷电路科技股份有限公司 | A kind of printed circuit board harmomegathus management-control method and device |
| CN110267437B (en) * | 2019-06-27 | 2022-05-31 | 深圳市兴森快捷电路科技股份有限公司 | Printed circuit board expansion and shrinkage control method and device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6662441B2 (en) | Method for making multi-layer printed circuit board registration | |
| JP2503725B2 (en) | Multilayer wiring board | |
| EP0479986B1 (en) | A multi-layer printed circuit board and a method for assuring assembly in a selected order | |
| JPH0621657A (en) | Checking pattern for layer organization of multilayer print wiring board | |
| JP2734367B2 (en) | Multilayer printed wiring board and method of manufacturing the same | |
| JP2000340950A (en) | Accuracy check mark structure for multilayer matching on multilayer circuit board | |
| JP3206635B2 (en) | Multilayer printed wiring board | |
| JP2638555B2 (en) | Multilayer printed wiring board | |
| JP4737055B2 (en) | Multilayer printed wiring board | |
| JPH05226846A (en) | Checking method for deviation of inner layer of multilayer printed wiring board | |
| JPH1056272A (en) | Multi-layer printed wiring board | |
| JP5104874B2 (en) | Lamination sequence inspection method and wiring board manufacturing method | |
| JP2570619B2 (en) | Multilayer printed wiring board and method of manufacturing the same | |
| JPH10112587A (en) | Manufacture of ceramic multilayer substrate | |
| JPH08107280A (en) | Multilayer board having blind through hole and its manufacture | |
| JPH03250789A (en) | multilayer printed wiring board | |
| JPH0414951Y2 (en) | ||
| JPH04365395A (en) | Multi-layer board | |
| JPH10163631A (en) | Multi-layer printed circuit board and its manufacturing method | |
| JPH04337696A (en) | Manufacture of multilayer board | |
| JPH03123099A (en) | Method for detecting inner layer position of multilayer printed wiring board | |
| JP4291163B2 (en) | Manufacturing method of multilayer printed wiring board | |
| JPH04131971A (en) | How to design multilayer printed wiring boards | |
| CN101442901A (en) | Method for composing multilayer printed circuit board | |
| JPS59172294A (en) | Method of identifying layer structure of multilayer printed circuit board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19991005 |