JPH06232749A - A/d converter - Google Patents

Abstract

PURPOSE:To obtain the A/D converter with a small scale and high resolution by applying A/D conversion to an output of a variable gain amplifier, A/D- converting a gain control voltage fed back to the amplifier and synthesizing the A/D conversion outputs. CONSTITUTION:A 1st A/D converter 2 converts an analog output signal V0 amplified by a variable amplifier 1 into a digital signal D1. On the other hand, the analog output signal V0 is detected by a detector 4 and fed back to the variable gain amplifier 1 via a low pass filter 6 as a gain control signal. Then the fed-back gain control voltage SDET is converted into a digital signal D2 by a 2nd A/D converter 3. Moreover, a digital signal processing unit 7 synthesizes digital output signals D1, D2 of the 1st and 2nd A/D converters 2, 3 to output the digital signal D0.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter,
In particular, A / A that converts an analog signal, such as a voice signal, whose amplitude changes greatly at low speed compared to the main signal, into a digital signal
The present invention relates to a D converter.

[0002]

2. Description of the Related Art Conventionally, when the amplitude of an analog signal becomes small, the quantization error relatively increases. Therefore, in order to maintain the signal quality even when the analog signal has a small amplitude, an A / D of high precision and high resolution is used. Needed a converter.

Also, the higher the maximum frequency of the signal to be processed, the more it is necessary to use an A / D converter that operates at a higher speed. In terms of circuit configuration, the all-parallel A / D converter is the fastest.

A conventional A / D converter will be described with reference to the drawings.

FIG. 4 is a block diagram showing an example of a conventional A / D converter. This conventional A / D converter is shown in the AD converter described in Japanese Patent Application Laid-Open No. 1-106526.

In the 8-bit serial-parallel type A / D converter shown in FIG. 4, the first voltage comparators CC ₁ , ..., C are used.
C _j, ..., CC ₁₅ is made to correspond to 8-bit configuration are provided 15 and also resistor group RG ₁ constituting a first reference voltage generating means RG, ..., RG _j, ..., each of RG ₁₆ 16
Formed by a series-connected resistor, and the node between the resistors is connected to the first voltage comparator CC ₁ , ..., CC _j ,
..., CC ₁₅ respectively. The second voltage comparator group FC has a voltage comparator FC corresponding to an 8-bit configuration.
It is configured by providing 15 _n (n = 1, ..., 15). The switch control circuit SCC corresponds to an 8-bit configuration, and includes 16 switch groups S each including 15 switches.
_{G 1, ..., SG j,} ..., is constituted by SG _16.

In this A / D converter, the first parallel type A
A first determination circuit J ₁ of the D conversion unit 101 and a first encoder E ₁ for determining a connection relationship between them are provided.
The shifter SF, which is the connection determining means, is inserted.

Further, in the second parallel AD converter 2, two switch control circuits SCU and SCD are added in addition to the above-mentioned switch control circuit SCC, and these switch control circuits SCU, SCC and SCD are used to The second reference voltage generating means SC ₁ is configured.

Further, the above-mentioned second voltage comparator group FC
Separately from the above, two voltage comparator groups FCU and FCD configured by providing 15 voltage comparators FC _n are added, which generate a first reference voltage via switch control circuits SCU, SCC and SCD, respectively. It is connected to the means RG.

Switch control circuits SCU, SCC, SCD
Regarding the connection configuration between the first reference voltage generating means RG and the first reference voltage generating means RG, for example, when the first determination circuit J ₁ determines that the analog input voltage V _in exists between the reference voltages V ₁ and V _2. The switch control circuit SCC is connected to the 15 reference voltages of the resistor group RG _j corresponding to the reference voltage ranges V ₁ to V ₂ by the control signal from the determination circuit J _1, and the switch control circuit SCU is thereby provided with one group. Accordingly, the resistance group RG _{j + 1} on the high potential side and the switch control circuit SCD are respectively connected to 15 reference voltages of the resistance group RG _j-1 on the low potential side.

Therefore, in this case, the voltage comparator group FC
Each of the 15 voltage comparators FC _n of U, FC and FCD has a resistance group RG via the second reference voltage generating means SC _1.
It receives 15 levels of reference voltages obtained by _{j + 1} , RG _j and RG _j-1 .

In the second parallel AD converter 102, a second connection for determining the connection relationship between each voltage comparator group FCU, FC, FCD and the second determination circuit J ₂ is further provided. A selector SL, which is a determining means, is inserted. That is, the selector SL controls each voltage comparator group FC according to the control signal output from the error correction circuit EC described later.
One set of output line groups is selected from the three output line groups of 15 units each of U, FC, and FCD and is connected to the determination circuit J ₂ .

The error correction circuit EC is a switch control circuit S.
It is composed of C ₂ , third voltage comparators CE ₁ and CE _2, and a third judgment circuit J ₃ . Switch control circuit S
C ₂ is given from the first reference voltage generating means RG to the first voltage comparators CC ₁ , ..., CC _j , ..., CC ₁₅ according to the control signal output from the first judgment circuit J _1. 15
Two adjacent voltage levels are selected from the level reference voltages, and the selected two voltage levels are applied as reference voltages to the two third voltage comparators CE ₁ and CE ₂ provided for error correction. Two voltage comparators CE ₁ and CE
_2, for example, the first judging circuit J ₁ by the analog input voltage V _in is the reference voltage V _1, if it is determined that between V ₂ control signal corresponding to the determination result determining circuit J ₁ from the switch control circuit It is input to SC ₂ and, as a result, V is used as the reference voltage for the voltage comparators CE ₁ and CE ₂ for error correction.
₁ and V ₂ are selected.

Voltage comparators CE ₁ and CE ₂ for error correction
Compares the reference voltage selected as described above with the analog input voltage V _in, and compares the comparison result with the third value.
Is input to the judgment circuit J ₃ of the
And the selector SL. The connection operation of the shifter SF and the selector SL is determined depending on whether or not the determination results of the third determination circuit J ₃ and the first determination circuit J ₁ are different.

[0015]

In this conventional A / D converter, the circuit scale increases as the number of bits increases, and the accuracy is maintained due to an increase in reference voltage step relative error and variations in circuit constituent elements. It will be difficult. Further, in this A / D converter, the number of circuits for comparing the input voltage with the reference voltage needs to be doubled each time the resolution is increased by 1 bit. In other words, the circuit scale doubles as the number of bits increases, and the resolution is limited in terms of the feasible circuit scale. Also, as the circuit scale increases and the number of comparators connected in parallel to the analog signal input increases, the input capacitance also increases, so an operational amplifier circuit with a high load drive capability is required at the input to operate at high frequencies. There was a problem such as becoming.

[0016]

An A / D converter according to the present invention includes a variable gain amplifier which inputs an analog signal and variably amplifies it, and a first digital signal which converts an output of the variable gain amplifier into a first digital signal. Of the A / D converter, a control voltage feedback device for detecting the amplitude of the output of the variable gain amplifier, amplifying it, and then low-pass-filtering the gain control voltage, and feeding the gain control voltage to the variable gain amplifier. A second A / D converter for converting to a second digital signal, and a digital for synthesizing the first and second digital signals output from the first and second A / D converters by digital signal processing. And a signal processor.

The A / D converter of the present invention is a variable gain amplifier for inputting an analog signal and variably amplifying it, and a first A / D for converting an output of the variable gain amplifier into a digital signal.
A converter, a detector for detecting the output amplitude of the variable gain amplifier, a DC amplifier for amplifying the output of the detector, and an output of the DC amplifier is fed back to the variable gain amplifier via a low-pass filter. A second A / D converter for converting the gain control voltage to a digital signal, and a digital signal processing circuit for synthesizing the digital signals respectively output from the first and second A / D converters by digital signal processing. MSB ₀ is an intermediate digital value between the maximum allowable input analog signal digital value and the minimum input analog signal digital value of the variable gain amplifier, and the first A /
The digital value of the intermediate value between the digital value of the maximum allowable input analog signal of the D converter and the digital value of the minimum input analog signal is defined as MSB _1, and the digital values of the respective outputs of the first and second A / D converters. When the numerical values are D ₁ and D ₂ , the digital signal processor outputs the output digital numerical value D ₀ as D ₀ = MSB ₀ + (D ₁ −MSB ₁ ) × D _0.
It is output as a result of the digital signal processing.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

Referring to FIG. 1 showing an embodiment of the present invention, an A / D converter receives a variable gain amplifier 1 for inputting an analog signal V _a and variably amplifying it, and an output V ₀ of the variable gain amplifier 1. An A / D converter (hereinafter referred to as ADC) 2 for converting into a digital signal D ₁ , a detector 4 for detecting the amplitude of the output V ₀ of the variable gain amplifier 1, and a DC amplifier 5 for amplifying the output of this detector 4. , A low-pass filter 6 for filtering the low-frequency part of the output frequency of the DC amplifier 5, and a gain for feeding back the output of the DC amplifier 5 to the variable gain amplifier 1 via the low-pass filter 6. A digital signal processor for converting the control voltage S _DET into a digital signal D ₂ and the digital signals D ₁ and D ₂ output from the ADC 2 and ADC 3 respectively by digital signal processing to output a digital signal D ₀ (hereinafter DSP) 7 and

FIG. 2 shows an example of input / output waveforms of the main part in FIG. 1, (a) is _a waveform diagram of the analog input signal V _a of the variable gain amplifier 1, and (b) is a waveform of the output signal of the detector 4. FIG. 6C is a diagram showing changes in the relative gain G _a of the variable gain amplifier 1, and FIG. 7D is a waveform diagram of the output signal V ₀ of the variable gain amplifier 1.

FIG. 3 shows the ADCs 2, 3 and DS in FIG.
The digital value of the output of P7 is shown, (a) is a figure which shows the digital value of the output of ADC2, (b) is the figure which shows the digital value of the output of ADC3, (c) is the figure which shows the digital value of the output of DSP7 Is.

Next, the operation of this embodiment will be described with reference to FIGS. 1, 2 and 3. The analog signal V _a input to the variable gain amplifier 1 is the analog signal V _{a as it is.}
Is output as a gain control signal and is fed back to the variable gain amplifier 1 via the low-pass filter 6 as a gain control signal.

For example, when an analog signal V _a as shown in FIG. 2A is input, and the initial gain of the variable gain amplifier 1 is kept constant, the output of the detector 4 corresponds to the input amplitude. The waveform shown in (b) is obtained. Figure 3 in reality
Although the rising portion of the stepwise waveform in (b) is a more blunt waveform than shown, it is assumed in this embodiment that the amplitude change is slow with respect to the input analog signal frequency and the change time is sufficiently long. The blunting of the rising edge of the waveform is not a problem. It is schematically shown in FIG.

The output of the detector 4 is amplified by the DC amplifier 5 and fed back to the variable gain amplifier 1 via the low-pass filter 6 as a gain control signal, so that the output level of the variable gain amplifier 1 is ADC2. An automatic level control (ALC) circuit for controlling the level to be a predetermined level determined by the maximum allowable input level of 3 is configured.

The low-pass filter 6 is inserted to improve the gain versus phase margin of automatic control and increase the stability against oscillation etc., but its cutoff frequency is set sufficiently high with respect to the amplitude change speed. . The relative gain G _a of the variable gain amplifier 1 is shown in FIG.
By changing as shown in (c), the output waveform becomes as shown in (d) of FIG.

Therefore, the amplitude of the analog signal V ₀ output from the variable gain amplifier 1 is kept constant even when the amplitude of the input signal changes at a low speed, and therefore, when it is converted into a digital signal by the ADC 1. The signal-to-noise ratio due to the quantization error is also unchanged and kept constant.

That is, in the input analog signal V _a shown in FIG. 2A, the minimum width of the voltage change is 48α, which is twice the maximum 24α with respect to the difference α between 3α and 2α. Is the input limit value of ADC1, the resolution is 1/4
8. 1/96, which is half the normal accuracy, is required as the characteristic of ADC1.

On the other hand, in the present embodiment, as shown in FIG. 2D, the maximum amplitude change width 3γ-2γ = γ and the maximum amplitude 3γ × 2 = 6γ. Therefore, the resolution is 1/6. The accuracy is 1/21.

Therefore, the accuracy and resolution of the ADC 1 are the minimum necessary accuracy and resolution for obtaining a desired signal-to-noise ratio for a constant input amplitude, so that the parallel type A having a high maximum frequency of the input signal is used. Even when using the / D converter, it is possible to suppress the overall circuit scale.

Further, by converting the gain control signal fed back to the variable gain amplifier 1 into a digital signal by the ADC 2, the amplitude information of the input analog signal V _a can be encoded.

FIG. 3B shows digital output values of the ADC 2. This numerical value is proportional to the reciprocal of the relative gain of the variable gain amplifier 1 shown in FIG. If a variable gain amplifier whose gain changes linearly with respect to the gain control signal is used, it can be obtained by A / D converting the gain control signal itself. In the case of this embodiment, the analog input signal amplitude is twice the initial value, 4
Since it is a signal that doubles or 8 times and increases with time, the resolution was set to 1/8.

Since the gain of the variable gain amplifier 1 is continuously controlled, it is possible to increase the resolution as necessary. As the resolution is increased, it is possible to cope with a large variation range of the amplitude of the analog input signal, and a fine variation is possible. Can also be supported. That is, when the resolution is ⅛, the change in amplitude that can be handled is in eight steps, and small changes below that result in a rounding error.

Next, the digital signal processing of the DSP in this embodiment will be described in detail with reference to FIGS. 1, 2 and 3.

LSB _{1 in} FIG. 3 (a) represents the minimum unit level LSB (least significant bit) for the resolution of ADC1. In this embodiment, A
Since the resolution of DC1 is ⅙, the maximum value of the output digital numerical value corresponds to 6 times LSB1 and the median value MSB ₁ of the output digital numerical values corresponds to 3 times LSB ₁ .

Generally, the resolution of the A / D converter is often a binary number, but MSB _{1 of} this embodiment is a level at which the numerical value of the most significant digit MSB (most significant bit) in the case of a binary number changes. Corresponding to, the median value of the analog input signal level range of ADC1 (the intermediate value between the maximum value and the minimum value)
Is a digital value that is output when is input.

In FIG. 2D, 3γ × 2 = 6γ is converted to ADC1.
Assuming that the input voltage range is, when the analog signal of 3γ is input to the input minimum value, the output digital value is MSB ₁
Becomes If LSB ₁ is 1, MSB ₁ is 3.

FIG. 3B shows the output digital numerical value of the ADC 2 having a resolution of 1/8, the maximum value thereof is 8 times the minimum digital numerical value LSB ₂ , and the median value MSB ₂ is 4 times the LSB _2. . In FIG. 2B, 0 to 8β are converted to ADC
Assuming an input voltage range of 2, when inputting a median value of 4β,
The output digital value is MSB ₂ .

On the other hand, by operating the automatic level control so that the value of the output amplitude V ₀ of the variable gain amplifier 1 becomes the maximum input voltage range of the ADC 1, the influence of the quantization error on the signal to noise ratio is minimized. You can do it.

Now, assuming that the width between the minimum value and the maximum value of the output amplitude V ₀ is the constant value of 3γ × 2 = 6γ as shown in FIG. 2D, the automatic level control is operated. The width between the minimum value and the maximum value of the input signal V _a shown in FIG.
α × 2 = 6α, 6α × 2 = 12α, 12α × 2 = 24
When α, 24α × 2 = 48α, the relative gain of the variable gain amplifier 1 is 8 times, 4 times as shown in (c) of FIG.
It changes with double, double and single. Variable gain amplifier 1 at this time
The gain control signal of 1β, 2β, as shown in FIG.
If it changes to 4β, 8β, the output digital numerical value of ADC2 is 1, 2, 4, 8 like D ₂ shown in FIG.
In this case, the relative gain of the variable gain amplifier 1 is the reciprocal of G _a shown in (c) of FIG. 2 and corresponds to the signal amplitude of the analog input signal changing at a low speed.

On the other hand, the high-speed signal change component V _{0 obtained} by removing the low-speed amplitude change component from V _a by the automatic level control is A
Input to DC1 and output digital numerical value as shown in FIG.
D ₁ shown in is obtained. Here, the outputs D ₁ and A of ADC1
An output D ₂ Prefecture of DC2, DSP 7 is an analog input signal V _a, as a digital arithmetic processing for converting into a digital number output signal D _0, the D ₀ at time _{t (o) D 0 = MSB} 0 + (D 1 −MSB ₁ ) × D ₂ …… (1) Here, MSB ₀ has an analog input signal of V
_It represents an output digital numerical signal when _a has a median value (an intermediate value between the minimum value and the maximum value of the input voltage range).

For example, when the maximum amplitude of the analog input signal V _a is 24α × 2 = 48α and the minimum signal change width is 3α-2α = α as shown in FIG. 48 required. That is, in the present embodiment, it is necessary to divide the minimum value and the maximum value of the input voltage range into 48 and digitize them, and the output digital numerical value D _{0 has} a minimum value of 0 and a maximum value of LSB ₀ . Double, median MSB ₀ is LS
It is 24 times B ₀ . LSB ₀ represents the minimum level unit of the output numerical value corresponding to the amount of change of the input signal, α, and when LSB ₀ is 1, the output numerical value of D ₀ is ₀ to 48,
The MSB ₀ will be 24.

This value of 24 is the analog input signal V _a
When the amplitude changing at a low speed of is 3α on one side, G _a is 8 times,
3α × 8 = 24α, and when the amplitude of the analog input signal V _a is 24α on one side, G _a is 1 and 24α × 1 = 24α, which is 24 times the minimum input signal change width α. is doing. In other words, D ₁ has a maximum of 6,
Since D ₂ has a maximum value of 8, D ₀ has a maximum _value of 6 × 8
= 48 and the MSB ₀ is the median value of 0 and 48 24
Is.

On the other hand, in MSB ₁ , since the output median value of ADC ₁ is “3”, as a result, in this embodiment, D ₀ = 24 +
The _{(D 1 -3) × D 2} .

That is, in the present embodiment, the DSP 7 performs the arithmetic processing shown in the equation (1), so that the digital numerical value output corresponding to the input of the analog signal (V _a ) shown in FIG. It is obtained as the output of the DSP 7 as shown in (c).

Since the ADC 2 only needs to operate at a low speed corresponding to the amplitude change speed of the analog signal, a circuit structure of a successive approximation type or the like is used, and a small circuit structure can be achieved even with high resolution. Therefore, the circuit scale of the entire A / D conversion device can be suppressed to a circuit configuration in which the number of components is smaller than that of the conventional A / D conversion device.

[0046]

As described above, according to the present invention, a variable gain amplifier for inputting an analog signal and variably amplifying it, and a first A for converting an output of the variable gain amplifier into a digital signal.
/ D converter, a detector that detects the output amplitude of the variable gain amplifier, a DC amplifier that amplifies the output of this detector, and the output of this DC amplifier is fed back to the variable gain amplifier via a low-pass filter. A second A / D converter for converting the gain control voltage to a digital signal, and a digital signal processor for synthesizing the digital signals output from the first and second A / D converters by digital signal processing. By preparing,
As compared with the conventional parallel type A / D converter, the circuit scale can be reduced and a high-speed digital signal with high resolution can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a waveform diagram of a main part in FIG. 1, where (a) is an analog input signal of a variable gain amplifier, (b) is an output signal of a detector, and (c) is a change in relative gain of the variable gain amplifier.
(D) shows the output signals of the variable gain amplifier.

3A and 3B are diagrams showing digital numerical values of outputs of the ADC and the DSP in FIG. 1, where FIG. 3A is an output digital numerical value of the ADC2, and FIG. 3B is a digital numerical value of an output of the ADC3;
(C) shows digital numerical values of the output of the DSP 7, respectively.

FIG. 4 is a block diagram showing an example of a conventional A / D conversion device.

[Explanation of symbols]

1 Variable Gain Amplifier 2, 3 A / D Converter (ADC) 4 Detector 5 DC Amplifier 6 Low-pass Filter 7 Digital Signal Processor (DSP) 101 First Parallel AD Converter 102 Second Parallel Type AD converter RG First reference voltage generation means CC _j First voltage comparator J ₁ First determination circuit E ₁ First encoder SF shifter (first connection determination means) SC ₁ Second reference voltage generation Means FCU, FC, FCD Second voltage comparator group J ₂ Second determination circuit E ₂ Second encoder SL selector (second connection determining means) EC error correction circuit SC ₂ Switch control circuits CE ₁ , CE ₂ Third voltage comparator J ₃ Third determination circuit

Claims (4)

[Claims] 1. A variable gain amplifier which inputs an analog signal and variably amplifies it, a first A / D converter which converts an output of the variable gain amplifier into a first digital signal, and an output of the variable gain amplifier. And a second A / D for converting the gain control voltage into a second digital signal An A / D including a converter and a digital signal processor for synthesizing the first and second digital signals output from the first and second A / D converters by digital signal processing, respectively. Converter. 2. The control voltage feedback device includes a detector that detects the amplitude of the output of the variable gain amplifier, a DC amplifier that amplifies the output of the detector, and a low-pass filter that low-pass filters the output of the DC amplifier. An A / D converter according to claim 1, further comprising a bandpass filter. 3. The digital value of an intermediate value between the digital value of the maximum allowable input analog signal of the variable gain amplifier and the digital value of the minimum input analog signal is set to MSB _0, and the maximum value of the first A / D converter is set. Let MSB _{1 be} the digital value of the intermediate value between the digital value of the allowable input analog signal and the digital value of the minimum input analog signal, and let the digital values of the outputs of the first and second A / D converters be D ₁ and At D _2, the digital signal processor outputs its output digital value D ₀ as D ₀ = MSB ₀ + (D ₁ −
The A / D conversion device according to claim 1, wherein the A / D conversion device outputs the result as the result of the digital signal processing of MSB ₁ ) × D ₀ . 4. A variable gain amplifier for inputting an analog signal and variably amplifying it, a first A / D converter for converting an output of the variable gain amplifier into a digital signal, and detecting an output amplitude of the variable gain amplifier. And a DC amplifier for amplifying the output of this detector, and a second gain control voltage for returning the output of this DC amplifier to the variable gain amplifier via a low-pass filter and converting it to a digital signal. A / D converter,
A digital signal processing circuit for synthesizing digital signals respectively output from the first and second A / D converters by digital signal processing, and a digital value and a minimum input analog of a maximum allowable input analog signal of the variable gain amplifier. MSB of the digital value of the intermediate value with the digital value of the signal
_0, and the digital value of the intermediate value between the digital value of the maximum allowable input analog signal and the digital value of the minimum input analog signal of the first A / D converter is MSB ₁ .
When the digital values of the outputs of the first and second A / D converters are D ₁ and D ₂ , respectively, the digital signal processor outputs the output digital value D ₀ as D ₀ = MSB _0.
An A / D converter which outputs as a result of the digital signal processing of + (D ₁ -MSB ₁ ) × D ₀ .