JPH06233332A - Test signal generator for ccd camera signal processing circuit - Google Patents

Abstract

PURPOSE:To provide a test signal generator which produces the test signal needed for evaluation and control of a signal processing circuit that processes the image signals received from a CCD image pickup element. CONSTITUTION:The line memories MEN 111a-114b store the digital image signals whose image data on each pixel consists of the feed-through data and the signal output level data. The read outputs of the memories MEN 111a-114b are selected by a line selector LSL 12 for each line as the image data DT. These data DT are supplied to the D/A converters 21a and 21b and converted into the analog image signals. These image signals undergo the control of both amplitude and DC levels through an analog part ANL 3 and are transmitted as the test signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal generator for testing a CCD camera signal processing circuit for evaluating and adjusting a signal processing circuit of a video camera (CCD camera) using a CCD as an image pickup device.

[0002]

2. Description of the Related Art Conventionally, evaluation / adjustment of a CCD camera signal processing circuit has been performed by using an output signal from a CCD image pickup device as it is or using a pseudo signal from a test signal generation circuit.

FIG. 3 is a block diagram of an example of a test signal generator used in a pseudo signal evaluation method. Figure 3
As shown in FIG. 1, this signal generator is a phase adjuster (P
S) 16, a bias circuit (BIAS) 17 for biasing the output of the PS 16 with a predetermined voltage value, and the B
A blanking circuit (BLK) 18 for removing unnecessary signals included in the horizontal blanking period of the output of the IAS 17,
An amplifier (AM for adjusting the level of the output of this BLK18
P) 19.

[0004]

Since this signal generator generates a pseudo signal by shaping the pulse waveform of the system clock, the items that can be evaluated using this pseudo signal are circuit operation check and dynamic range check. Etc.

On the other hand, the above-mentioned other method using the output signal itself of the CCD image pickup device is excellent in that the supply signal to the signal processing circuit is almost the same as the actual operation mode, but in a completely different aspect. With difficulty. That is, since the development of the signal processing circuit is generally carried out in parallel with the development of the CCD camera, the CCD image pickup device itself which should supply the test signal to the prototype of the signal processing circuit is still in the prototype stage. It is not uncommon to find them in. The output signal from the image sensor in such a stage may include a defect.

Therefore, an object of the present invention is to generate a signal for a CCD camera signal processing circuit test which can generate a pseudo signal having a high degree of similarity with the output of a CCD image pickup device without restricting the kind and number of evaluation items. It is to provide a signal generator that does.

[0007]

SUMMARY OF THE INVENTION A signal generator for testing a CCD camera signal processing circuit according to the present invention uses an image of each pixel by first data representing a feedthrough level and second data representing a signal output level. A plurality of line memories in which digital image signals forming data are stored for each one line of horizontal scanning, and a selection unit for selecting a read output from the plurality of line memories in units of one line of the horizontal scanning, The digital / analog converting means for converting the output of the selecting means into an analog image signal, and the level adjusting means for adjusting the amplitude level and DC level of the output of the digital / analog converting means are provided.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

A signal generator for testing a CCD camera signal processing circuit according to an embodiment of the present invention, whose block diagram is shown in FIG. 1, is composed of two CCD elements each of which corresponds to one horizontal scanning line. A test signal equivalent to the output signal from the CCD image pickup device having the CCD array (so-called dual channel configuration) is generated.

As shown in FIG. 1, this signal generator comprises a digital section (DGT) 1 and a digital unit for converting digital image data from the DGT 1 into an analog image signal.
An analog (D / A) conversion unit (CNV) 2, an analog unit (ANL) 3 for adjusting the amplitude level and DC level of the analog image signal from CNV 2, and DGTs 1, C
It is composed of a sync signal generator (SYN) 5 and a clock pulse generator (CKG) 6 which supply sync signals to NV2 and ANL3 through a signal bus 4, respectively.

The DGT 1 includes a line memory group (LMG) 11 having a memory capacity for a plurality of CCD arrays,
And a line selector (LSL) 12. LMG11
Is eight line memories (MEM) 111a and 111b each capable of storing one horizontal scanning line of the image data including the first data indicating the feedthrough level and the second data indicating the signal output level. 112a, ... 114
b and an address unit (ADR) 115 for generating a read address signal to each of these MEMs.
The LSL 12 scans the data from the LMG 11 in the horizontal scan 1
Data selector (DTS) 12 that selects in units of lines
1 and a select signal generator (DEC) 122 that generates a line select signal that controls the selection operation of the DTS 121.
Composed of and.

The CNV2 is composed of two D / A converters 21a and 21b for converting the digital image data from the LSL 12 into an analog signal. The ANL 3 has two amplifiers (AM) for adjusting the amplitude levels of the analog image signals from the D / A converters 21a and 21b, respectively.
P) 41a and 41b, and two clamp circuits (CP) 42a and 42b for setting the DC levels of the outputs of the AMPs 21a and 41b, respectively.

Next, the operation of this embodiment will be described.

The SYN5 is driven in response to the clock pulse CLK supplied from the CKG6 through the signal bus 4, and the horizontal synchronizing signal HSYN generated by the SYN5 causes the ADR 115 to start counting. In response to the read address signal from the ADR 115, the MEMs 111a and 111b output image data for one horizontal scanning line. MEMs 112a / 112b, 113 in the LMG11
In a / 113b and 114a / 114b, image data for three lines subsequent to the image data for one line is stored.

Image data for four horizontal scanning lines from the MEMs 111a, 111b, ... And 114b are selected by the DTS 21 line by line in response to the line select signal and are supplied to the CNV2 as image data DT.

This image data DT is converted into a pair of analog image signals for one line by a pair of D / A converters 21a / 21b. The analog image signals from the D / A converters 21a / 21b are AMP31a / 31b and CP32a.
/ 32b adjusts the amplitude level and the DC level.

A pair of D / A converters (21a / 21b), AMPs (31a / 31b) and CPs (32a / 32b) are arranged in CNV2 and ANL3, respectively. This is because an output signal equivalent to that of a CCD image pickup device having a structure in which two CCD arrays are assigned per scanning line is generated.

MEMs 111a, 111b, ... And 11
Referring also to FIG. 2 which shows a timing diagram of the operation in one of the 4b, the clock pulses CLK are
A read clock pulse to each of the. Data A
Is data stored in the MEM 111a, and data B is M
Data A stored in EM111b are shown respectively, and data A
And the data B form image data for one horizontal scanning line.

Data A is a chain of memory data a,
Each of the memory data a is composed of field through data (FT data) representing a feed through level and signal output level data (signal level data) representing a signal output level. The FT data and the signal level data respectively correspond to one cycle of the clock pulse CLK, and the memory data a composed of the FT data 1 and the signal level data 1 shown in the figure correspond to one pixel of the image signal by the CCD image pickup device. Similarly, the memory data b is composed of FT data 2 and signal level data 2 and represents one pixel. Clock pulse CL for memory data a and b
Alternate pairs of MEM111a / 1 for each cycle of K
By reading from 11b, the image data output equivalent to the output of the CCD image pickup device having the above dual channel configuration is obtained.

The dual-channel CCD image pickup device in this embodiment can be replaced with a normal single-array CCD image pickup device. In that case, one D / A converter in CNV2 and one AMP and CP in ANL3 are all right.

When the number of pixels per horizontal scanning line of the pseudo image signal generated by the test signal generator is changed, the repetition frequency of the clock pulse CLK is set corresponding to the changed number of pixels, and the clock pulse is changed. Compatible SYN
And ADR counts are used. In addition, MEM111
If the a, 111b, ... And 114b are constituted by ROM, the image data can be changed by replacing the ROM, and if constituted by RAM, the image data can be changed by writing on the host computer side. You can also do it.

[0022]

As described above, the signal generator for testing the CCD camera signal processing circuit of the present invention stores the image signal necessary for the evaluation / adjustment of the signal processing circuit in the line memory and defines each pixel. Since image data for one horizontal scanning line is formed in the form of a chain of feedthrough data and signal output level data, a highly stable test signal, that is, a pseudo CCD image sensor output signal can be generated.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a timing diagram of the operation of the line memory in FIG.

FIG. 3 is a block diagram of a pseudo signal generator used in a conventional technique for evaluating a CCD camera signal processing circuit.

[Explanation of symbols]

1 Digital Section (DGT) 2 Digital / Analog Converter (CNV) 3 Analog Section (ANL) 4 Signal Bus 5 Synchronous Signal Generator (SYN) 6 Clock Pulse Generator (CKG) 11 Line Memory Group (LMG) 12 Line Selector (LSL) 16 Phase adjuster (PS) 17 Bias circuit (BIAS) 18 Blanking circuit (BLK) 19, 31a, 31b Amplifier (AMP) 21a, 21b Digital-analog converter (D /
A converter) 32a, 32b Clamp circuit (CP) 111a, 111b, 112a, 112b, 113a,
113b, 114a, 114b Line memory (MEM) 115 Address part (ADR) 121 Data selector (DTS) 122 Select signal generator (DEC) CLK Clock pulse DT Image data HSYN Horizontal sync signal

Claims (4)

[Claims] 1. A signal generator for generating a test signal for evaluating and adjusting a signal processing circuit for processing an image signal from a CCD image pickup device, the first data representing a feedthrough level and a signal output level. A plurality of line memories each storing a digital image signal that constitutes image data of each pixel by the second data for one line of horizontal scanning, and a read output from the plurality of line memories is one line of the horizontal scanning. A selection means for selecting in units of minutes, a digital / analog conversion means for converting the output of the selection means into an analog image signal, and a level adjusting means for adjusting the amplitude level and DC level of the output of the digital / analog conversion means. A signal generator, comprising: 2. The signal generator according to claim 1, wherein the level adjusting means comprises an amplifier for amplifying the analog image signal and a clamp circuit for controlling a direct current level of the output of the amplifier. 3. The signal generator according to claim 1, wherein the line memory is composed of a ROM. 4. The signal generator according to claim 1, wherein the line memory is composed of a RAM.