JPH06259891A - Device for reproducing recording medium - Google Patents

Abstract

PURPOSE:To accurately read digital data recorded in a magnetic tape. CONSTITUTION:Digital video data recorded in a magnetic tape 1 is reproduced by a magnetic head 2, and converted to digital data by an A/D converter 4. This digital data is viterbi-decoded by a viterbi-decoder 8, and synchronization is detected by a synchronization ID detector 9 from decoded data. An error counter 11 counts the number of occurrence of errors in synchronization detecting. A phase control circuit 12 controls sampling phase of the A/D converter 4 corresponding to a count value of the error counter 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording medium reproducing apparatus suitable for use in a digital video tape recorder.

[0002]

2. Description of the Related Art In a digital video tape recorder, it is considered that a video signal is digitized and recorded by a partial response class IV. The video data reproduced from the magnetic tape can be decoded using, for example, a Viterbi decoder.

By the way, when the data reproduced from such a magnetic tape is decoded by the Viterbi decoder, the reproduced signal is A / D converted by the A / D converter at a predetermined sampling rate.
Viterbi decoding may be performed using the D-converted and A / D-converted data. In such a case, if the sampling phase of the A / D converter is not correct,
When the data is decoded, the error rate becomes worse. The optimum point of this sampling phase changes due to variations in the characteristics of the magnetic tape and the magnetic head.

[0004]

However, in the conventional apparatus, since the sampling phase is adjusted at the stage of manufacturing the reproducing apparatus, there is a problem that the adjustment takes a long time. Further, since the value is fixed after being adjusted once, there is a problem that accurate data reading becomes difficult when different types of magnetic tapes are adopted.

The present invention has been made in view of such a situation, and makes it possible to read data accurately.

[0006]

A recording medium reproducing apparatus of the present invention reproduces information by a magnetic head 2 as reproducing means for reproducing information recorded on a magnetic tape 1 as a recording medium. A / D to A / D convert signals
A / D converter 4 as conversion means, error counter 11 as detection means for detecting the error rate of the signal output from A / D converter 4, and A corresponding to the detection result of error counter 11 And a phase control circuit 12 as a phase control means for controlling the sampling phase of the / D converter 4.

The phase control circuit 12 can control the sampling phase of the A / D converter 4 by the dichotomy method, for example.

[0008]

In the recording medium reproducing apparatus having the above structure, A /
The sampling phase of the D converter 4 is the error counter 1
The output of 1 is controlled by the phase control circuit 12. Therefore, adjustment for phase control becomes unnecessary, and even when the magnetic tape 1 is replaced with a different type, the data can always be read accurately.

[0009]

1 is a block diagram showing the configuration of an embodiment of a digital video tape recorder to which a recording medium reproducing apparatus of the present invention is applied. In this embodiment, the digital video data recorded on the magnetic tape 1 is reproduced by the magnetic head 2 and supplied to the A / D converter 4 and the PLL circuit 5 via the reproduction amplifier 3. There is. The clock generated by the PLL circuit 5 and the control signal output from the phase control circuit 12 are also supplied to the A / D converter 4.

The data output from the A / D converter 4 is
It is output to the sync ID detector 9 via the filter 6, the adaptive equalizer 7, and the Viterbi decoder 8. The data output from the sync ID detector 9 is further output to a circuit (not shown) via the time axis error correction circuit 10. Further, the detection signal output from the sync ID detector 9 is output to the error counter 11, and the output of the error counter 11 is output to the phase control circuit 12.

Next, the operation will be described.

The magnetic head 2 reproduces the digital video data recorded on the magnetic tape 1, and the reproduction amplifier 3
Amplifies this reproduction data to generate the PLL circuit 5 and A / D
Output to the converter 4. The PLL circuit 5 generates a clock from the input signal and uses the clock for the A / D converter 4
Supply to. The A / D converter 4 performs A / D conversion on the data input from the regenerative amplifier 3 in synchronization with the clock supplied from the PLL circuit 5.

The digital data sampled by the A / D converter 4 is input to the filter 6 and added with the sample value one clock before (after the processing of 1 + D is performed), and then the adaptive equalizer. 7 is output. Adaptive equalizer 7
Equalizes the input data into a waveform suitable for decoding in the Viterbi decoder 8 in the subsequent stage. The Viterbi decoder 8 decodes the input data according to, for example, the Ferguson algorithm. The data decoded by the Viterbi decoder 8 is input to the sync ID detector 9, and the sync and ID included in the data are detected. Sync ID
The data output from the detector 9 is input to the time axis error correction circuit 10 and, after the time axis error is corrected, an error detection / correction circuit (ECC circuit), a deframing circuit, a D / A conversion (not shown). It is finally output to a CRT or the like via a container or the like.

The sync ID detector 9 outputs a detection signal to the error counter 11 when the sync cannot be detected correctly. The error counter 11 counts this detection signal for a certain period (for example, one track), and outputs the count output to the phase control circuit 12. The phase control circuit 12 controls the sampling phase of the A / D converter 4 according to the count value input from the error counter 11. That is, the A / D converter 4 is
Corresponding to the control signal supplied from the phase control circuit 12,
The delay time of the data input from the regenerative amplifier 3 is controlled. As a result, the servo is applied such that the sampling phase in which the sync detection error rate in the sync ID detector 9 becomes the smallest.

FIG. 2 shows a more detailed configuration example of the phase control circuit 12. A counter (not shown) inputs to the counter 21 an increment signal generated at the beginning of a track or the beginning of a frame and a reset signal for resetting the count value at a predetermined timing. . The counter 21 counts the increment signal and outputs the count value i to the decoder 22. The decoder 22 has an internal RO
M is built in, and a control signal is output to each section according to the table written in the ROM. The data output from the error counter 11 (FIG. 1) is supplied to the register 23 or 24 via the switch 26 and stored therein. Comparator 25
Compares the values stored in the registers 23 and 24 and outputs the comparison result to the decoder 22.

Data stored in the register 23 or 24 is transferred to and stored in the register 29 via the switch 27. The data stored in the register 29 is supplied to the comparator 30 at the next sampling, and is compared with the data currently stored in the register 23 or 24 via the switch 28. The comparison result of the comparator 30 is supplied to the decoder 22.
The data output from the decoder 22 is output to the A / D converter 4 via the register 31.

The phase control circuit 12 of FIG. 2 is adapted to search for a sampling phase which minimizes the error rate of the sync by the dichotomy method. Next, the operation will be described with reference to the flowchart of FIG.

First, in step S1, i and X
An initial value of 0 or p0 is set in (0). That is, the value i of the counter 21 is initialized to 0, and the variable X (0) in the decoder 22 is set to the value p.
0 is initialized. Next, in step S2, for example, when an increment signal is generated at the beginning of the track, the counter 21 increments i by 1. When the count value i of the counter 21 is incremented, the decoder 22 performs the processing of steps S3 and S4,
In addition, the processes of steps S5 and S6 are executed at a predetermined timing.

That is, as shown in FIG. 4, the range for searching for the sampling phase having the minimum error rate is P
With (0) (for example, 0 radian) as the center, the range is P (-n) (for example, -π) on the left side and P (n) (for example, + π) for the right side. In other words, the sampling phase of the A / D converter 4 is from P (-n) to P (n).
In the range up to, it is variable in 2n + 1 steps in steps of Δp. As the initial value X (0) of the phase solution that minimizes the error rate, the phase positions P (-n) and P
An intermediate phase P (0) in the range of (n) is set. Then, in step S3, the position P (n / 2) of the sampling phase intermediate the tuning between P (0) and P (n) is the phase position R.
Is set as. This R is expressed by the following equation. R = X (0) + n × Δp / 2

Then, the error rate at the sampling phase position R is set to the variable ER in step S4.

That is, at the timing at the sampling phase position R, the decoder 22 switches the switch 26 shown in FIG. 2 to the upper side in the drawing, and the register 23 stores the error rate (count value of the error counter 11) at that time as ER. Remember.

Similarly, in step S5, P
Position L of the sampling phase intermediate between (-n) and P (0)
Is selected. That is, this position L can be expressed by the following equation. L = X (0) -n × Δp / 2

Then, in step S6, the error rate at the sampling phase position L is set to the variable EL.

That is, the decoder 22 switches the switch 26 to the lower side in FIG. 2 at the timing at the phase position EL, and stores the data supplied from the error counter 11 in the register 24 as EL.

Next, in step S7, step S4
And the values ER and EL fetched in S6 are compared. Since the values ER and EL are error rates, it is preferable that the values are small. Since the sampling phase position that minimizes this error rate is now being searched for, if the value ER is smaller than the value EL, step S
In step 8, the phase position of R is set in X (0). Now, this R is R = X (0) + n in step S3.
It is set to × Δp / 2. That is, in FIG. 4, the error rates EL and ER in the sampling phases L and R are
Among these, since it is determined that the error rate ER in R is smaller, the error rate is minimized in the vicinity of this sampling phase R, and the search for the next sampling phase is performed in that vicinity. is there.

Next, in step S9, it is determined whether or not the absolute value of E-ER is smaller than a preset allowable value ε. This variable E is set in step S11 which will be described later, and the ER at the previous sampling value is set. That is, in step S9, the difference between the error rate E obtained last time and the error rate ER obtained this time is preset (R of the decoder 22).
It is determined whether it is within the range of ε (stored in the OM).

When the absolute value of the difference between E and ER is within this range of ε, it means that the sampling phase that minimizes the error rate has been found, so the processing is terminated. E-
When the absolute value of ER is not within the range of ε, step S10
Then, it is determined whether 2 ⁱ is equal to n. That is,
As described above, since P (0) and P (n) are divided into n phase steps, when 2 ⁱ becomes equal to n, the error rate in all n sampling phases Will be compared. Therefore, in this case, the processing is ended. When 2 ⁱ is not equal to n, the process proceeds to step S11, and the error rate ER read in step S4 is set to the variable E. Then, the process returns to step S2 and the subsequent processing is repeated.

The processing in steps S8 to S11 is as follows.
The processing is performed when ER is smaller than EL. However, when EL is determined to be smaller than ER in step S7, in steps S12 to S15,
The same processing as in steps S8 to S11 described above is executed. That is, in this case, L is set to X (1) in step S12, it is determined in step S13 whether the absolute value of E-EL is smaller than ε, and 2 ⁱ is n in step S14. Is determined. Then, in step S15, EL is set to the variable E.

That is, the decoder 22 includes registers 23 and 2
The switch 27 is switched so as to select the smaller one of the values ER and EL stored in 4 and stored in the register 29 as the variable E (steps S11 and S15). Then, the switch 28 is switched so that the smaller one of the ER and EL stored in the registers 23 and 24 is selected and supplied to the comparator 30. Then, the comparator 30 receives the error rate E in the previous sampling stored in the register 29 and the smaller error rate ER or EL at the present time supplied via the switch 28.
And the comparison result ((E-ER) or (E-
EL)) is output to the decoder 22. The decoder 22
It is determined whether the value supplied from the comparator 30 is smaller than ε. Then, the above operation is repeated corresponding to the determination result.

In the first search shown in FIG. 4, EL
When it is determined that the ER is smaller, the second search is performed between P (0) and P (n) as shown in FIG. In this case, X (1) is an intermediate sampling phase position between P (0) and P (n). The intermediate sampling phase position between X (1) and P (n) is R, and the intermediate phase position between P (0) and X (1) is L.
It is said that Then, as in the case of the first time, the magnitudes of the error rates ER and EL at the sampling phase position R and the sampling phase position L are determined.

Since such processing is repeated, the kth
A schematic representation of the error rate search range for the second time is as shown in FIG. That is, in this case, X (k−1) −Δp × n / 2 ^k−1 and X (k−1)
Within + Δp × n / 2 ^k−1 , the phase position that minimizes the error rate is searched. The sampling phase position in the middle of the two tunes is X (k-1). Then, the phase position R becomes X (k−1) + Δp × n / 2 ^k , and the sampling phase position L becomes X (k−1) −Δp × n / 2 ^k .

As described above, when the difference between the error rate at the time of the previous search and the error rate at the time of the current search becomes a sufficiently small value (when it is within the range of ε), the phase position is changed. It is determined that the error rate has become the minimum. At this time, the decoder 22 outputs the signal corresponding to the phase position to the A / D converter 4 via the register 31.
Output to. The A / D converter 4 delays the input signal by the time corresponding to this control signal and performs sampling (A / D
Conversion). As a result, the sampling phase position of the A / D converter 4 is controlled to the phase position where the sync error rate in the sync ID detector 9 is minimized.

FIG. 7 shows a partial response class IV.
The eye pattern after (PRIV) adaptive equalization is shown.
The PRIV channel data has a value of -1, 0, or +1. However, as shown in FIG.
From the point (P (0)) to -π (P (-n)) or + π
It can be seen that as the sampling phase of A / D conversion shifts in the direction of (P (+ n)), the influence of noise increases, and the error rate deteriorates. That is, it can be seen that the error rate has one minimum value between −π and + π. In order to obtain this one local minimum value, the dichotomy is used in this embodiment.

This bisection method is a stable algorithm that surely converges within a finite time, does not require complicated calculation, and the hardware for realizing this is simply configured by a counter, a register, a comparator, and the like. can do. Further, since the number of searches or the termination condition of the search can be arbitrarily set, the accuracy and the time required for the search can be adjusted as necessary.

In the above embodiment, the error rate of the sync is used as the evaluation function, but it is also possible to use the error rate in the ECC circuit in the subsequent stage as the evaluation function.

As described above, by using the error rate as the evaluation function, it is possible to minimize the influence of noise from dropouts and other devices. In other words, for example, when the phase is controlled by using the deviation from the zero-cross point, some means for eliminating accidental factors such as dropout and noise from an external device is required. However, by using the error rate as the evaluation function in this manner, it is not necessary to adopt these special means.

In the above description, the case of recording data on a magnetic tape is taken as an example, but the present invention can be applied to the case of recording on a magnetic disk, an optical disk, a magneto-optical disk, or other recording medium. is there. Also, the data to be recorded can be data other than audio data and other video data.

[0038]

As described above, according to the recording medium reproducing apparatus of the first aspect, the sampling phase of the A / D conversion means is controlled in accordance with the error rate of the signal output from the A / D conversion means. By doing so, it is not necessary to adjust the phase at the time of manufacture, and it is possible to always read information accurately even when the type of recording medium is changed.

According to the recording medium reproducing apparatus of the second aspect, since the sampling phase of the A / D conversion means is controlled by the bisection method, the phase can be surely controlled with a simple structure. Is possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a digital video tape recorder to which a recording medium reproducing apparatus of the present invention is applied.

FIG. 2 is a block diagram showing a configuration example of a phase control circuit 12 in the embodiment of FIG.

FIG. 3 is a flowchart illustrating the operation of the embodiment of FIG.

FIG. 4 is a diagram illustrating a first process in the flowchart of FIG.

5 is a diagram illustrating a second process of the flowchart in FIG.

FIG. 6 is a diagram illustrating a k-th process in the flowchart of FIG.

FIG. 7 is a diagram illustrating an eye pattern.

[Explanation of symbols]

 1 magnetic tape 2 magnetic head 3 reproduction amplifier 4 A / D converter 5 PLL circuit 6 filter 7 adaptive equalizer 8 Viterbi decoder 9 sync ID detector 10 time axis error correction circuit 11 error counter 12 phase control circuit 21 counter 22 Decoder 23, 24 register 25 comparator 29 register 30 comparator 31 register

Claims (2)

[Claims] 1. A reproducing unit for reproducing information recorded on a recording medium, and A for A / D converting a signal reproduced by the reproducing unit.
A / D conversion means, a detection means for detecting an error rate of a signal output from the A / D conversion means, and a sampling phase of the A / D conversion means is controlled according to a detection result of the detection means. And a phase control means for controlling the recording medium reproducing apparatus. 2. The recording medium reproducing apparatus according to claim 1, wherein the phase control means controls a sampling phase of the A / D conversion means by a bisection method.